IDT70V17L20PFI [IDT]
Dual-Port SRAM, 32KX9, 20ns, CMOS, PQFP100, TQFP-100;
| 型号： | IDT70V17L20PFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 32KX9, 20ns, CMOS, PQFP100, TQFP-100 静态存储器 |
| 文件： | 总17页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
IDT70V17L
HIGH-SPEED 3.3V
32K x 9 DUAL-PORT
STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
◆
◆
– Commercial:15/20ns (max.)
– Industrial:20ns (max.)
Low-power operation
◆
◆
◆
◆
◆
– IDT70V17L
Active: 440mW (typ.)
Standby: 660µW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V17 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
◆
◆
Functional Block Diagram
R/WL
CE0L
CE1L
R/WR
CE
0
R
CE
1
R
OEL
OER
I/O
Control
I/O
Control
0-8L
I/O
0-8R
I/O
(1,2)
(1,2)
R
BUSY
L
BUSY
.
32Kx9
A
14L
0L
A
A
14R
0R
MEMORY
ARRAY
70V17
Address
Decoder
Address
Decoder
A
15
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE 0L
CE1L
CE0R
CE1R
OER
OE
L
R/WL
R/WR
SEM
INT
L
L
SEM
R
(2)
(2)
INT
R
M/S(1)
NOTES:
5643 drw 01
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
JUNE 2003
1
DSC-5643/1
©2003IntegratedDeviceTechnology,Inc.
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Description
The IDT70V17is a high-speed32Kx9Dual-PortStaticRAM. The for reads or writes to any location in memory. An automatic power
IDT70V17 is designed to be used as a stand-alone 288K-bit Dual-Port down feature controlled by the chip enables (either CE0 or CE1)
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit- permit the on-chip circuitry of each port to enter a very low standby
or-morewordsystem.UsingtheIDTMASTER/SLAVEDual-PortRAM power mode.
approach in 18-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete these devices typically operate on only 440mW of power.
logic. TheIDT70V17ispackagedina100-pinThinQuadFlatpack(TQFP).
This device provides two independent ports with separate control,
Fabricated using IDT’s CMOS high-performance technology,
address, and I/O pins that permit independent, asynchronous access
Pin Configurations(1,2,3)
06/12/03
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
NC
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
2
3
A
A
A
7L
8L
9L
A
A
A
A
A
A
A
A
7R
4
8R
5
9R
A
A
A
A
A
10L
11L
12L
13L
14L
6
10R
11R
12R
13R
14R
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT70V17PF
PN100-1
NC
NC
NC
NC
Vss
NC
NC
(4)
VDD
100-Pin
TQFP
Top View
NC
NC
NC
NC
CE0L
CE1L
(5
)
NC
NC
CE0R
CE1R
SEM
R/W
OE
Vss
Vss
NC
SEM
R/W
OE
L
L
L
R
R
R
Vss
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5643 drw 02
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Pin Names
Left Port
Right Port
Names
Chip Enables
CE0L, CE1L
R/W
OE
CE0R, CE1R
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
A0L - A14L
A
0R - A14R
I/O0L - I/O8L
I/O0R - I/O8R
Data Input/Output
Semaphore Enable
Interrupt Flag
SEM
INT
BUSY
L
SEM
INT
BUSY
M/S
R
L
R
Busy Flag
L
R
Master or Slave Select
Power (3.3V)
V
DD
Vss
Ground (0V)
5643 tbl 01
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Supply Voltage
Ground
Min.
Typ.
Max.
3.6
0
Unit
V
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
V
DD
ss
IH
IL
3.0
3.3
V
0
0
V
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
____
V
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3(2)
V
T
BIAS
____
V
-0.3(1)
0.8
V
TSTG
Storage
Temperature
5643 tbl 04
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
DC Output
Current
mA
IOUT
5643 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
CIN
VIN = 3dV
9
pF
COUT
VOUT = 3dV
10
pF
5643 tbl 05
NOTES:
Maximum Operating Temperature
andSupplyVoltage
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Grade
Ambient
GND
Vcc
Temperature(1)
Commercial
Industrial
0OC to +70OC
0V
0V
3.3V
3.3V
+
+
0.3V
0.3V
-40OC to +85OC
5643 tbl 03
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
3
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Truth Table I – Chip Enable(1,2)
CE
1
Mode
CE
CE0
VIL
VIH
Port Selected (TTL Active)
L
< 0.2V
>VDD -0.2V
X
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
VIH
X
VIL
H
(3)
>VDD -0.2V
X
(3)
X
<0.2V
5643 bl 06
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or >VDD-0.2V.
Truth Table II – Non-Contention Read/Write Control
Inputs(1)
Outputs
CE(2)
H
OE
X
X
L
SEM
H
R/W
I/O0-8
Mode
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselected: Power-Down
Write to Memory
L
H
L
H
X
H
Read Memory
X
H
X
Outputs Disabled
5643 tbl 07
NOTES:
1. A0L — A14L ≠ A0R — A14R
2. Refer to Chip Enable Truth Table.
Truth Table III – Semaphore Read/Write Control(1)
Inputs
Outputs
(2)
R/W
H
I/O0-8
Mode
CE
OE
L
SEM
L
H
DATAOUT
Read Semaphore Flag Data Out
Write I/O into Semaphore Flag
Not Allowed
H
L
X
L
DATAIN
0
↑
______
X
X
L
5643 tbl 08
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O8). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
4
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V17L
Max.
Symbol
|ILI
|ILO
Parameter
Test Conditions
DD = 3.6V, VIN = 0V to VDD
CE(2) = VIH, VOUT = 0V to VDD
OL = +4mA
OH = -4mA
Min.
Unit
µA
µA
V
(1)
___
|
Input Leakage Current
Output Leakage Current
Output Low Voltage
V
5
5
___
___
|
VOL
I
0.4
___
VOH
Output High Voltage
I
2.4
V
5643 tbl 09
NOTES:
1. At VDD < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)
70V17L15
Com'l Only
70V17L20
Com'l
& Ind
Unit
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(1) Max. Typ.(1) Max.
mA
IDD
Dynamic Operating
Current
(Both Ports Active)
L
L
L
L
L
L
L
L
L
L
145
235
135
135
35
205
220
55
CE = VIL, Outputs Disabled
SEM = VIH
(2)
___
___
IND
f = fMAX
mA
mA
mA
mA
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
40
70
CE
L
= CE
R
= VIH
= VIH
SEM
R
= SEM
L
(2)
___
___
35
65
f = fMAX
(4)
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND
100
155
90
140
150
3.0
3.0
135
145
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(2)
___
___
90
f=fMAX
,
SEM
R
= SEM
L
= VIH
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
L
and CE
R
> VDD - 0.2V,
COM'L
IND
0.2
3.0
0.2
0.2
90
V
IN > VDD - 0.2V or VIN < 0.2V, f = 0(3)
SEM = SEM > VDD- 0.2V
___
___
R
L
(4)
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
IND
95
150
CE"A" < 0.2V and CE"B" > VDD - 0.2V
SEM = SEM > VDD - 0.2V,
IN > VDD - 0.2V or VIN < 0.2V,
,
R
L
___
___
90
V
(2)
Active Port Outputs Disabled, f = fMAX
5643 tbl 10
NOTES:
1. DD = 3.3V, TA = +25°C, and are not production tested. IDDDC = 90mA (Typ.)
V
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
590Ω
590Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns Max.
1.5V
DATAOUT
BUSY
INT
DATAOUT
1.5V
30pF
5pF*
435Ω
435Ω
Figures 1 and 2
5643 tbl 11
5643 drw 03
5643 drw 04
Figure 1. AC Output Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
Waveform of Read Cycles(5)
t
RC
ADDR
(4)
t
t
AA
(4)
CE(6)
OE
ACE
(4)
t
AOE
R/W
(1)
t
OH
t
LZ
(4)
DATAOUT
VALID DATA
(2)
tHZ
BUSYOUT
(3,4)
BDD
5643 drw 05
t
Timing of Power-Up Power-Down
CE(6)
tPU
tPD
ICC
50%
50%
.
5643 drw 06
ISB
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
6
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V17L15
Com'l Only
70V17L20
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
15
15
20
20
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
t
t
10
12
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
10
10
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
____
____
____
____
t
15
20
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
10
____
____
t
Semaphore Address Access Time
15
20
ns
5643 tbl 12
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
70V17L15
Com'l Only
70V17L20
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
10
15
____
____
t
10
10
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
10
____
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
5643 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
7
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM(9,10)
(3)
(6)
(2)
t
WP
tAS
tWR
R/W
DATAOUT
DATAIN
(7)
t
OW
t
WZ
(4)
(4)
t
DH
tDW
5643 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
t
AW
CE or SEM(9,10)
(3)
(6)
(2)
tWR
tAS
tEW
R/W
DATAIN
tDW
tDH
5643 drw 08
NOTES:
1. R/W or CE = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus
for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
8
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
VALID ADDRESS
A0-A2
VALID ADDRESS
tAW
tWR
t
ACE
tEW
SEM
t
OH
t
DW
tSOP
OUT
DATA
DATAIN VALID
I/O
VALID(2)
tAS
tWP
tDH
R/W
tSWRD
t
AOE
OE
tSOP
Write Cycle
Read Cycle
5643 drw 09
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O8) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE "A"
R/W"A"
SEM"A"
t
SPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
5643 drw 10
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
9
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V17L15
Com'l Only
70V17L20
Com'l
& Ind
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min.
Max.
Min.
Max. Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
15
17
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
t
15
17
____
____
t
12
15
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
12
15
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
30
25
45
30
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5643 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
10
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)(2,4,5)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
5643 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
t
WB
BUSY"B"
(1)
tWH
(2)
R/W"B"
5643 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
11
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1,3)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
t
APS
CE"B"
t
BAC
tBDC
BUSY"B"
5643 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
(2)
t
APS
ADDR"B"
MATCHING ADDRESS "N"
t
BAA
tBDA
BUSY"B"
5643 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V17L15
70V17L20
Com'l Only
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
15
15
20
20
____
____
t
Interrupt Reset Time
ns
5643 tbl 15
12
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Waveform of Interrupt Timing(1,5)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(3)
(4)
t
AS
tWR
CE"A"
R/W"A"
INT"B"
(3)
t
INS
5643 drw 15
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
tINR
INT"B"
5643 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV — Interrupt Flag(1,4,5)
Left Port
Right Port
OE
R/WL
A14L-A0L
R/WR
A
14R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INTL
CE
R
R
INTR
(2)
L
L
X
X
L
X
X
X
L
7FFF
X
X
X
X
L
X
L
L
X
X
L
X
7FFF
7FFE
X
L
R
(3)
X
X
H
R
(3)
X
X
L
X
X
X
L
(2)
X
7FFE
H
X
X
L
5643 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Chip Enable Truth Table.
13
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Truth Table V —
Address BUSY Arbitration(4)
Inputs
Outputs
A
OL-A14L
(1)
(1)
A
OR-A14R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
MATCH
H
MATCH
(2)
(2)
(3)
Write Inhibit
5643 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V17 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D8
Left
D0
- D8
Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5643 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V17.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
TheIDT70V17providestwoportswithseparatecontrol,addressand (HEX),whereawriteisdefinedasCER=R/WR=VILpertheTruthTable.
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation Theleftportclearstheinterruptthroughaccessofaddresslocation7FFE
in memory. The IDT70V17 has an automatic power down feature when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port
controlled by CE. The CE0 and CE1 control the on-chip power down interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
circuitrythatpermitstherespectiveporttogointoastandbymodewhen 7FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread
not selected (CE = VIH). When a port is enabled, access to the entire thememorylocation7FFF.Themessage(9bits)at7FFEor7FFFisuser-
memoryarrayispermitted.
definedsinceitisanaddressableSRAMlocation.Iftheinterruptfunction
isnotused,addresslocations7FFEand7FFFarenotusedasmailboxes,
butaspartoftherandomaccessmemory.RefertoTruthTableIV forthe
interruptoperation.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)is assignedtoeachport. Theleftportinterrupt
flag(INTL)isassertedwhentherightportwritestomemorylocation7FFE
14
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
resultina glitchedinternalwrite inhibitsignalandcorrupteddata inthe
slave.
BusyLogic
Busy Logic provides a hardware indication that both ports of the
RAMhave accessedthe same locationatthe same time. Italsoallows
one of the two accesses to proceed and signals the other side that the
RAMis “Busy”.TheBUSY pincanthenbeusedtostalltheaccess until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe
event of an illegal or illogical operation. If the write inhibit function of
BUSYlogicis notdesirable,the BUSYlogiccanbedisabledbyplacing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pinoperates solelyas awriteinhibitinputpin.Normaloperationcanbe
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
Semaphores
TheIDT70V17is anextremelyfastDual-Port32Kx9CMOSStatic
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags alloweitherprocessoronthe leftorright
side ofthe Dual-PortRAMtoclaima privilege overthe otherprocessor
for functions defined by the system designer’s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other
shared resource.
The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
activityonthe leftportinnowayslows the access time ofthe rightport.
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE, the Dual-Port RAM enable, and SEM, the
semaphore enable. The CE and SEM pins control on-chip power
downcircuitrythatpermits the respective porttogointostandbymode
when not selected. This is the condition which is shown in Truth Table
III where CE and SEM are both HIGH.
TheBUSYoutputsontheIDT70V17RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
A15
CE
0
CE
0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSY
R
BUSY
L
BUSYL
CE1
CE1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
SystemswhichcanbestusetheIDT70V17containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
a performance increase offered by the IDT70V17s hardware sema-
phores,whichprovidealockoutmechanismwithoutrequiringcomplex
programming.
BUSY
L
BUSYL
BUSY
R
BUSY
R
.
5643 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70V17 RAMs.
Softwarehandshakingbetweenprocessors offers themaximumin
system flexibility by permitting shared resources to be allocated in
varyingconfigurations.TheIDT70V17doesnotuseitssemaphoreflags
to control any resources through hardware, thus allowing the system
designertotalflexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
Width Expansion with Busy Logic
Master/Slave Arrays
WhenexpandinganIDT70V17RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMsarraywill
receivea BUSYindication,andtooutputthatindication.Anynumberof
slavestobeaddressedinthesameaddressrangeasthemasterusethe
BUSY signal as a write inhibit signal. Thus on the IDT70V17 RAM the
BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and
theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)as shown
in Figure 3.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthis method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen
The BUSY arbitration on a master is based on the chip enable and
15
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
tothesamesemaphoreflagitwillfail,aswillbeverifiedbythefactthata
onewillbereadfromthatsemaphoreontherightsideduringsubsequent
read. Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap between the
read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continueuntilaoneiswrittentothesamesemaphorerequestlatch.Should
verifiesitssuccessinsettingthelatchbyreadingit. Ifitwassuccessful,it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
TheeightsemaphoreflagsresidewithintheIDT70V17inaseparate
memoryspacefromtheDual-PortRAM.Thisaddressspaceisaccessed
byplacingalowinputontheSEM pin(whichactsasachipselectforthe
semaphoreflags)andusingtheothercontrolpins(Address,CE,andR/
W)as theywouldbeusedinaccessingastandardStaticRAM.Eachof
the flags has a unique address which can be accessed by either side
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof
theotheraddresspinshasanyeffect.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
is written into an unused semaphore location, that flag will be set to a
zeroonthatside anda one onthe otherside (see TruthTable VI). That
semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
SEMAPHORE
READ
SEMAPHORE
READ
5643 drw 18
Figure 4. IDT70V17 Semaphore Logic
fromtheothersideispending)andthencanbewrittentobybothsides. theotherside’ssemaphorerequestlatchhavebeenwrittentoazeroin
The fact that the side which is able to write a zero into a semaphore themeantime,thesemaphoreflagwillflipovertotheothersideassoon
subsequently locks out writes from the other side is what makes asaoneiswrittenintothefirstside’srequestlatch.Thesecondside’sflag
semaphore flags useful in interprocessor communications. (A thor- willnowstayLOWuntilitssemaphorerequestlatchiswrittentoaone.From
ough discussion on the use of this feature follows shortly.) A zero this it is easy to understand that, if a semaphore is requested and the
written into the same location from the other side will be stored in the processor which requested it no longer needs the resource, the entire
semaphore request latch for that side until the semaphore is freed by systemcanhangupuntilaoneiswrittenintothatsemaphorerequestlatch.
the first side.
The criticalcase ofsemaphore timingis whenbothsides requesta
Whena semaphore flagis read, its value is spreadintoalldata bits single token by attempting to write a zero into it at the same time. The
so that a flag that is a one reads as a one in all data bits and a flag semaphore logic is specially designed to resolve this problem. If
containinga zeroreads as allzeros. The readvalue is latchedintoone simultaneous requests are made, the logic guarantees that only one
side’s output register when that side's semaphore select (SEM) and side receives the token. If one side is earlier than the other in making
output enable (OE) signals go active. This serves to disallow the the request, the first side to make the request will receive the token. If
semaphore from changing state in the middle of a read cycle due to a bothrequests arriveatthesametime,theassignmentwillbearbitrarily
write cycle from the other side. Because of this latch, a repeated read made to one port or the other.
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
A sequence WRITE/READ must be used by the semaphore in secure. As with any powerful programming technique, if semaphores
order to guarantee that no system level contention will occur. A are misused or misinterpreted, a software error can easily happen.
processor requests access to shared resources by attempting to write
Initialization of the semaphores is not automatic and must be
a zero into a semaphore location. If the semaphore is already in use, handled via the initialization program at power-up. Since any sema-
the semaphore request latch will contain a zero, yet the semaphore phore request flag which contains a zero must be reset to a one,
flag will appear as one, a fact which the processor will verify by the all semaphores on both sides should have a one written into them
subsequent read (see Table VI). As an example, assume a processor at initialization from both sides to assure that they will be free
writes a zero to the left port at a free semaphore location. On a when needed.
subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question.Meanwhile,ifaprocessorontherightsideattemptstowriteazero
16
IDT70V17L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 3.3V 32K x 9 Dual-Port Static RAM
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
100-pin TQFP (PN100-1)
15
20
Commercial Only
Speed in nanoseconds
Commercial & Industrial
L
Low Power
70V17 288K (32K x 9) Dual-Port RAM
5643 drw 19
PreliminaryDatasheet:
"PRELIMINARY'datasheetscontaindescriptionsforproductsthatareinearlyrelease.
DatasheetDocumentHistory:
06/12/03:
InitialDataSheet
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
408-284-2794
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
17
相关型号：
©2020 ICPDF网 联系我们和版权申明