IDT70V24L55G [IDT]
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM; HIGH -SPEED 3.3V 4K ×16双口静态RAM![IDT70V24L55G](http://pdffile.icpdf.com/pdf1/p00086/img/icpdf/IDT70V24L_454844_icpdf.jpg)
型号: | IDT70V24L55G |
厂家: | ![]() |
描述: | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
文件: | 总17页 (文件大小:280K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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IDT70V24S/L
HIGH-SPEED 3.3V
4K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• Devices are capable of withstanding greater than 2001V
electrostatic charge.
• On-chip port arbitration logic
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
• Full on-chip hardware support of semaphore signaling
between ports
— IDT70V24S
Active: 230mW (typ.)
• Fully asynchronous operation from either port
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 84-pin PGA, 84-pin PLCC, and 100-pin
TQFP
Standby: 3.3mW (typ.)
— IDT70V24L
Active: 230mW (typ.)
Standby: .66mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT70V24 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
DESCRIPTION:
The IDT70V24 is a high-speed 4K x 16 Dual-Port Static
RAM. The IDT70V24 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTER/SLAVE
FUNCTIONAL BLOCK DIAGRAM
R/
UB
W
L
L
R/
W
R
UB
R
LB
CE
OE
L
LB
CE
OER
R
L
R
L
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
(1,2)
BUSY (1,2)
L
BUSYR
A
11L
0L
A
11R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
0R
12
NOTES:
12
1. (MASTER):
BUSY is output;
(SLAVE): BUSY
is input.
2. BUSY outputs
and INT outputs
are non-tri-stated
push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/ W
L
CE
OE
R/W
R
L
R
L
R
SEM
R
SEM
L
INT (2)
R
INT(2)
L
M/S
2911 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
OCTOBER 1996
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
©1996 Integrated Device Technology, Inc.
DSC-2911/3
1
6.38
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
Dual-Port RAM for 32-bit-or-more word systems. Using the memory. An automatic power down feature controlled by CE
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or permits the on-chip circuitry of each port to enter a very low
wider memory system applications results in full-speed, error- standby power mode.
free operation without the need for additional discrete logic.
This device provides two independent ports with separate ogy, these devices typically operate on only 350mW of power.
control, address, and I/O pins that permit independent, The IDT70V24 is packaged in a ceramic 84-pin PGA, an
Fabricated using IDT’s CMOS high-performance technol-
asynchronous access for reads or writes to any location in 84-Pin PLCC, and a 100-pin Thin Quad Plastic Flatpack.
PIN CONFIGURATIONS(1,2)
INDEX
11 10
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
I/O8L
I/O9L
A
A
A
A
A
A
A
A
7L
6L
5L
4L
3L
2L
1L
0L
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O10L
I/O11L
I/O12L
I/O13L
GND
IDT70V24
J84-1
I/O14L
I/O15L
INT
L
F84-2
BUSY
L
V
CC
84-PIN PLCC/
FLATPACK
TOP VIEW
GND
I/O0R
I/O1R
I/O2R
GND
(3)
M/S
BUSY
R
INT
R
VCC
A
A
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
1R
2R
3R
4R
5R
6R
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
2911drw 02
Index
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
N/C
N/C
N/C
1
N/C
N/C
N/C
N/C
75
74
2
3
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N/C
4
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
5
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT70V24
PN100-1
INTL
BUSY
GND
M/S
BUSY
INTR
VCC
L
GND
I/O0R
I/O1R
I/O2R
100-PIN
TQFP
TOP VIEW
(3)
R
VCC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
1R
2R
3R
4R
N/C
N/C
N/C
N/C
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2911 drw 03
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the actual part marking.
6.38
2
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D)(1,2)
63
I/O7L
61
I/O5L
60
I/O4L
58
I/O2L
55
I/O0L
54
51
48
46
45
42
11
10
09
08
07
06
05
04
03
02
01
A
11L
A
10L
A
7L
5L
OE
L
SEM
L
LBL
66
I/O10L
64
I/O8L
62
I/O6L
59
I/O3L
56
I/O1L
49
50
47
44
43
40
N/C
A
9L
A
8L
6L
3L
0L
A
UB
L
CEL
67
I/O11L
65
I/O9L
68
I/O12L
71
I/O14L
70
57
53
52
41
39
R/W
L
GND
V
CC
A
A
4L
2L
69
I/O13L
38
37
A
A
72
I/O15L
73
33
35
34
BUSY
L
A
VCC
INT
L
IDT70V24
G84-3
75
I/O0R
74
32
31
36
GND
GND
M/S
GND
A
1L
84-PIN PGA
TOP VIEW
(3)
76
I/O1R
77
I/O2R
80
I/O4R
83
I/O7R
78
28
29
30
V
CC
A
0R
INT
R
BUSY
R
79
I/O3R
26
27
A
2R
5R
A
1R
3R
81
I/O5R
7
11
12
23
25
SEM
R
A
GND
GND
A
82
I/O6R
1
2
5
8
10
14
17
20
18
22
24
I/O9R
I/O10R I/O13R I/O15R R/W
15
R
A
11R
A
8R
A
6R
9R
A
4R
7R
UB
R
84
I/O8R
3
4
6
9
13
16
19
21
I/O11R I/O12R I/O14R
N/C
A
10R
A
A
OER
LB
R
CER
A
B
C
D
E
F
G
H
J
K
L
2911 drw 04
Index
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate the actual part-marking.
PIN NAMES
Left Port
Right Port
CER
Names
Chip Enable
CEL
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
A0L – A11L
I/O0L – I/O15L
SEML
A0R – A11R
I/O0R – I/O15R
SEMR
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
UBL
UBR
LBL
LBR
INTL
INTR
BUSYL
BUSYR
M/S
VCC
Master or Slave Select
Power
GND
Ground
2911 tbl 1
6.38
3
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
R/W
X
OE UB
LB
X
H
H
L
SEM
H
I/O8-15
I/O0-7
High-Z
High-Z
High-Z
Mode
Deselected: Power Down
H
X
X
X
X
X
L
X
H
L
High-Z
High-Z
DATAIN
High-Z
X
X
H
Both Bytes Deselected
Write to Upper Byte Only
L
L
H
L
L
H
L
H
DATAIN Write to Lower Byte Only
L
L
L
H
DATAIN DATAIN Write to Both Bytes
DATAOUT High-Z Read Upper Byte Only
L
H
H
H
X
L
H
L
H
L
L
H
L
H
High-Z DATAOUT Read Lower Byte Only
DATAOUT DATAOUT Read Both Bytes
L
X
L
L
H
H
X
X
X
HighZ
High-Z
Outputs Disabled
NOTE:
2911 tbl 02
1. A0L — A11L ≠ A0R — A11R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
CE
H
R/W
H
OE
UB
X
LB
X
SEM
I/O8-15
I/O0-7
Mode
L
L
L
L
L
L
L
L
DATAOUT DATAOUT Read Data in Semaphore Flag
DATAOUT DATAOUT Read Data in Semaphore Flag
DATAIN DATAIN Write DIN0 into Semaphore Flag
DATAIN DATAIN Write DIN0 into Semaphore Flag
X
H
H
X
H
X
H
X
X
X
X
X
H
L
H
X
L
L
X
X
—
—
—
—
Not Allowed
Not Allowed
X
L
NOTE:
2911 tbl 03
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC OPERATING
Symbol
Rating
Commercial Unit
CONDITIONS
(2)
Symbol
Parameter
Min. Typ. Max. Unit
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +4.6
V
VCC
Supply Voltage
3.0
0
3.3
0
3.6
0
V
V
V
V
GND
VIH
Supply Voltage
TA
Operating
Temperature
0 to +70
°C
Input High Voltage
Input Low Voltage
2.0
-0.3(1)
—
—
Vcc+0.3
0.8
VIL
TBIAS
TSTG
IOUT
Temperature
Under Bias
–55 to +125 °C
–55 to +125 °C
NOTES:
2911 tbl 06
1. VIL≥ -1.5V for pulse width less than 10ns.
Storage
Temperature
2. VTERM must not exceed Vcc + 0.5V.
DC Output
Current
50
mA
CAPACITANCE(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
NOTES:
2911 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc +0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to < 20ma for the period over VTERM > Vcc
+ 0.5V.
Symbol
CIN
Parameter
Conditions(2) Max. Unit
Input Capacitance
VIN = 3dV
9
pF
pF
COUT
Output
Capacitance
VOUT = 3dV
11
NOTES:
2911 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade
Temperature
GND
VCC
Commercial
0°C to +70°C
0V
3.3V ± 0.3
2911 tbl 05
6.38
4
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V)
IDT70V24S
IDT70V24L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 3.6V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
IOL = 4mA
Min.
Max.
10
Min.
—
Max.
5
Unit
µA
µA
V
|ILI|
—
—
|ILO|
VOL
VOH
10
—
5
—
0.4
—
—
0.4
—
Output High Voltage
IOH = -4mA
2.4
2.4
V
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
2911 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V ± 0.3V)
70V24X25
70V24X35
70V24X55
Test
Symbol
Parameter
Condition
Version
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
COM.
S
L
80
80
140
120
70
70
115
100
70
70
115
100
mA
(3)
(Both Ports Active)
f = fMAX
ISB1
ISB2
Standby Current
(Both Ports — TTL
CER = CEL = VIH
SEMR = SEML = VIH
COM.
COM.
S
L
12
10
25
20
10
8
25
20
10
8
25
20
mA
mA
(3)
Level Inputs)
f = fMAX
(5)
Standby Current
(One Port — TTL
Level Inputs)
CE"A"=VIL and CE"B"=VIH
S
L
40
40
82
72
35
35
72
62
35
35
72
62
Active Port Outputs Open
(3)
f = fMAX
SEMR = SEML = VIH
ISB3
ISB4
Full Standby Current
(Both Ports — All
Both Ports CEL and
CER >VCC - 0.2V
COM.
COM.
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
mA
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC-0.2V
Full Standby Current
(One Port — All
CE"A" < 0.2 and
S
L
50
50
81
71
45
45
71
61
45
45
71
61
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
SEMR = SEML > VCC-0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port
Outputs Open,
(3)
f = fMAX
NOTES:
2911 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICC DC = 70mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.38
5
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns Max.
1.5V
1.5V
Figures 1 and 2
2911 tbl 10
3.3V
3.3V
590Ω
590Ω
DATAOUT
BUSY
INT
DATAOUT
435Ω
30pF
435Ω
5pF
2911 drw 05
Figure 1. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V24X25
IDT70V24X35
IDT70V24X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
tAA
Read Cycle Time
25
—
—
—
—
3
—
25
25
25
15
—
—
15
—
25
—
35
35
—
—
—
—
3
—
35
35
35
20
—
—
20
—
35
—
45
55
—
—
—
—
3
—
55
55
55
30
—
—
25
—
50
—
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time(3)
Byte Enable Access Time(3)
tACE
tABE
tAOE
tOH
tLZ
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
3
3
3
tHZ
—
0
—
0
—
0
tPU
tPD
—
15
—
—
15
—
—
15
—
tSOP
tSAA
ns
NOTES:
2911 tbl 11
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
TIMING OF POWER-UP POWER-DOWN
CE
t
PU
t
PD
I
CC
SB
50%
50%
I
2911 drw 06
6.38
6
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
(4)
tABE
UB, LB
R/W
tOH
(1)
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3, 4)
2911 drw 07
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted firs CE, OE, LB, or UB.
3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT70V24X25 IDT70V24X35
IDT70V24X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tEW
Write Cycle Time
Chip Enable to End-of-Write(3)
25
20
20
0
—
—
—
—
—
—
—
15
—
15
—
—
—
35
30
30
0
—
—
—
—
—
—
—
20
—
20
—
—
—
55
45
45
0
—
—
—
—
—
—
—
25
—
25
—
—
—
ns
ns
tAW
Address Valid to End-of-Write
Address Set-up Time(3)
ns
tAS
ns
tWP
Write Pulse Width
20
0
25
0
40
0
ns
tWR
Write Recovery Time
ns
tDW
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
—
0
20
—
0
30
—
0
ns
tHZ
ns
tDH
ns
tWZ
—
0
—
0
—
0
ns
tOW
ns
tSWRD
tSPS
NOTES:
5
5
5
ns
5
5
5
ns
2911 tbl 12
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW
time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).
6.38
7
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM (9)
UB or LB (9)
(3)
(2)
(6)
t
WR
t
AS
tWP
R/
W
(7)
t
OW
t
WZ
(4)
(4)
DATAOUT
DATAIN
t
DW
tDH
2911 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9)
UB or LB (9)
(6)
AS
(3)
WR
(2)
EW
t
t
t
R/W
t
DW
tDH
DATAIN
2911 drw 09
NOTES:
1. R/W or CE or UB & LB must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a Low UB or LB and a Low CE and a Low R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM Low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.Transitionismeasured±200mVfromLoworHigh-impedancevoltage
with Output Test Load (Figure 2).
8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW
time.
6.38
8
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tOH
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
WR
t
ACE
tAW
t
EW
SEM
tSOP
t
DW
DATAIN
VALID
DATAOUT
I/O0
(2)
VALID
tAS
tWP
t
DH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2911 drw 10
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
“A”
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
“B”
R/W"B"
SEM"B"
2911 drw 11
NOTES:
1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/WA or SEMA going High to R/WB or SEMB going High.
4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag.
6.38
9
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT70V24X25
IDT70V24X35
IDT70V24X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Low
BUSY Disable Time from Chip High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
—
—
—
—
5
25
25
25
25
—
35
—
—
—
—
—
5
35
35
35
35
—
35
—
—
—
—
—
5
45
45
45
45
—
40
—
ns
ns
ns
ns
ns
ns
ns
—
20
—
25
—
25
Write Hold After BUSY(5)
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
0
—
—
ns
ns
20
25
25
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
55
50
—
—
60
55
—
—
80
75
ns
tDDD
ns
NOTES:
2740 tbl 13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M / S= H)" or "Timing Waveform
of Write With Port-To-Port Delay (M / S = L)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. "X" in part numbers indicates power rating (S or L).
TIMING WAVEFORM OF READ WITH BUSY(M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
t
BAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
2911 drw 12
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".
6.38
10
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SLAVE WRITE (M/S = VIH)
t
WP
R/W"A"
(3)
t
WB
BUSY"B"
(1)
t
WH
R/
W"B"
(2)
2911 drw 13
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. Busy is asserted on port "B" Blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the "slave" version.
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(M/S = VIH)(1)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
t
BAC
tBDC
BUSY"B"
2911 drw 14
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDRESS "N"
ADDR"A"
ADDR"B"
(2)
t
APS
MATCHING ADDRESS "N"
t
BAA
tBDA
BUSY"B"
2911 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
6.38
11
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT70V24X25
IDT70V24X35
IDT70V24X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
0
—
—
25
30
0
0
—
—
30
35
0
0
—
—
40
45
ns
ns
ns
tWR
tINS
Write Recovery Time
Interrupt Set Time
—
—
—
—
—
—
tINR
Interrupt Reset Time
ns
NOTE:
2911 tbl 14
1. "X" in part numbers indicates power rating (S or L).
WAVEFORM OF INTERRUPT TIMING(1)
t
WC
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A"
(3)
AS
(4)
t
tWR
R/W"A"
INT"B"
(3)
INS
t
2911 drw 16
t
RC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
INR
t
INT"B"
2911 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal ( CE or R/W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/W ) is de-asserted first.
TRUTH TABLES
TRUTH TABLE III — INTERRUPT FLAG(1)
Left Port
Right Port
OER A11R-A0R INTR
R/WL
CEL
L
OEL A11L-A0L INTL
R/WR
CER
X
Function
Set Right INTR Flag
L
X
X
X
L
FFF
X
X
X
L(3)
H(2)
X
X
L
X
L
X
L(2)
H(3)
X
X
X
L
FFF
FFE
X
Reset Right INTR Flag
Set Left INTL Flag
X
X
X
X
L
X
X
L
FFE
X
X
X
Reset Left INTL Flag
NOTES:
2911 tbl 15
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
6.38
12
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION
Inputs
Outputs
A0L-A11L
CER A0R-A11R BUSYL
(1)
(1)
CEL
X
BUSYR
Function
Normal
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
Normal
X
MATCH
H
H
Normal
Write Inhibit(3)
L
MATCH
(2)
(2)
NOTES:
2911 tbl 16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V24 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
NOTES:
2911 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V24.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
The IDT70V24 provides two ports with separate control,
addressandI/Opinsthatpermitindependentaccessforreads
or writes to any location in memory. The IDT70V24 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE High). When a port is enabled, access to the entire
memory array is permitted.
memory location FFF (HEX) and to clear the interrupt flag
(INTR), therightportmustreadthememorylocationFFF. The
message (16 bits) at FFE or FFF is user-defined, since it is an
addressable SRAM location. If the interrupt function is not
used, address locations FFE and FFF are not used as mail
boxes, but as part of the random access memory. Refer to
Truth Table for the interrupt operation.
BUSY LOGIC
INTERRUPTS
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signalstheothersidethattheRAMis“Busy”. Thebusypincan
thenbeusedtostalltheaccessuntiltheoperationon theother
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
If the user chooses to use the interrupt function, a memory
location(mailboxormessagecenter)isassignedtoeachport.
Theleftportinterruptflag(INTL)isassertedwhentherightport
writestomemorylocationFFE(HEX), whereawriteisdefined
as the CE=R/W=VIL per the Truthe Table. The left port clears
the interrupt by accessing address location FFE when
CER=OER=VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to
6.38
13
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BUSY
L
BUSY
R
BUSY
L
BUSY
R
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY
R
BUSY
L
BUSYL
BUSY
R
BUSYR
BUSY
L
2911 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V24 RAMs.
to observe this timing can result in a glitched internal write
applications. In some cases it may be useful to logically OR
inhibit signal and corrupted data in the slave.
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/Spin. Once in slave mode theBUSY
pin operates solely as a write inhibit input pin. Normal opera-
tion can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 70V24 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
SEMAPHORES
The IDT70V24 is an extremely fast Dual-Port 4K x 16
CMOS Static RAM with an additional 8 address locations
dedicatedtobinarysemaphoreflags. Theseflagsalloweither
processorontheleftorrightsideoftheDual-PortRAMtoclaim
a privilege over the other processor for functions defined by
the system designer’s software. As an example, the sema-
phore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
oftherightport. Bothportsareidenticalinfunctiontostandard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
anon-semaphorelocation. Semaphoresareprotectedagainst
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70V24 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70V24 RAM the busy pin
is an output if the part is used as a master (M/S pin = H), and
the busy pin is an input if the part used as a slave (M/S pin =
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busyononeothersideofthearray. Thiswouldinhibitthewrite
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enableandaddresssignalsonly.Itignoreswhetheranaccess
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiatedwitheithertheR/Wsignalorthebyteenables. Failure
Systems which can best use the IDT70V24 contain mul-
tiple processors or controllers and are typically very high-
speed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V24's hardware semaphores,
which provide a lockout mechanism without requiring com-
plex programming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT70V24 does
6.38
14
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
not use its semaphore flags to control any resources through data bits so that a flag that is a one reads as a one in all data
hardware, thus allowing the system designer total flexibility in bits and a flag containing a zero reads as all zeros. The read
system architecture.
valueislatchedintooneside’soutputregisterwhenthatside's
An advantage of using semaphores rather than the more semaphore select (SEM) and output enable (OE) signals go
common methods of hardware arbitration is that wait states active. This serves to disallow the semaphore from changing
are never incurred in either processor. This can prove to be state in the middle of a read cycle due to a write cycle from the
a major advantage in very high-speed systems.
other side. Because of this latch, a repeated read of a
semaphoreinatestloopmustcauseeithersignal(SEMorOE)
to go inactive or the output will never change.
HOW THE SEMAPHORE FLAGS WORK
A sequence WRITE/READ must be used by the sema-
phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema-
phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
andtheothersidehigh. Thisconditionwillcontinueuntilaone
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provideahardwareassistforauseassignmentmethodcalled
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthesharedresource. Ifitwasnotsuccessfulinsettingthe
latch, it determines that the right side processor has set the
latchfirst, hasthetokenandisusingthesharedresource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT70V24 in
a separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
eithersidethroughaddresspinsA0–A2. Whenaccessingthe
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flagwillbesettoazeroonthatsideandaoneontheotherside
(see Table III). That semaphore can now only be modified by
thesideshowingthezero. Whenaoneiswrittenintothesame
locationfromthesameside,theflagwillbesettoaoneforboth
sides (unless a semaphore request from the other side is
pending)andthencanbewrittentobybothsides.Thefactthat
the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica-
tions. (Athoroughdiscussingontheuseofthisfeaturefollows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming tech-
When a semaphore flag is read, its value is spread into all
6.38
15
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
nique, if semaphores are misused or misinterpreted, a soft- into Semaphore 1. If the right processor performs a similar
ware error can easily happen. task with Semaphore 0, this protocol would allow the two
Initialization of the semaphores is not automatic and must processors to swap 2K blocks of Dual-Port RAM with each
be handled via the initialization program at power-up. Since other.
any semaphore request flag which contains a zero must be
The blocks do not have to be any particular size and can
reset to a one, all semaphores on both sides should have a even be variable, depending upon the complexity of the
one written into them at initialization from both sides to assure software using the semaphore flags. All eight semaphores
that they will be free when needed.
could be used to divide the Dual-Port RAM or other shared
resourcesintoeightparts.Semaphorescanevenbeassigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
ofmemoryduringatransferandtheI/Odevicecannottolerate
any wait states. With the use of semaphores, once the two
deviceshasdeterminedwhichmemoryareawas“off-limits”to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
applicationasresourcemarkersfortheIDT70V24’sDual-Port
RAM. Say the 4K x 16 RAM was to be divided into two 2K x
16 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
usedtoindicatethesidewhichwouldcontrolthelowersection
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 2K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were success-
fully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 2K. Mean-
while the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain
controlofthesecond2Ksectionbywriting,thenreadingazero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces-
sors can access their assigned RAM segments at full speed.
Another application is in the area of complex data struc-
tures. In this case, block arbitration is very important. For this
applicationoneprocessormayberesponsibleforbuildingand
updating a data structure. The other processor then reads
andinterpretsthatdatastructure. Iftheinterpretingprocessor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processortocomebackandreadthecompletedatastructure,
thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
2911 drw 19
Figure 4. IDT70V24 Semaphore Logic
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16
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
PF
G
J
100-pin TQFP (PN100-1)
84-pin PGA (G84-3)
84-pin PLCC (J84-1)
25
35
55
Speed in nanoseconds
S
L
Standard Power
Low Power
70V24 64K (4K x 16) 3.3V Dual-Port RAM
2911 drw 20
6.38
17
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