IDT70V25S35JI [IDT]
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM; 高速3.3V 8K ×16双口静态RAM
| 型号： | IDT70V25S35JI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
| 文件： | 总22页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
8K x 16 DUAL-PORT
STATIC RAM
IDT70V25S/L
Features
True Dual-Ported memory cells which allow simultaneous
◆
◆
IDT70V25 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
reads of the same memory location
High-speed access
◆
◆
– Commercial:15/20/25/35/55ns(max.)
– Industrial:20/25/35/55ns(max.)
Low-power operation
◆
◆
◆
◆
– IDT70V25S
Active:400mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V25L
◆
◆
◆
◆
Active:380mW(typ.)
Standby: 660µW (typ.)
Separate upper-byte and lower-byte control for multiplexed
◆
bus compatibility
Functional Block Diagram
WL
R/
R/WR
UBR
UBL
LBR
CER
OER
LBL
CEL
OEL
,
I/O8L-I/O15L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
I/O0L-I/O7L
(1,2)
BUSYL
(1,2)
BUSYR
A12R
A12L
A0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0R
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CER
OER
R/WR
CEL
OEL
R/WL
SEMR
INTR
SEML
INTL
(2)
(2)
M/S
2944 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
MAY 2000
1
DSC-2944/8
©2000IntegratedDeviceTechnology,Inc.
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typicallyoperate ononly400mWofpower.
The IDT70V25is a high-speed8Kx16Dual-PortStaticRAM. The
IDT70V25 is designed to be used as a stand-alone Dual-Port RAM or
as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or wider
memorysystemapplications results infull-speed, error-free operation
without the need for additional discrete logic.
This device provides two independent ports with separate control,
The IDT70V25 is packaged in a ceramic 84-pin PGA, an 84-Pin
PLCC and a 100-pin Thin Quad Flatpack.
Pin Configurations(1,2,3)
INDEX
11 10
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
8L
I/O
7L
6L
5L
A
A
A
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O9L
73
72
71
70
69
68
67
10L
I/O
I/O11L
12L
A4L
3L
A
2L
A
1L
A
I/O
I/O13L
GND
A0L
14L
I/O
15L
I/O
CC
V
IDT70V25J
(4)
INT
L
J84-1
66
65
64
63
62
61
60
59
58
57
56
55
54
BUSYL
GND
M/S
84-Pin PLCC
Top View
(5)
GND
0R
I/O
I/O1R
2R
BUSY
R
I/O
VCC
3R
INT
R
0R
A
I/O
I/O4R
A1R
2R
A
3R
A
4R
A
5R
A
6R
A
5R
I/O
6R
I/O
7R
I/O
8R
I/O
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
2944 drw 02
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
N/C
N/C
I/O10L
N/C
N/C
N/C
N/C
A5L
75
74
2
3
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4
5
11L
I/O
6
4L
A
3L
A
7
I/O12L
I/O13L
GND
8
A2L
1L
9
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O14L
0L
A
INTL
IDT70V25PF
PN100-1
15L
I/O
(4)
CC
V
GND
0R
I/O
I/O1R
I/O2R
BUSYL
GND
M/S
BUSYR
INTR
A0R
100-Pin TQFP
(5)
Top View
CC
V
I/O3R
4R
A1R
2R
A
I/O
5R
I/O
A3R
A4R
N/C
N/C
N/C
N/C
I/O6R
N/C
N/C
N/C
N/C
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
2944 drw 03
6.422
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
63
61
60
58
55
54
OEL
49
UBL
53
51
48
LBL
47
46
45
42
11
10
09
08
07
06
05
04
03
02
01
7L
10L
11L
13L
15L
0R
5L
4L
2L
0L
1L
11L
9L
10L
8L
7L
5L
I/O
I/O
I/O
I/O
I/O
SEML
A
A
A
66
64
62
59
56
50
CEL
52
44
43
40
8L
6L
3L
I/O
I/O
I/O
I/O
I/O
12L
A
A
A
A
67
65
57
41
39
L
R/W
CC
V
GND
I/O
9L
6L
3L
0L
I/O
A
4L
A
69
68
38
37
I/O
12L
I/O
A
2L
A
72
71
73
33
35
34
BUSYL
I/O
CC
14L
V
A
I/O
INTL
IDT70V25G
G84-3(4)
75
70
74
32
31
36
I/O
GND
GND
M/
S
GND
1L
A
84-Pin PGA
Top View(5)
76
77
78
28
29
30
CC
V
1R
I/O
2R
4R
7R
9R
0R
A
I/O
INTR
BUSYR
79
80
26
27
2R
A
3R
I/O
I/O
1R
A
81
83
7
11
12
23
25
SEMR
5R
I/O
5R
A
I/O
I/O
GND
GND
3R
A
82
1
3
2
5
8
10
14
17
20
22
24
6R
I/O
10R
12R
13R
14R
15R
R
11R
12R
8R
A
6R
9R
4R
A
I/O
I/O
I/O
R/W
A
A
UBR
84
4
6
9
15
LBR
13
16
18
19
21
8R
I/O
11R
10R
A
7R
A
I/O
I/O
I/O
A
OER
CER
A
A
B
C
D
E
F
G
H
J
K
L
2944 drw 04
Index
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Left Port
Right Port
Names
CEL
CER
WR
Chip Enable
WL
R/
R/
Read/Write Enable
Output Enable
Address
OEL
0L
OER
12L
0R
A
12R
A
- A
- A
0L
15L
0R
15R
I/O - I/O
SEML
UBL
I/O - I/O
SEMR
UBR
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
LBL
LBR
INTL
INTR
BUSYL
BUSYR
S
Busy Flag
M/
Master or Slave Select
Power
CC
V
GND
Ground
2944 tbl 01
6.42
3
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
X
L
I/O8-15
High-Z
High-Z
DATAIN
High-Z
DATAIN
I/O0-7
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
Mode
Deselected: Power Down
CE
H
X
L
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
H
L
L
H
L
H
L
L
L
H
L
H
H
H
X
L
H
L
H
DATAOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
OUT
DATA
L
L
H
L
H
L
L
L
H
DATAOUT
High-Z
DATAOUT
High-Z
X
H
X
X
X
Outputs Disabled
2944 tbl 02
NOTE:
1. A0L — A12L ≠ A0R — A12R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
H
↑
I/O8-15
I/O0-7
Mode
CE
H
X
H
X
L
OE
L
UB
X
H
X
H
L
LB
X
H
X
H
X
L
SEM
L
DATAOUT
DATAOUT
DATAIN
DATAOUT
DATAOUT
DATAIN
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
Write DIN0 into Semaphore Flag
Not Allowed
L
L
X
X
X
X
L
L
DATAIN
DATAIN
↑
____
____
X
X
L
____
____
L
X
L
Not Allowed
2944 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
6.442
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Maximum Operating Temperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
Commercial
0OC to +70OC
0V
0V
3.3V+ 0.3V
3.3V+ 0.3V
Industrial
-40OC to +85OC
Temperature
Under Bias
-55 to +125
-55 to +125
50
oC
oC
TBIAS
TSTG
IOUT
2944 tbl 05
NOTES:
1. This is the parameter TA.
Storage
Temperature
DC Output
Current
mA
2944 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
3.6
0
Unit
V
VCC
Supply Voltage
3.0
3.3
GND Ground
0
0
V
(2)
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
VCC+0.3
0.8
V
-0.5(1)
V
____
Capacitance(1) (TA = +25°C, f = 1.0MHz)
2944 tbl 06
NOTES:
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
Max. Unit
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
CIN
VIN = 3dV
9
pF
COUT
VOUT = 3dV
10
pF
2944 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V25S
70V25L
Min.
Symbol
|ILI|
Parameter
Test Conditions
Min.
Max.
10
Max.
5
Unit
µA
µA
V
(1)
___
___
___
___
Input Leakage Current
VCC = 3.6V, VIN = 0V to VCC
___
___
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
IH OUT
CC
10
5
CE = V , V = 0V to V
VOL
IOL = +4mA
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
2944 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
6.42
5
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
70V25X15
Com'l Only
70V25X20
Com'l
& Ind
70V25X25
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
CE = VIL, Outputs Open
SEM = VIH
(3)
f = fMAX
____
____
____
____
IND
S
L
140
130
225
195
130
125
210
180
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
mA
mA
mA
CER and CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
____
____
____
____
MIL &
IND
S
L
20
15
45
40
16
13
45
40
(5)
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(3)
f=fMAX
____
____
____
____
MIL &
IND
S
L
80
75
130
115
75
72
125
110
SEMR = SEML = VIH
Full Standby Current
Both Ports CEL and
CER > VCC - 0.2V,
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
(Both Ports
-
CMOS Level Inputs)
VIN > VCC - 0.2V or
____
____
____
____
VIN < 0.2V, f = 0(4)
MIL &
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
SEMR = SEML > VCC-0.2V
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
SEMR = SEML > VCC-0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
____
____
____
____
MIL &
IND
S
L
80
75
130
115
75
70
120
105
(3)
f = fMAX
2944 tbl 09a
70V25X35
Com'l
& Ind
70V25X55
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
120
115
180
155
120
115
180
155
mA
CE = VIL, Outputs Open
SEM = VIH
L
(3)
f = fMAX
IND
S
L
120
115
200
170
120
115
200
170
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
13
11
25
20
13
11
25
20
mA
mA
mA
mA
CER and CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
MIL &
IND
S
L
13
11
40
35
13
11
40
35
(5)
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
70
65
100
90
70
65
100
90
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(3)
f=fMAX
MIL &
IND
S
L
70
65
120
105
70
65
120
105
SEMR = SEML = VIH
Full Standby Current
Both Ports CEL and
CER > VCC - 0.2V,
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
(Both Ports
-
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
MIL &
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
SEMR = SEML > VCC-0.2V
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
65
60
100
85
65
60
100
85
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
SEMR = SEML > VCC-0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
MIL &
IND
S
L
65
60
115
100
65
60
115
100
(3)
f = fMAX
2944 tbl 09b
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. Icc dc = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.462
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
3.3V
3.3V
GND to 3.0V
3ns Max.
1.5V
590Ω
590Ω
Input Rise/Fall Times
OUT
BUSY
INT
DATA
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
1.5V
Ω
435
5pF*
30pF
435Ω
Figures 1 and 2
,
2944 tbl 10
2944 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test
Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
50%
50%
I
SB
,
2944 drw 06
6.42
7
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70V25X15
Com'l Only
70V25X20
Com'l
& Ind
70V25X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
tAA
tACE
Address Access Time
15
15
15
20
20
20
25
25
25
____
____
____
____
____
____
____
____
____
Chip Enable Access Time(3)
Byte Enable Access Time(3)
tABE
tAOE
tOH
tLZ
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable Access Time(3)
10
12
13
____
____
____
Output Hold from Address Change
3
3
3
____
____
____
Output Low-Z Time(1,2)
3
3
3
____
____
____
Output High-Z Time(1,2)
tHZ
10
12
15
____
____
____
Chip Enable to Power Up Time(1,2)
PU
t
0
0
0
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
____
____
____
tPD
15
20
25
____
____
____
tSOP
tSAA
10
10
10
____
____
____
15
20
25
ns
2944 tbl 11a
70V25X35
Com'l
& Ind
70V25X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
tAA
Address Access Time
35
35
35
55
55
55
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
tACE
tABE
tAOE
tOH
20
30
____
____
3
3
____
____
tLZ
3
3
Output High-Z Time(1,2)
15
25
____
____
tHZ
tPU
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
0
____
____
____
____
tPD
35
50
____
____
tSOP
tSAA
15
15
____
____
35
55
ns
2944 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
6.482
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE
(4)
tAOE
OE
(4)
tABE
UB, LB
R/W
(1)
tOH
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3,4)
2944 drw 07
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltage(5)
70V25X15
Com'l Only
70V25X20
Com'l
& Ind
70V25X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
12
0
15
0
20
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
15
15
____
____
____
10
12
15
____
____
____
tDH
0
0
0
(1,2)
____
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
10
12
15
____
____
____
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
Flag Write to Read Time
Flag Contention Window
SEM
SEM
ns
2944 tbl 12a
70V25X35
Com'l
& Ind
70V25X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
25
0
40
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
15
30
____
____
15
25
____
____
tDH
0
0
(1,2)
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
25
____
____
0
5
5
0
5
5
____
____
____
____
ns
2944 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire
tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
6.1402
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9)
CE or SEM(9)
(3)
tWR
(2)
(6)
tAS
tWP
R/W
DATAOUT
DATAIN
(7)
tWZ
tOW
(4)
(4)
tDW
tDH
2944 drw 08
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
(9)
or
CE SEM
(3)
(6)
(2)
tWR
tEW
tAS
(9)
or
UB LB
R/
W
tDW
tDH
DATAIN
2944 drw 09
NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. tEW must be met for either condition.
6.42
11
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tACE
tWR
tAW
tEW
SEM
tSOP
tDW
DATAOUT
VALID(2)
DATAIN
VALID
I/O0
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2944 drw 10
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
2944 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.1422
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
70V25X15
Com'l Ony
70V25X20
Com'l
& Ind
70V25X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
____
____
____
____
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
15
17
17
____
____
____
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
18
30
30
Write Hold After BUSY(5)
12
15
17
____
____
____
BUSY TIMING (M/S = VIL)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWB
0
0
0
ns
ns
tWH
12
15
17
(1)
____
____
____
____
____
____
tWDD
tDDD
Write Pulse to Data Delay
30
25
45
35
50
35
ns
Write Data Valid to Read Data Delay(1)
ns
2944 tbl 13a
70V25X35
Com'l
& Ind
70V25X55
Com'l
& Ind
Symbol
BUSY TIMING (M/S = VIH)
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
20
35
____
____
5
5
____
____
BUSY Disable to Valid Data(3)
35
40
Write Hold After BUSY(5)
25
25
____
____
BUSY TIMING (M/S = VIL)
____
____
____
____
BUSY Input to Write(4)
BUSY(5)
tWB
0
0
ns
ns
tWH
Write Hold After
25
25
PORT-TO-PORT DELAY TIMING
(1)
____
____
____
____
tWDD
tDDD
Write Pulse to Data Delay
60
45
80
65
ns
Write Data Valid to Read Data Delay(1)
ns
2944 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
6.42
13
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH)
tWC
ADDR"A"
R/W"A"
MATCH
tWP
tDH
tDW
DATAIN "A"
VALID
(1)
tAPS
ADDR"B"
MATCH
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
2944 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”.
6.1442
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/ "A"
W
(3)
tWB
BUSY"B"
(1)
tWH
(2)
R/ "B"
W
,
2944 drw 13
NOTES:
1. tWH must be met for both master BUSY input (slave) and output (master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
"B"
BUSY
2944 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
NOTES:
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
tBAA
tBDA
2944 drw 15
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70V25X15
Com'l Only
70V25X20
Com'l
& Ind
70V25X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
tAS
Address Set-up Time
0
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
0
____
____
____
15
15
20
20
20
20
____
____
____
Interrupt Reset Time
ns
2944 tbl 14a
70V25X35
Com'l
& Ind
70V25X55
Com'l
& Ind
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
tAS
Address Set-up Time
0
0
ns
ns
ns
WR
t
Write Recovery Time
Interrupt Set Time
0
0
____
____
tINS
tINR
25
25
40
40
____
____
Interrupt Reset Time
ns
2944 tbl 14b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.1462
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
INTERRUPT SET ADDRESS (2)
(3)
tAS
(4)
tWR
CE"A"
R/
W"A"
(3)
tINS
INT"B"
2944 drw 16
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
2944 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
17
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III Interrupt Flag(1)
Left Port
Right Port
R/WL
L
A12L-A0L
1FFF
X
R/WR
X
A12R-A0R
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
CEL
L
OEL
X
INTL
X
CER
X
OER
X
INTR
(2)
L
(3)
X
X
X
X
X
L
L
1FFF
1FFE
X
H
(3)
X
X
X
X
L
L
L
X
X
X
(2)
X
L
L
1FFE
H
X
X
X
Reset Left INTL Flag
2944 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Truth Table IV Address BUSY
Arbitration
Inputs
Outputs
A12L-A0L
12R-A0R
(1)
(1)
A
Function
Normal
Normal
Normal
CE
L
CER
X
BUSYL
BUSYR
X
H
X
L
NO MATCH
MATCH
H
H
H
H
X
H
MATCH
H
H
L
MATCH
(2)
(2)
Write Inhibit(3)
2944 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V25 are
push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2944 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V25.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables.
6.1482
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
SLAVE
Dual Port
SRAM
CE
CE
MASTER
Dual Port
SRAM
BUSYR
BUSYR
BUSYL
BUSYL
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
BUSYR
BUSYR
BUSYR
BUSYL
BUSYL
BUSYL
2944 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V25 SRAMs.
Functional Description
The IDT70V25 provides two ports with separate control, address writeoperationscanbepreventedtoaportbytyingtheBUSYpinforthat
and I/O pins that permit independent access for reads or writes to any portLOW.
location in memory. The IDT70V25 has an automatic power down
The BUSY outputs on the IDT 70V25 SRAM in master mode, are
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry push-pulltypeoutputs anddonotrequirepullupresistors tooperate.If
that permits the respective port to go into a standby mode when not theseSRAMsarebeingexpandedindepth,thentheBUSYindicationfor
selected (CE HIGH). When a port is enabled, access to the entire the resulting array requires the use of an external AND gate.
memory array is permitted.
Width Expansion with Busy Logic
Master/Slave Arrays
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)is assignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
1FFE (HEX), where a write is defined as the CER = R/WR = VIL per
Truth Table III. The left port clears the interrupt by an address location
1FFE access when CEL = OEL = VIL, R/WL is a "don't care". Likewise,
the right port interrupt flag (INTR) is set when the left port writes to
memorylocation1FFF(HEX)andtoclearthe interruptflag(INTR), the
rightportmustreadthememorylocation1FFF. Themessage(16bits)
at 1FFE or 1FFF is user-defined, since it is an addressable SRAM
location. If the interrupt function is not used, address locations 1FFE
and1FFFarenotusedasmailboxes,butaspartoftherandomaccess
memory. Refer to Truth Table III for the interrupt operation.
When expanding an IDT70V25 SRAM array in width while using
BUSYlogic, one masterpartis usedtodecide whichside ofthe SRAM
array will receive a BUSYindication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V25 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actualwrite pulse canbe initiatedwitheitherthe R/W signalorthe byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
Semaphores
The use of BUSY logic is not required or desirable for all applica-
tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe
event of an illegal or illogical operation. If the write inhibit function of
BUSYlogicis notdesirable,the BUSYlogiccanbedisabledbyplacing
the part in slave mode with the M/Spin. Once in slave mode the BUSY
pinoperates solelyas awriteinhibitinputpin.Normaloperationcanbe
programmed by tying the BUSY pins HIGH. If desired, unintended
TheIDT70V25is anextremelyfastDual-Port8Kx16CMOSStatic
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags alloweitherprocessoronthe leftorright
side of the Dual-Port SRAM to claim a privilege over the other
processor for functions defined by the system designer’s software. As
an example, the semaphore can be used by one processor to inhibit
the otherfromaccessinga portionofthe Dual-PortSRAMoranyother
6.42
19
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
sharedresource.
as a chip select for the semaphore flags) and using the other
The Dual-Port SRAM features a fast access time, and both ports control pins (Address, OE, and R/W) as they would be used in
are completelyindependentofeachother. This means thatthe activity accessing a standard static RAM. Each of the flags has a unique
on the left port in no way slows the access time of the right port. Both address which can be accessed by either side through address pins
ports are identical in function to standard CMOS Static RAM and can A0 – A2. When accessing the semaphores, none of the other address
be accessed at the same time with the only possible conflict arising pins has any effect.
from the simultaneous writing of, or a simultaneous READ/WRITE of,
When writing to a semaphore, only data pin D0 is used. If a LOW
a non-semaphore location. Semaphores are protected against such level is written into an unused semaphore location, that flag will be set
ambiguous situations and may be used by the system program to to a zero on that side and a one on the other side (see Truth Table V).
avoid any conflicts in the non-semaphore portion of the Dual-Port That semaphore can now only be modi-fied by the side showing the
SRAM. These devices have an automatic power-down feature con- zero. When a one is written into the same location from the same side,
trolled by CE, the Dual-Port SRAM enable, and SEM, the semaphore the flagwillbe settoa one forbothsides (unless a semaphore request
enable. The CE and SEM pins control on-chip power down circuitry fromtheothersideispending)andthencanbewrittentobybothsides.
that permits the respective port to go into standby mode when not The fact that the side which is able to write a zero into a semaphore
selected. This is the condition which is shown in Truth Table I where subsequently locks out writes from the other side is what makes
CE and SEM are both HIGH.
semaphore flags useful in interprocessor communications. (A thor-
Systems which can best use the IDT70V25 contain multiple ough discussion on the use of this feature follows shortly.) A zero
processors or controllers and are typically very high-speed systems written into the same location from the other side will be stored in the
which are software controlled or software intensive. These systems semaphore request latch for that side until the semaphore is freed by
can benefit from a performance increase offered by the IDT70V25's the first side.
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Whena semaphore flagis read, its value is spreadintoalldata bits
so that a flag that is a one reads as a one in all data bits and a flag
Softwarehandshakingbetweenprocessors offers themaximumin containinga zeroreads as allzeros. The readvalue is latchedintoone
system flexibility by permitting shared resources to be allocated in side’s output register when that side's semaphore select (SEM) and
varying configurations. The IDT70V25 does not use its semaphore output enable (OE) signals go active. This serves to disallow the
flags to control any resources through hardware, thus allowing the semaphore from changing state in the middle of a read cycle due to a
system designer total flexibility in system architecture.
write cycle from the other side. Because of this latch, a repeated read
An advantage of using semaphores rather than the more common of a semaphore in a test loop must cause either signal (SEM or OE) to
methods of hardware arbitration is that wait states are never incurred go inactive or the output will never change.
in either processor. This can prove to be a major advantage in very
high-speed systems.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processorwritesazerototheleftportatafreesemaphorelocation.On
asubsequentread,theprocessorwillverifythatithas writtensuccess-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dentofthe Dual-PortSRAM. These latches canbe usedtopass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthis method,
thestateofasemaphorelatchisusedasatokenindicatingthatshared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V25 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
6.2402
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
secondside’sflagwillnowstayLOWuntilitssemaphorerequestlatchis control of the second 4K section by writing, then reading a zero into
writtentoaone.Fromthisitiseasytounderstandthat,ifasemaphoreis Semaphore 1. If it succeeded in gaining control, it would lock out the
requested and the processor which requested it no longer needs the left side.
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
The critical case of semaphore timing is when both sides request Semaphore 1 was still occupied by the right side, the left side could
a single tokenbyattemptingtowrite a zerointoitatthe same time. The undo its semaphore request and perform other tasks until it was able
semaphore logic is specially designed to resolve this problem. If to write, then read a zero into Semaphore 1. If the right processor
simultaneous requests are made, the logic guarantees that only one performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe
side receives the token. If one side is earlier than the other in making twoprocessors toswap4Kblocks ofDual-PortSRAMwitheachother.
the request, the first side to make the request will receive the token. If
bothrequests arriveatthesametime,theassignmentwillbearbitrarily variable, depending upon the complexity of the software using the
made to one port or the other. semaphore flags. All eight semaphores could be used to divide the
The blocks do not have to be any particular size and can even be
One caution that should be noted when using semaphores is that Dual-Port SRAM or other shared resources into eight parts. Sema-
semaphores alone do not guarantee that access to a resource is phores can even be assigned different meanings on different sides
secure. As with any powerful programming technique, if semaphores rather than being given a common meaning as was shown in the
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
example above.
Semaphores are a useful form of arbitration in systems like disk
handled via the initialization program at power-up. Since any sema- interfaces where the CPU must be locked out of a section of memory
phore request flag which contains a zero must be reset to a one, all during a transfer and the I/O device cannot tolerate any wait states.
semaphores on both sides should have a one written into them at With the use of semaphores, once the two devices has determined
initialization from both sides to assure that they will be free when which memory area was “off-limits” to the CPU, both the CPU and the
needed.
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
UsingSemaphoresSomeExamples
Perhaps the simplest application of semaphores is their applica-
tionasresourcemarkersfortheIDT70V25’sDual-PortSRAM.Saythe
8K x 16 SRAM was to be divided into two 4K x 16 blocks which were
to be dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
thelowersectionofmemory,andSemaphore1couldbedefinedasthe
indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port
SRAM, the processor on the left port could write and then read a zero
in to Semaphore 0. If this task were successfully completed (a zero
was read back rather than a one), the left processor would assume
control of the lower 4K. Meanwhile the right processor was attempting
to gain control of the resource after the left processor, it would read
back a one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try and gain
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure blockis released. This allows the interpretingprocessor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2944 drw 19
Figure 4. IDT70V25 Semaphore Logic
6.42
21
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information(1)
IDT XXXXX
A
999
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
G
J
100-pin TQFP (PN100-1)
84-pin PGA (G84-3)
84-pin PLCC (J84-1)
15
20
25
35
55
Commercial Only
,
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Speed in Nanoseconds
S
L
Standard Power
Low Power
128K (8K x 16) 3.3V Dual-Port RAM
70V25
2944 drw 20
Datasheet Document History
3/8/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
Page 9 Fixed typographical error
Changed drawing format
Page1Chaged660mWto660µW
Replaced IDT logo
5/19/99:
6/10/99:
8/30/99:
11/12/99:
11/18/99:
3/10/00:
Page 2 Fixed pin 55 in PN100 package
Added 15 & 20ns speed grades
UpgradedDCparameters
AddedIndustrialTemperatureinformation
Changed±200mVto0mVinnotes
Page5FixednoteforAbsoluteMaximumRatingstable
5/16/00:
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6.2422
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