IDT70V3319S166PRFG8 [IDT]
Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP128, TQFP-128;
| 型号： | IDT70V3319S166PRFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP128, TQFP-128 时钟 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
256/128K x 18
SYNCHRONOUS
IDT70V3319/99S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
GridArray
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package
◆
◆
High-speed data access
◆
◆
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
– Due to limited pin count PL/FToption is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
◆
◆
Full synchronous operation on both ports
– 6ns cycle time, 166MHzoperation(6Gbps bandwidth)
– Fast 3.6ns clock to data out
◆
◆
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
Green parts available, see ordering information
Functional Block Diagram
UBL
UBR
LBL
LBR
FT/PIPE
L
1b 0b
b
1a 0a
a
0a 1a
a
0b 1b
b
FT/PIPER
1/0
1/0
R/WL
R/WR
CE0L
CE0R
1
1
CE1R
CE1L
B
B
B B
0
W W
0
W W
0
L
1
L
1
0
R
R
1/0
1/0
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OEL
OER
,
0a 1a
1b 0b 1a 0a
ab
0b 1b
ba
0/1
FT/PIPE
R
FT/PIPE
L
0/1
256K x 18
MEMORY
ARRAY
I/O0R - I/O17R
Din_L
I/O0L - I/O17L
Din_R
,
CLKR
CLKL
(1)
L
(1)
A
17L
A
A
17R
0R
Counter/
Address
Reg.
Counter/
Address
Reg.
A0L
ADDR_R
ADDR_L
REPEAT
ADS
CNTEN
REPEAT
ADS
CNTEN
R
R
L
R
L
5623 tbl 01
TDI
TCK
TMS
TRST
NOTE:
1. A17 is a NC for IDT70V3399.
JTAG
TDO
JANUARY 2009
1
DSC 5623/9
©2009 Integrated DeviceTechnology,Inc.
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70V3319/99isahigh-speed256/128Kx18bitsynchronous or bidirectional data flow in bursts. An automatic power down feature,
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to controlledbyCE0andCE1, permits the on-chipcircuitryofeachportto
allowsimultaneousaccessofanyaddressfrombothports.Registerson enter a very low standby power mode.
control, data, and address inputs provide minimal setup and hold
The70V3319/99cansupportanoperatingvoltageofeither3.3Vor
times. The timing latitude provided by this approach allows systems 2.5Vononeorbothports,controllablebytheOPTpins.Thepowersupply
tobedesignedwithveryshortcycletimes.Withaninputdataregister,the forthe core ofthe device (VDD)remains at3.3V.
IDT70V3319/99hasbeenoptimizedforapplicationshavingunidirectional
PinConfiguration(1,2,3,4,5)
08/01/02
1
2
3
4
5
6
7
8
9
11 12 13 14
10
16 17
15
I/O9L
VSS
A
16L
A
12L
A
B
C
D
E
F
NC
V
SS
NC
A
8L
NC
V
DD
A
0L
OPT
L
NC
TDO
CLK
L
CNTEN
L
A4L
NC
(1)
VSS
NC
A
9L
TDI
NC
CE0L
V
SS
SS
ADS
L
VSS
VDDQR I/O8L
NC
A
17L
A13L
A5L
A1L
I/O9R
V
DDQR PIPE/FT
L
NC
A14L
VDDQL
A10L
UB
L
V
DD
I/O8R
CE1L
V
A6L
A2L
NC
V
SS
R/W
L
NC
VSS
I/O10L
NC
VDDQL
A
15L
A
11L
VDD
I/O7R
NC
A
7L
LB
L
A3L
VDD
I/O7L
OE
L
REPEAT
L
I/O11L
NC
VDDQR I/O10R
I/O6L
NC
VSS
NC
VSS
I/O6R
VDDQL I/O11R
NC
VDDQR
NC
VSS
NC
V
SS
I/O12L
NC
NC
I/O5L
V
DDQL
NC
G
H
J
V
DD
V
SS
SS
I/O5R
NC
V
DDQR I/O12R
NC
VDD
70V3319/99BF
BF-208(6)
V
DDQL
V
DD
V
VDDQR
VDD
VSS
V
SS
VSS
208-Pin fpBGA
Top View(7)
I/O3R
NC
I/O4R
I/O14R
NC
V
SS
VDDQL
V
SS
K
L
I/O13R
V
SS
I/O14L
NC
VDDQR
I/O13L
I/O4L
I/O3L
NC
VSS
VDDQL
I/O15R
NC
V
SS
VSS
I/O2R
NC
V
DDQR
I/O2L
NC
M
N
P
R
T
NC
V
SS
V
DDQL
I/O15L
NC
I/O1R
NC
I/O16L
I/O16R
VDDQR
TRST
A
16R
A8R
A
12R
9R
NC
I/O1L
VSS
V
DD
SS
CLKR
CNTEN
R
A
4R
(1)
17R
A
TCK
TMS
NC
A13R
V
SS
I/O17R
CE0R
CE1R
VDDQR
NC
A
NC
I/O0R
ADS
R
V
A5R
VDDQL
V
SS
SS
A1R
VSS
NC
I/O17L
UBR
NC
A14R
A10R
VSS
V
DDQL
A6R
V
NC
NC
R/WR
A2R
VSS
PIPE/FT
R
LBR
VDD
I/O0L
NC
A
7R
OER
REPEAT
R
A
3R
V
DD
NC
A15R
A11R
OPTR
A0R
U
5623 drw 02c
NOTES:
1. A17 is a NC for IDT70V3399.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4,5) (con't.)
70V3319/99BC
BC-256(6)
256-Pin BGA
Top View(7)
08/01/02
A1
A2
A3
A6
A7
A8
A9
CE1L
A11
A12
A13
A14
A4
A5
A10
A15
A16
A
17L(1)
NC
TDI
NC
A
11L
A
8L
9L
7L
NC
CNTEN
L
A
5L
A2L
A0L
A14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
NC
NC TDO
A
12L
10L
A
REPEAT
L
A
4L
A
1L
NC
A
15L
UB
L
R/W
L
VDD
NC
NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
NC
A
13L
A
I/O9L
V
SS
A
16L
A
NC
LB
L
CLK
L
ADS
L
A
6L
A3L
I/O8L
OPT
L
NC
D1
D2
D6
DDQL
D9
DDQL
D11
DDQR
D3
D5
VDDQL
L
D7
DDQR
D8
DDQR
D10
D12
D13
D14
D15
D16
D4
NC I/O9R
V
V
V
VDDQL
NC
V
V
VDDQR
VDD
NC
NC I/O8R
PIPE/FT
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
V
DD
V
DD
SS
SS
V
SS
V
SS
SS
SS
V
SS
V
SS
V
DD
V
DD
V
DDQR
I/O10R I/O10L NC
V
DDQL
NC
I/O7R
I/O7L
F7
F3
F5
F6
F9
F10
F1
F2
F14
F15
F16
F11
F13
F4
F8
F12
V
SS
I/O11R
VDD
V
VSS
V
SS
I/O11L NC
VSS
VDDQR I/O6R
NC I/O6L
V
VDD
V
DDQL
G1
G2
G5
H5
G4
G6
G8
G9
G3
G7
G10
G12
G13 G14
G15
G16
G11
NC
NC
V
SS
SS
SS
V
DDQR
V
V
VSS
I/O12L
I/O5L NC
DDQL
NC
VSS
V
SS
VSS
V
VSS
H11
H12
H13
H16
H7
H8
H9
H10
H14
H15
H3
H4
H6
H1
H2
V
SS
VSS
I/O5R
VDDQL
VSS
VSS
VSS
V
SS
SS
NC
NC
V
VSS
NC
V
DDQR
NC I/O12R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O13L
I/O14R I/O13R
V
DDQL
V
V
SS
VSS
V
SS
SS
VSS
VDDQR
V
VSS
V
SS
I/O4R
I/O3R I/O4L
K6
K8
K10
K12
K13
K5
K7
L7
K9
K11
K2
K4
K15
K16
K1
K3
K14
V
SS
V
V
SS
SS
VSS
V
DDQR
NC
VDDQL
V
SS
DD
V
SS
VSS
VSS
NC I/O3L
NC
I/O14L
NC
L8
L11
L12
L13
L3
L4
L5
L6
L9
L10
L15
L16
L1
L2
L14
V
SS
VSS
VSS
V
DD
V
DDQL
V
V
SS
VSS
V
I/O15R
V
DDQR
NC I/O2R
I/O15L NC
I/O2L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1
M2
M3
M4
M16
M14
M15
V
DD
VDD
VSS
VSS
V
SS
V
SS
VDD
VDD
V
DDQL
I/O1R I/O1L
I/O16R I/O16L NC
V
DDQR
NC
N8
N12
N16
N13
N4
N5
N6
DDQR
N7
N9
N10
N11
N15
N1
N2
N3
N14
VDDQL
VDDQL
VDD
NC
VDDQR
V
VDDQL
VDDQR
VDDQR
V
DDQL
PIPE/FT
R
I/O0R
NC I/O17R NC
NC
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
NC I/O17L TMS
A16R
A13R
A
7R
NC
LB
R
CLK
R
ADSR
A6R
NC
NC
I/O0L
A10R
A3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
A
15R
A
12R
A
9R
UB
R
CE0R R/W
R
REPEAT
R
NC
NC
NC TRST NC
A
4R
A1R OPT
R
NC
T2
T3
T1
T4
17R(1)
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
TCK
NC
NC
A
A
14R
NC CE1R
NC
NC
A
11R
A
8R
OE
R
CNTEN
R
A
5R
A
2R
A0R
5623 drw 02d
,
NOTES:
1. A17 is a NC for IDT70V3399.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4,5,8,9) (con't.)
08/06/02
A
A
OPT
1L
0L
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A
14L
A15L
L
A
17L
16L
(1)
V
SS
IO8L
IO8R
A
IO9L
IO9R
DDQL
V
V
V
V
IO7L
IO7R
SS
SS
V
IO10L
SS
DDQL
9
10
IO10R
V
DDQR
SS
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
SS
V
DDQR
IO11L
IO11R
IO12L
IO12R
V
V
IO6L
IO6R
IO5L
IO5R
V
V
V
V
IO4R
IO4L
IO3R
IO3L
IO2R
IO2L
V
V
IO1R
IO1L
V
V
IO0R
IO0L
OPT
DD
70V3319/99PRF
PK-128(6)
DD
DD
DD
V
V
SS
SS
SS
SS
IO13R
IO13L
128-Pin TQFP
Top View(7)
IO14R
IO14L
IO15R
IO15L
26
V
DDQL
SS
27
28
29
30
31
32
33
34
35
36
37
38
SS
V
DDQL
IO16R
IO16L
V
DDQR
SS
V
SS
DDQR
IO17R
IO17L
(1)
17R
A
R
A
A
A
16R
A
A
0R
1R
15R
14R
.
5623 drw 02a
NOTES:
1. A17 is a NC for IDT70V3399.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 14mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
8. PIPE/FT option in PK-128 is not supported due to limitation in pin count. Device is pipelined outputs only on each port.
9. Due to the limited pin count, JTAG is not supported in the PK-128 package.
6.42
4
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
Chip Enables(6)
CE0L
R/W
OE
,
CE1L
CE0R, CE1R
L
R/W
R
Read/Write Enable
Output Enable
L
OE
R
(1)
(1)
A
0L - A17L
A0R - A17R
Address
I/O0L - I/O17L
CLK
PIPE/FT (5)
ADS
CNTEN
REPEAT
UB
LB
I/O0R - I/O17R
CLK
Data Input/Output
Clock
L
R
(5)
L
PIPE/FT
R
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
L
ADSR
L
CNTEN
R
(4)
Counter Repeat
L
REPEAT
R
(6)
Upper Byte Enable (I/O
9-I/O17)
L
UBR
(6)
Lower Byte Enable (I/O
0-I/O8)
L
LBR
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)(2)
NOTES:
1. A17 is a NC for IDT70V3399.
(2,3)
OPT
L
OPT
R
Option for selecting VDDQX
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
(2)
VDD
Power (3.3V)
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
5. PIPE/FT option in PK-128 package is not supported due to limitation in pin count.
Device is pipelined output mode only on each port.
V
SS
Ground (0V)
TDI
TDO
TCK
TMS
TRST
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5623 tbl 01
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
5
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3)
Upper Byte
I/O9-17
Lower Byte
I/O0-8
CLK
↑
CE
1
R/W
X
X
X
L
MODE
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Write to Lower Byte Only
Write to Upper Byte Only
Write to Both Bytes
OE
X
X
X
X
X
X
L
CE
0
UB
X
X
H
H
L
LB
X
X
H
L
H
X
L
L
L
L
L
L
L
L
X
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
↑
H
H
H
H
H
H
H
H
↑
DIN
↑
H
L
L
DIN
High-Z
↑
L
L
DIN
DIN
↑
H
L
L
H
H
H
X
High-Z
DOUT
Read Lower Byte Only
Read Upper Byte Only
Read Both Bytes
↑
L
H
L
DOUT
High-Z
↑
L
L
DOUT
DOUT
↑
H
L
L
High-Z
High-Z
Outputs Disabled
↑
5623 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
(3)
ADS CNTEN REPEAT(6)
CLK
↑
I/O
I/O(0)
I/O (n) External Address Used
I/O(p) External Address Blocked—Counter disabled (Ap reused)
DI/O(p+1) Counter Enabled—Internal Address generation
(4)
X
An
An
X
X
X
An
An
X
X
X
H
L
D
Counter Reset to last valid ADS load
(4)
L
H
H
H
D
↑
Ap
Ap
Ap
H
H
D
↑
(5)
Ap + 1
L
↑
5623 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB, LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and UB, LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB, LB.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
6
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
RecommendedDCOperating
TemperatureandSupplyVoltage(1)
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
Max.
3.45
2.6
0
Unit
V
Ambient
Grade
Commercial
Temperature
GND
0V
VDD
V
DD
DDQ
SS
IH
3.15 3.3
0OC to +70OC
3.3V
3.3V
+
+
150mV
150mV
V
2.4
0
2.5
V
Industrial
-40OC to +85OC
0V
V
0
V
5623 tbl 04
(2)
____
V
DDQ + 100mV
Input High Voltage
1.7
V
V
NOTES:
(Address & Control Inputs)
1. This is the parameter TA. This is the "instant on" case temperature.
(3)
(2)
____
____
V
IH
Input High Voltage - I/O
1.7
V
DDQ + 100mV
V
VIL
Input Low Voltage
-0.3(1)
0.7
V
5623 tbl 05a
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 100mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPTpinforthatportmustbesettoVIL (0V),andVDDQX forthatportmustbesupplied
as indicated above.
AbsoluteMaximumRatings(1)
Symbol
Rating
Commercial
& Industrial
Unit
(2)
Terminal Voltage
with Respect to GND
-0.5 to +4.6
V
V
TERM
RecommendedDCOperating
Conditions with VDDQ at 3.3V
(3)
Temperature Under Bias
-55 to +125
oC
T
BIAS
STG
JN
OUT
oC
oC
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
3.15 3.3
Max.
3.45
3.45
0
Unit
V
T
Storage Temperature
Junction Temperature
DC Output Current
-65 to +150
+150
V
DD
DDQ
SS
IH
T
V
V
I
50
mA
V
0
0
V
5623 tbl 06
NOTES:
(2)
____
Input High Voltage
(Address & Control Inputs)
2.0
VDDQ + 150mV
V
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
(3)
(3)
(2)
____
____
V
IH
Input High Voltage - I/O
2.0
V
DDQ + 150mV
V
VIL
Input Low Voltage
-0.3(1)
0.8
V
5623 tbl 05b
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6.42
7
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)(TA = +25°C, F = 1.0MHZ)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
Max. Unit
CIN
V
8
pF
(3)
OUT
C
VOUT = 3dV
10.5
pF
5623 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3319/99S
Symbol
Parameter
Test Conditions
VDDQ = Max., VIN = 0V to VDDQ
Min.
Max.
10
Unit
µA
µA
V
Input Leakage Current(1)
___
___
___
|ILI|
(1)
|ILO
OL (3.3V) Output Low Voltage(2)
OH (3.3V) Output High Voltage(2)
OL (2.5V) Output Low Voltage(2)
OH (2.5V) Output High Voltage(2)
|
Output Leakage Currentt
10
CE
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
V
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
5623 tbl 08
NOTE:
1. At VDD < 2.0V leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
6.42
8
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V3319/99S166 70V3319/99S133
Com'l Only
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
370
Max.
500
Typ.(4)
320
320
115
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
mA
mA
mA
CE
L
and CER= VIL,
S
S
S
S
S
S
400
480
160
195
290
350
Outputs Disabled,
____
____
(1)
IND
f = fMAX
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH,
Outputs Disabled,
f = fMAX
COM'L
IND
125
200
____
____
(1)
115
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
COM'L
IND
250
350
220
220
Active Port Outputs Disabled,
____
____
(1)
f=fMAX
ISB3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports Outputs Disabled
COM'L
IND
S
S
15
30
15
15
30
40
CE
L and CER > VDDQ - 0.2V,
VIN > VDDQ - 0.2V
____
____
(2)
or VIN < 0.2V, f = 0
(5)
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
mA
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V
COM'L
IND
S
S
250
350
220
220
290
350
V
IN > VDDQ - 0.2V or VIN < 0.2V
____
____
(1)
Active Port, Outputs Disabled, f = fMAX
5623 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
9
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
2.5V
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.4V
GND to 3.0V/GND to 2.4V
2ns
833Ω
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
DATAOUT
1.5V/1.25V
5pF*
770Ω
Figures 1 and 2
5623 tbl 10
,
3.3V
590Ω
5pF*
50Ω
50Ω
,
DATAOUT
DATAOUT
1.5V/1.25
10pF
435Ω
(Tester)
5623 drw 03
Figure 1. AC Output Test load.
,
5623 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
∆tCD
(Typical, ns)
3
2
•
1
•
•
•
,
20.5
50
80 100
200
30
-1
Capacitance (pF)
5623 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
10
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3319/99S166
Com'l Only
70V3319/99S133
Com'l
& Ind
Symbol
Parameter
Min.
20
Max.
Min.
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
____
____
t
CYC1
CYC2
CH1
CL1
CH2
CL2
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRPT
HRPT
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Clock Cycle Time (Flow-Through)
(1)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Clock Cycle Time (Pipelined)
6
7.5
7
t
Clock High Time (Flow-Through)(1)
Clock Low Time (Flow-Through)(1)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(1)
Address Setup Time
6
t
6
7
t
2.1
2.1
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
2.6
2.6
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
t
t
t
Address Hold Time
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
t
t
t
t
t
R/W Hold Time
t
Input Data Setup Time
t
Input Data Hold Time
t
ADS Setup Time
t
ADS Hold Time
t
CNTEN Setup Time
t
CNTEN Hold Time
t
REPEAT Setup Time
t
0.5
0.5
REPEAT Hold Time
____
____
t
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)(1)
Clock to Data Valid (Pipelined)(1)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
4.0
4.2
____
____
t
1
1
t
1
3.6
12
1
4.2
15
____
____
t
____
____
t
3.6
4.2
____
____
t
1
1
1
1
1
1
t
3
3
____
____
t
Port-to-Port Delay
Clock-to-Clock Offset
____
____
tCO
5
6
ns
5623 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
6.42
11
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
t
SC
tHC
t
SC
SB
t
HC
HB
(3)
CE1
t
SB
tHB
t
t
(5)
UB, LB
R/W
tHW
tSW
tSA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
tCD2
Qn + 1
Qn + 2 (5)
(1)
tCKLZ
t
OHZ
tOLZ
OE (1)
tOE
5623 drw 06
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE
0
tSC
tHC
tSC
tHC
(3)
CE1
tSB
tHB
tHB
UB, LB
tSB
R/W
tSW
tHW
tSA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
An + 3
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2(5)
tCKLZ
tDC
tOHZ
tOLZ
OE(1)
tOE
5623 drw 07
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB, LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
12
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
tSA tHA
A6
A5
A4
A3
A2
A0
A1
tSC tHC
t
SC
tHC
tCD2
tCD2
tCKHZ
tCD2
Q0
A2
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
tDC
tCKLZ
tDC
tCKHZ
tSA tHA
A6
A5
A4
A3
A0
A1
tSC tHC
CE0(B2)
tSC tHC
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
5623 drw 08
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
tSC
tHC
CE0(B1)
t
SC
tHC
(1)
tCD1
tCD1
tCKHZ
tCD1
tCD1
D
0
D
3
D5
D
1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
(1)
tDC
tCKLZ
tCKLZ
t
DC
t
CKHZ
tSA
tHA
A6
A
5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
tSC
tHC
(1)
(1)
t
CD1
t
CKHZ
t
CD1
(1)
tCKHZ
D4
DATAOUT(B2)
D2
(1)
t
CKLZ
tCKLZ
5623 drw 09
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3319/99 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
13
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
R/W"A"
ADDRESS"A"
DATAIN"A"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
CO
t
CLK"B"
t
CD2
R/W"B"
t
SW
SA
t
HW
HA
t
t
NO
ADDRESS"B"
DATAOUT"B"
MATCH
MATCH
VALID
tDC
5623 drw 10
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
t
CO
t
CD1
R/W "B"
t
HW
HA
t
SW
t
t
SA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
t
CD1
VALID
VALID
tDC
t
DC
5623 drw 11
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
14
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE
0
1
tSC
tHC
CE
tSB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
ADDRESS(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
tCD2
tCD2
(1)
tCKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP(4)
WRITE
READ
5623 drw 12
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
UB, LB
tSW tHW
R/W
tSW tHW
ADDRESS(3)
DATAIN
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
t
SA
tHA
t
SD
tHD
Dn + 2
tCD2
tCD2
tCKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
5623 drw 13
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
15
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
UB, LB
t
SW tHW
R/
W
t
SW tHW
(3)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
t
SD
tHD
DATAIN
Dn + 2
t
CD1
t
CD1
t
CD1
tCD1
(1)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
t
DC
t
CKLZ
t
DC
t
CKHZ
NOP(5)
READ
WRITE
6523 drw 14
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)(2)
tCYC1
CH1
t
tCL1
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
UB, LB
tSW tHW
t
SW tHW
R/
W
(3)
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
ADDRESS
DATAIN
t
SA
tHA
t
SD tHD
Dn + 2
t
OE
CD1
tDC
t
CD1
t
CD1
t
(1)
Qn + 4
Qn
DATAOUT
t
CKLZ
t
DC
t
OHZ
OE
READ
WRITE
READ
5623 drw 15
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
16
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
t
SAD tHAD
ADS
t
SAD tHAD
CNTEN
t
SCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5623 drw 16
Timing Waveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
t
CH1
tCL1
CLK
t
SA
tHA
An
ADDRESS
tSAD tHAD
t
SAD
tHAD
ADS
tSCN
tHCN
CNTEN
t
CD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
WITH
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
COUNTER
5623 drw 17
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
17
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
5623 drw 18
Timing Waveform of Counter Repeat(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
LAST ADS LOAD
Ax
LAST ADS +1
An
An + 1
tSW tHW
R/W
ADS
t
SAD
tHAD
CNTEN
tSCN tHCN
tSRPT
tHRPT
REPEAT
tSD
tHD
D0
DATAIN
(5)
QLAST+1
Qn
QLAST
DATAOUT
EXECUTE (6)
REPEAT
READ
LAST ADS
ADDRESS
READ
ADDRESS n
READ
ADDRESS n+1
WRITE
READ
LAST ADS
LAST ADS
ADDRESS
ADDRESS + 1
5623 drw 19
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and REPEAT = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
18
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
Depth and Width Expansion
The IDT70V3319/99 provides a true synchronous Dual-Port Static
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock
signal.
The IDT70V3319/99 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3319/99 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Throughcombiningthecontrol
signals, the devices can be grouped as necessary to accommodate
applicationsneeding36-bitsorwider.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3319/99s for depth
expansionconfigurations. Twocycles arerequiredwithCE0 LOWand
CE1 HIGHtore-activatetheoutputs.
(1)
A18/A17
IDT70V3319/99
IDT70V3319/99
CE0
CE0
CE1
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V3319/99
IDT70V3319/99
CE1
CE1
CE0
CE0
UB, LB,
R/W,
Control Inputs
Control Inputs
OE,
CLK,
ADS,
5623 drw 20
REPEAT,
CNTEN
Figure 4. Depth and Width Expansion with IDT70V3319/99
NOTE:
1. A17 is for IDT70V3319, A16 is for IDT70V3399.
6.42
19
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
t
JCYC
t
JR
tJF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
TRST
,
5623 drw 21
t
JRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70V3319/99
Max.
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Units
ns
____
____
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
t
ns
t
40
ns
(1)
____
t
3
ns
(1)
____
t
3
ns
____
____
t
50
ns
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
____
t
25
ns
____
t
0
ns
____
____
t
15
15
ns
t
JTAG Hold
ns
5623 tbl 12
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
20
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
0x0314(1)
0x33
1
IDT Device ID (27:12)
Defines IDT part number
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
IDRegister Indicator Bit (Bit 0)
5623 tbl 13
NOTE:
1. Device ID for IDT70V3399 is 0x0315.
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
5623 tbl 14
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the bypass register (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0011
0001
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED
All other codes
Several combinations are reserved. Do not use codes other than those
identified above.
5623 tbl 15
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
21
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
A
XXXXX
A
999
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(1)
Green
BF
PRF
BC
208-pin fpBGA (BF-208)
128-pin TQFP (PK-128)
256-pin BGA (BC-256)
Commercial Only
166
133
Speed in Megahertz
Commercial & Industrial
S
Standard Power
,
70V3319 4Mbit (256K x 18-Bit) Synchronous Dual-Port RAM
70V3399 2Mbit (128K x 18-Bit) Synchronous Dual-Port RAM
5623 drw 22
NOTE:
1. Green parts available. For specific speeds, packages and powers contact your local sales office.
IDT Clock Solution for IDT70V3319/99 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
IDT
PLL
Clock Device
IDT Dual-Port
Part Number
Input Duty
Cycle
Requirement
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
3.3/2.5
I/O
70V3319/99
LVTTL
8pF
40%
166
75ps
IDT5V2528
5623 tbl 16a
6.42
22
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory:
06/02/00:
07/12/00:
06/20/01:
InitialPublicOffering
Page 1 Addedmuxtofunctionalblockdiagram
Page 1 AddedJTAGinformationforTQFPpackage
Page 4 CorrectedTQFPpackagesize
Page 1 AddedPL/FToption
Page 20 ChangedmaximumvalueforJTAGACElectricalCharacteristicsfortJCD from20nsto25ns
Page 9 AddedIndustrialTemperatureDCParameters
07/30/01:
11/20/01:
Page 2, 3 & 4 Added date revision for pin configurations
Page 11 ChangedtOE valueinACElectricalCharacteristics,pleaserefertoErrata#SMEN-01-05
Page 1 & 22 Replaced TM logo with ® logo
Page 10 ChangedACTestConditionsInputRise/FallTimes
Consolidatedmultipledevicesintoonedatasheet
08/06/02:
Page 1&5AddedDCDcapabilityforPipelinedOutputs
Page 7 Clarified TBIAS and added TJN
Page 9 ChangedDCElectricalParameters
Page 11 RemovedClockRise&FallTimefromACElectricalCharacteristicsTable
RemovedPreliminarystatus
05/19/03:
02/08/06:
Page11 AddedByte Enable SetupTime &Byte Enable HoldTime toACElecctricalCharacteristics Table
Page 22 AddedIDTClockSolutionTable
Page 1 Addedgreenavailabilitytofeatures
Page 6 Changed footnote 2 for Truth Table I from ADS, CNTEN, REPEAT = VIH to ADS, CNTEN, REPEAT = X
Page 22 Addedgreenindicatortoorderinginformation
07/25/08:
01/19/09:
Page 9 Corrected a typo in the DC Chars table
Page 22 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
23
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