IDT70V3379S5PRF
更新时间:2024-09-18 02:02:05
品牌:IDT
描述:HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3379S5PRF 概述
HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE 高速3.3V 32K ×18同步流水式双端口静态3.3V或2.5V接口RAM SRAM
IDT70V3379S5PRF 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Obsolete | 零件包装代码: | QFP |
包装说明: | PLASTIC, TQFP-128 | 针数: | 128 |
Reach Compliance Code: | not_compliant | ECCN代码: | 3A991.B.2.B |
HTS代码: | 8542.32.00.41 | 风险等级: | 5.76 |
最长访问时间: | 5 ns | 其他特性: | PIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE |
最大时钟频率 (fCLK): | 100 MHz | I/O 类型: | COMMON |
JESD-30 代码: | R-PQFP-G128 | JESD-609代码: | e0 |
长度: | 20 mm | 内存密度: | 589824 bit |
内存集成电路类型: | DUAL-PORT SRAM | 内存宽度: | 18 |
湿度敏感等级: | 3 | 功能数量: | 1 |
端口数量: | 2 | 端子数量: | 128 |
字数: | 32768 words | 字数代码: | 32000 |
工作模式: | SYNCHRONOUS | 最高工作温度: | 70 °C |
最低工作温度: | 组织: | 32KX18 | |
输出特性: | 3-STATE | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | LFQFP | 封装等效代码: | QFP128,.63X.87,20 |
封装形状: | RECTANGULAR | 封装形式: | FLATPACK, LOW PROFILE, FINE PITCH |
并行/串行: | PARALLEL | 峰值回流温度(摄氏度): | 240 |
电源: | 2.5/3.3,3.3 V | 认证状态: | Not Qualified |
座面最大高度: | 1.6 mm | 最大待机电流: | 0.015 A |
最小待机电流: | 3.15 V | 子类别: | SRAMs |
最大压摆率: | 0.36 mA | 最大供电电压 (Vsup): | 3.45 V |
最小供电电压 (Vsup): | 3.15 V | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | COMMERCIAL | 端子面层: | Tin/Lead (Sn85Pb15) |
端子形式: | GULL WING | 端子节距: | 0.5 mm |
端子位置: | QUAD | 处于峰值回流温度下的最长时间: | 20 |
宽度: | 14 mm | Base Number Matches: | 1 |
IDT70V3379S5PRF 数据手册
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PDF下载HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3379S
Features:
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)
and 208-pin fine pitch Ball Grid Array, and 256-pin
BallGridArray
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
◆
◆
◆
◆
◆
◆
– Commercial:4.2/5/6ns (max.)
– Industrial:5/6ns (max)
Pipelined output mode
◆
◆
◆
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHzoperation(9.6Gbps bandwidth)
– Fast 4.2ns clock to data out
◆
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
FunctionalBlockDiagram
UBL
UBR
LBR
L
LB
R/WL
R/WR
B
B
B B
W W
W W
0
L
1
L
1
R
0
R
CE0L
CE0R
1L
CE
1R
CE
OEL
OER
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
32K x 18
MEMORY
ARRAY
,
.
I/O0 L - I/O1 7 L
Din_L
Din_R
I/O0R - I/O17R
L
CLK
CLKR
A14L
A14R
Counter/
Address
Reg.
Counter/
Address
Reg.
A0L
A0R
ADDR_L
ADDR_R
L
CNTRST
R
CNTRST
ADSR
L
ADS
CNTENL
CNTENR
4833 tbl 01
APRIL 2001
1
DSC 4833/8
©2001IntegratedDeviceTechnology,Inc.
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70V3379isahigh-speed32Kx18bitsynchronousDual-Port inbursts.Anautomaticpowerdownfeature,controlledbyCE0andCE1,
RAM. The memory array utilizes Dual-Port memory cells to allow permitstheon-chipcircuitryofeachporttoenteraverylowstandbypower
simultaneousaccessofanyaddressfrombothports.Registersoncontrol, mode.
data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming
The70V3379cansupportanoperatingvoltageofeither3.3Vor2.5V
latitudeprovidedbythisapproachallowssystemstobedesignedwithvery ononeorbothports,controllablebytheOPTpins.Thepowersupplyfor
shortcycletimes.Withaninputdataregister,theIDT70V3379hasbeen the core ofthe device (VDD)remains at3.3V.
optimizedforapplicationshavingunidirectionalorbidirectionaldataflow
PinConfiguration(1,2,3,4)
1
2
3
4
5
6
7
8
9
11 12 13 14
16 17
10
15
I/O9L
VSS
NC
NC
A12L
NC
NC
A8L
NC
VDD
A0L
OPTL
A
B
C
D
E
F
VSS
NC
CLKL CNTEN
L
A4L
A1L
A2L
NC
VSS
NC
A9L
A10L
A7L
VSS
VSS
OE
VSS
NC
CE0L
ADSL
VSS
VDDQR
I/O8L
NC
NC
NC
NC
A13L
A5L
I/O9R
VSS
VDDQR
VDD
A14L
VDDQL
L
I/O8R
UB
V
DD
V
SS
CE1L
A6L
A3L
R/WL
NC
I/O10L
NC
V
DDQL
A11L
V
DD
I/O7R
NC
LB
L
V
DD
NC
NC
L
I/O7L
VSS
NC
CNTRST
L
I/O11L
NC
VDDQR I/O10R
I/O6L
VSS
NC
I/O6R
VDDQL I/O11R
V
DDQR
NC
VSS
NC
NC
VSS
NC
VDD
I/O12L
NC
VDD
VSS
I/O5L
VSS
VDDQL
NC
G
H
J
VDDQR I/O12R
NC
I/O5R
VDD
70V3379BF
BF-208(5)
VDDQL
VDD
VSS
VDDQR
VSS
VSS
208-Pin fpBGA
Top View(6)
I/O3R
I/O4R
I/O14R
NC
VDDQL
VSS
I/O4L
VDDQR
I/O2L
NC
VSS
I/O13R
SS
K
L
V
I/O14L
VDDQR
I/O13L
VSS
I/O2R
NC
NC
VSS
I/O
3L
VDDQL
NC
VSS
I/O15R
NC
VSS
NC
M
N
P
R
T
NC
VDDQL
I/O15L
NC
I/O1R
I/O16L
I/O16R
VDDQR
A8R
NC
NC
NC
A13R
A14R
A11R
A12R
NC
I/O1L
VSS
VDD
CLKR CNTEN
R
A4R
NC
V
SS
I/O17R
CE
0R
VDDQR
NC
NC
VSS
A9R
A10R
A7R
NC
UBR
LBR
ADSR
I/O0R
VSS
VSS
A5R
VDDQL
VSS
A1R
A2R
NC
I/O
17L
NC
VSS
CE1R
VDD
VSS
V
DDQL
A
6R
V
SS
NC
WR
R/
NC
NC
VDD
I/O0L
NC
OER CNTRST
R
A3R
VDD
NC
NC
OPTR
A
0R
U
4833 tbl 02
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
70V3379BC
BC-256(5)
256-Pin BGA
Top View(6)
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
NC
NC
NC
A11L
A8L
NC CE1L
A5L
A2L
A0L
CNTENL
NC
A14L
NC
NC
OEL
B1
B2
B3
B6
B7
B9
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
NC
NC
NC
A12L
A9L
A4L
A1L
CE0L
CNTRSTL
NC
NC
R/
VDD
NC
NC
UBL
WL
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
NC
A13L
A10L
I/O9L VSS
NC
A7L
NC
CLKL
A6L
A3L
I/O8L
LBL
ADSL
OPTL NC
D1
D2
D6
D9
D11
D3
D5
D7
D8
D10
D12
D13
D14
D15
D16
D4
NC I/O9R
VDDQL
VDDQL
VDDQR
NC
VDDQL
VDDQR VDDQR
VDDQL
VDDQR VDD
NC
NC I/O8R
VDD
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
VDD VDD
VSS
VSS
VSS
VSS
VDD
VDD VDDQR
I/O10R I/O10L NC VDDQL
NC
I/O7R
I/O7L
F7
F5
F6
F9
F10
F1
F2
F3
F11
F13
F14
F15
F16
F8
F12
F4
VSS
I/O11L NC I/O11R
VDD VSS
VSS
VSS
I/O6R NC I/O6L
VDDQR
VSS
VDDQL
VSS
VDD
G1
G5
G2
G4
G6
G8
G9
G3
G14
G15
G16
G7
G10
G12
G13
G11
NC
VSS
NC
VDDQR
VSS
VSS
VSS
I/O12L
I/O5L NC
NC
VSS
VSS
VSS
VDDQL
VSS
H11
H12
H16
H13
H7
H8
H9
H10
H14
H15
H5
H6
H3
H4
H1
H2
VSS VSS
I/O5R
VDDQL
VSS VSS
VSS
VSS
NC
NC
NC VDDQR VSS
VSS
NC I/O12R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O13L
VSS
I/O14R I/O13R VDDQL
VSS
VSS
VSS
VSS
VDDQR
VSS
VSS
VSS
I/O4R
I/O3R I/O4L
K6
K8
K10
K12
K13
K2
K4
K5
K7
K9
K11
K15
K16
K1
K3
K14
VSS
VSS
VSS
VSS
VDDQR
NC
VDDQL VSS
VSS
VSS
VSS
NC I/O3L
NC
I/O14L
NC
L7
L8
L11
L12
L13
L5
L6
L9
L10
L3
L4
L15
L16
L1
L2
L14
VSS
VSS
VSS VDD
VDDQL
I/O15R VDDQR VDD
VSS
VSS
VSS
NC I/O2R
I/O15L NC
I/O2L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1
M2
M3
M4
M16
M14
M15
VDD VDD
VSS
VSS
VSS
VSS
VDD VDD
VDDQL
I/O16R I/O16L NC VDDQR
NC
I/O1R I/O1L
N8
N12
N13
N16
N4
N5
N6
N7
N9
N10
N11
N15
N1
N2
N3
N14
VDDQL
VDDQL
NC
VDD
VDD VDDQR VDDQR VDDQL
VDDQR VDDQR VDDQL
I/O0R
NC I/O17R NC
NC
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
NC I/O17L NC
NC A13R
A7R
NC
CLKR
A6R
NC
NC
I/O0L
LBR
ADSR
A10R
A3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
NC A12R A9R
R/
NC
UBR CE0R
WR CNTRSTR
NC
NC
NC
NC
A4R
A1R OPTR
NC
T2
T3
T1
T4
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
NC
NC
NC
NC
A14R
NC
CE1R
NC
NC
A11R
A8R
R
OE CNTEN
R
A5R
A2R
A0R
4833 drw 02c
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
,
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
A1L
A0L
OPTL
NC (VSS)(7)
IO8L
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
A14L
NC
VSS
NC
IO9L
IO9R
VDDQL
IO8R
NC (VSS)(7)
VSS
VDDQL
IO7L
IO7R
VSS
VDDQR
IO6L
IO6R
IO5L
IO5R
VDD
VDD
VSS
VSS
IO10L
9
10
IO10R
VDDQR
VSS
IO11L
IO11R
IO12L
IO12R
VDD
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
70V3379PRF
PK-128(5)
VDD
VSS
VSS
83
82
81
80
79
78
77
VSS
IO4R
IO4L
IO3R
IO3L
IO2R
IO13R
IO13L
IO14R
IO14L
128-Pin TQFP
Top View(6)
IO15R
IO15L
76
75
74
73
72
71
70
69
68
67
66
65
IO2L
VSS
VDDQL
IO1R
IO1L
VDDQL
VSS
IO16R
IO16L
VDDQR
VSS
27
28
29
30
31
32
33
34
35
36
37
38
VSS
VDDQR
IO0R
IO0L
IO17R
IO17L
NC
NC
NC
OPTR
A0R
A1R
A14R
.
4833 drw 02a
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign
these pins as Vss. Customers who plan to take advantage of the upgrade path should treat these pins as VSS on the 70V3379 and 70V3389. If no upgrade is
needed, the pins can be treated as NC.
6.42
4
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
CE0L
1L
CE0R 1R
, CE
Chip Enables
, CE
WL
R/
WR
R/
Read/Write Enable
Output Enable
OEL
OER
0L
A
14L
- A
0R
A
14R
- A
Address
0L
17L
0R
17R
I/O - I/O
I/O - I/O
Data Input/Output
Clock
L
CLK
R
CLK
ADSL
ADSR
Address Strobe Enable
Counter Enable
Counter Reset
Byte Enables (9-bit bytes)
CNTENL
CNTRSTL
CNTENR
CNTRSTR
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
L
L
R
R
UB - LB
UB - LB
Power (I/O Bus) (3.3V or 2.5V)(1)
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
DDQ L
DDQR
V
V
(1,2)
L
OPT
R
OPT
DDQX
Option for selecting V
DD
V
Power (3.3V)(1)
Ground (0V)
SS
V
4833 tbl 01
Truth Table IRead/Write and Enable Control(1,2,3)
Upper Byte Lower Byte
CLK
↑
0
CE1
H
R/W
X
L
I/O9-18
High-Z
High-Z
DIN
I/O0-8
High-Z
DIN
MODE
OE
X
X
X
X
L
CE
UB
H
H
L
LB
H
L
L
L
L
L
L
L
L
L
All Bytes Deselected
Write to Lower Byte Only
Write to Upper Byte Only
Write to Both Bytes
H
↑
H
H
L
L
High-Z
↑
IN
D
IN
D
H
L
L
↑
H
H
L
L
H
H
H
X
High-Z
DOUT
DOUT
High-Z
DOUT
Read Lower Byte Only
Read Upper Byte Only
Read Both Bytes
↑
L
H
H
L
↑
L
H
L
DOUT
↑
H
H
L
L
High-Z
High-Z
Outputs Disabled
↑
4833 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = VIH.
3. OE is an asynchronous input signal.
6.42
5
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2)
Previous
Address
Addr
Used
(6)
(3)
Address
CLK
I/O
DI/O(0)
DI/O (n) External Address Used
MODE
ADS CNTEN CNTRST
(4)
X
An
An
X
X
X
0
An
X
X
X
H
L
Counter Reset to Address 0
↑
↑
↑
↑
(4)
L
H
H
H
Ap
Ap
Ap
H
H
DI/O(p)
External Address Blocked—Counter disabled (Ap reused)
(5)
Ap + 1
L
DI/O(p+1) Counter Enabled—Internal Address generation
4833 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
RecommendedOperating
TemperatureandSupplyVoltage(1,2)
RecommendedDCOperating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
2.375 2.5
Max.
3.45
2.625
0
Unit
V
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
VDD
3.3V + 150mV
3.3V + 150mV
VDDQ
VSS
V
Industrial
0V
0
0
V
(2)
Input High Voltage(3)
1.7
V
____
4833 tbl 04
VDDQ + 125mV
VIH
NOTES:
(Address & Control Inputs)
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case tempereature.
(3)
(2)
____
____
VIH
VIL
Input High Voltage - I/O
1.7
VDDQ + 125mV
V
Input Low Voltage
-0.3(1)
0.7
V
4833 tbl 05a
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 125mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be
supplied as indicated above.
AbsoluteMaximumRatings(1)
Symbol
Rating
Commercial
& Industrial
Unit
(2)
VTE RM
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
RecommendedDCOperating
Conditions with VDDQ at 3.3V
TBIAS
Temp erature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
3.15 3.3
Max.
3.45
3.45
0
Unit
V
VDD
Storage
Temp erature
TSTG
VDDQ
VSS
V
IOUT
DC Output Current
mA
0
0
V
4833 tbl 06
(2)
____
Input High Voltage
(Address & Control Inputs)
2.0
VDDQ + 150mV
V
VIH
NOTES:
(3)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
(3)
____
____
(2)
VIH
Input High Voltage - I/O
2.0
VDDQ + 150mV
V
(1)
V
IL
Input Low Voltage
-0.3
0.8
V
4833 tbl 05b
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6.42
6
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
Max. Unit
CIN
VIN = 3dV
8
pF
(3 )
COUT
VOUT = 3dV
10.5
pF
4833 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3379S
Symbol
|ILI|
Parameter
Test Conditions
VDDQ = Max., VIN = 0V to VDDQ
Min.
Max.
10
Unit
µA
µA
V
(1)
___
___
___
Input Leakage Current
|ILO|
Output Leakage Current
0
IH
1
IL OUT
DDQ
10
CE = V or CE = V , V = 0V to V
VOL (3.3V) Output Low Voltage(2)
VOH (3.3V) Output High Voltage(2)
VOL (2.5V) Output Low Voltage(2)
VOH (2.5V) Output High Voltage(2)
IOL = +4mA, VDDQ = Min.
0.4
___
IOH = -4mA, VDDQ = Min.
2.4
V
___
IOL = +2mA, VDDQ = Min.
0.4
V
___
IOH = -2mA, VDDQ = Min.
2.0
V
4833 tbl 08
NOTE:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.
6.42
7
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V3379S4
Com'l Only
70V3379S5
Com'l
70V3379S6
Com'l
& Ind
& Ind
Symbol
DD
Parameter
Test Condition
Version
COM'L
Typ.(4)
375
Max.
460
Typ.(4)
Max.
Typ.(4)
Max.
Unit
I
Dynamic Ope rating
Current (Both
Ports Active )
mA
L
R
CE and CE = VIL
,
S
S
S
S
S
S
S
S
S
S
285
285
105
105
190
190
6
360
245
245
95
310
360
125
150
225
260
15
Outputs Disabled,
____
____
(1)
IND
415
145
175
260
300
15
f = fMAX
I
SB1
Standby Current
(Both Ports - TTL
Le ve l Inputs)
mA
mA
mA
CEL
f = fMAX
=
CER = VIH
COM'L
IND
145
190
(1)
____
____
95
(5)
I
SB2
Standby Current
(One Port - TTL
Le ve l Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disable d,
COM'L
IND
265
325
175
175
6
____
____
(1)
MAX
f=f
I
SB3
Full Standby Current Both Ports CEL and
(Both Ports - CMOS CER > VDD - 0.2V, VIN > VDD - 0.2V
Le ve l Inputs)
COM'L
IND
6
15
____
____
(2)
6
30
6
30
IN
or V < 0.2V, f = 0
(5)
I
SB4
Full Standby Current
(One Port - CMOS
Le ve l Inputs)
mA
CE"A" < 0.2V and CE"B" > VDD - 0.2V
IN > VDD - 0.2V or VIN < 0.2V, Active
Port, Outputs Disable d, f = fMAX
COM'L
IND
265
325
180
180
260
300
170
170
225
260
V
____
____
(1)
4833 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
8
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
2.5V
AC Test Conditions
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.35V
GND to 3.0V/GND to 2.35V
3ns
833Ω
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
DATAOUT
1.5V/1.25V
5pF*
770
Ω
Figures 1, 2, and 3
4833 tbl 10
,
3.3V
50Ω
50Ω
590Ω
5pF*
,
DATAOUT
1.5V/1.25
10pF
DATAOUT
(Tester)
4833 drw 03
435Ω
Figure 1. AC Output Test load.
,
4833 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
3
∆tCD
(Typical, ns)
2
1
•
•
•
•
20.5
50
80 100
200
30
-1
Capacitance (pF)
4833 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
·
6.42
9
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3379S4
Com'l Only
70V3379S5
Com'l
70V3379S6
Com'l
& Ind
& Ind
Symbol
Parameter
Clock Cycle Time (Pipelined)
Clock High Time (Pipelined)
Clock Low Time (Pipelined)
Clock Rise Time
Min.
7.5
3
Max.
Min.
10
Max.
Min.
12
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
tCYC2
tCH2
tCL2
tR
4
5
3
4
5
____
____
____
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
tSA
tHA
tSC
tHC
tSB
Address Setup Time
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
HB
t
tSW
tHW
tSD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
ADS Setup Time
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
tHRST
(1)
0.7
0.7
1.0
CNTRST Hold Time
____
____
____
OE
t
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Pipelined)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
4
5
6
____
____
____
tOLZ
tOHZ
tCD2
tDC
0
0
0
1
4
1
4.5
1
5
____
____
____
4.2
5
6
____
____
____
1
1
1
1
1
1
1
1.5
1
tCKHZ
tCKLZ
3
4.5
6
____
____
____
Port-to-Port Delay
____
____
____
tCO
Clock-to-Clock Offset
6
8
10
ns
4833 tbl 11
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
6.42
10
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
(3)
tSC tHC
CE1
tSB
(5)
tHB
tHB
tSB
UB, LB(0-3)
R/W
tHW
tHA
tSW
tSA
ADDRESS(4)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (5)
DATAOUT
Qn + 1
(1)
tCKLZ
tOHZ
tOLZ
tOE
(1)
OE
NOTES:
4833 drw 06
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB or LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
tSA tHA
A6
A5
A4
A3
A2
A0
A1
tSC tHC
tSC tHC
tCD2
tCD2
tCKHZ
tDC
tCD2
Q0
Q3
A5
Q1
A3
DATAOUT(B1)
ADDRESS(B2)
tDC
tCKLZ
tCKHZ
tSA tHA
A0
A6
A4
A2
A1
tSC tHC
CE0(B2)
tSC tHC
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
NOTES:
4833 drw 07
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3379 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
11
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2)
L
CLK
tSW tHW
R/WL
tSA tHA
MATCH
NO
MATCH
ADDRESSL
DATAINL
CLKR
tSD
tHD
VALID
(3)
tCO
tCD2
WR
R/
tSW tHW
tSA tHA
NO
ADDRESSR
DATAOUTR
MATCH
MATCH
VALID
tDC
4833 drw 08
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC + tCD2).
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE
0
tSC tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
ADDRESS(3)
An + 3
An + 4
An
tSA tHA
An +1
An + 2
An + 2
tSD
Dn + 2
tHD
DATAIN
tCD2
tCD2
(1)
tCKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP(4)
WRITE
READ
4833 drw 09
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
12
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB LB
,
tSW tHW
R/W
tSW tHW
(3)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
tSA tHA
tSD tHD
DATAIN
Dn + 2
tCD2
tCD2
tCKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
4833 drw 10
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
4833 drw 11
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
13
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn
Dn + 4
Dn + 1
Dn + 3
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
4833 drw 12
Timing Waveform of Counter Reset(2)
tCYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax
0
1
An
An + 1
tSW tHW
R/W
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
NOTES:
4833 drw 13
1. CE0,
, and R/W = VIL; CE1 and CNTRST = VIH.
UB, LB
UB, LB
CE0,
= VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
14
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
Depth and Width Expansion
TheIDT70V3379providesatruesynchronousDual-PortStaticRAM
interface. Registered inputs provide minimal set-up and hold times on
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked
ontherisingedgeoftheclock signal,however,theself-timedinternalwrite
pulseisindependentoftheLOWtoHIGHtransitionoftheclocksignal.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
The IDT70V3379 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
TheIDT70V3379canalsobeusedinapplicationsrequiringexpanded
width,asindicatedinFigure4.Throughcombiningthecontrolsignals,the
devices can be grouped as necessary to accommodate applications
needing 36-bits or wider.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enablesalloweasierbankingofmultipleIDT70V3379sfordepthexpan-
sion configurations. Two cycles are required with CE0 LOW and CE1
HIGHtore-activatetheoutputs.
A15
IDT70V3379
IDT70V3379
CE0
CE0
CE1
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V3379
IDT70V3379
CE1
CE1
CE0
CE0
UB, LB
R/W,
Control Inputs
Control Inputs
OE,
CLK,
.
ADS,
4833 drw 14
CNTRST,
CNTEN
Figure 4. Depth and Width Expansion with IDT70V3379
6.42
15
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BF
PRF
BC
208-pin fpBGA (BF-208)
128-pin TQFP (PK-128)
256-pin BGA (BC-256)
Commercial Only
4
5
6
Commercial & Industrial
Speed in nanoseconds
Commercial & Industrial
S
Standard Power
70V3379 576K (32K x 18-Bit) Synchronous Dual-Port RAM
4833 drw 15A
6.42
16
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory
1/18/98:
3/15/99:
4/28/99:
6/8/99:
6/11/99:
7/14/99:
8/4/99:
InitialPublicRelease
Page 10 AdditionalNotes
AddedfpBGApackage
Page 2 Changedpackagebodyheightfrom1.5mmto1.4mm
Page 5 Deleted note 6 for Table II
Page 2 Corrected pin to T3 to VDDQL
Page 6 Improved power numbers
10/4/99:
11/12/99:
2/28/00:
5/1/00:
Upgraded speed to 133MHz, added 2.5V I/O capability
Replaced IDT logo
AddednewBGApackage,addedfull2.5Vinterfacecapability
Page 2 Addedballpitch
Page 3 Renamedpins
Page 6 Madecorrections toTruthTable
Page 9 Changed Ω numbers in figure 2
Page 4 Addedinformationtopinandpinnotes
Page 6 Increatedstoragetemperatureparameter
ClarifiedTAParameter
6/7/00:
Page 8 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Removednote7onDCElectricalCharacteristicstable
Page 1 Changed 64K to 32K in block drawing
RemovedPreliminarystatus
AddedIndustrialTemperatureRangesandremovedrelatednotes
1/10/01:
4/10/01:
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
17
IDT70V3379S5PRF 相关器件
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