IDT70V658S10BF [IDT]
HIGH-SPEED 3.3V 64K X 36 ASYNCHRONOUS DUAL-PORT STATIC RAM; 高速3.3V 64K ×36异步双端口静态RAM型号: | IDT70V658S10BF |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | HIGH-SPEED 3.3V 64K X 36 ASYNCHRONOUS DUAL-PORT STATIC RAM |
文件: | 总23页 (文件大小:196K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
IDT70V658S
HIGH-SPEED 3.3V 64K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
Features
True Dual-Port memory cells which allow simultaneous
◆
◆
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
LVTTL-compatible, single 3.3V (±150mV) power supply
for core
access of the same memory location
High-speed access
◆
◆
◆
– Commercial:10/12/15ns (max.)
– Industrial:12/15ns (max.)
Dual chip enables allow for depth expansion without
◆
◆
◆
external logic
◆
IDT70V658 easily expands data bus width to 72 bits or
◆
◆
◆
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
◆
On-chip port arbitration logic
Functional Block Diagram
3
BE
L
BE
3
2
R
R
BE
2
L
BE
BE
BE
1
BE
BE
1
0
R
L
L
0
R
R/W
R/
W
R
L
B
E
0
L
B
E
1
L
B
E
2
L
B
E
3
L
B
E
3
B
E
2
B
E
1
B
E
0
CE0
CE
0
R
R R
R
L
R
CE1
R
CE1
L
OE
OE
R
L
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_R
Dout27-35_R
Dout18-26_L
Dout27-35_L
64K x 36
MEMORY
ARRAY
I/O - I/O
0L 35L
Di n_L
Di n_R
I/O - I/O
0R 35R
A
A
15R
0R
A15 L
A0 L
Address
Decoder
Address
Decoder
ADDR_L
ADDR_R
CE
CE1
0
CE
0
L
R
ARBITRATION
R
CE1
INTERRUPT
SEMAPHORE
LOGIC
L
OE
OE
R
L
R/W
L
R/W
R
BUSY
SEM
BUSY
R
L
SEM
M/S
L
R
INT
INT
L
R
TMS
TCK
TDI
JTAG
TDO
TRST
5613 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
JUNE 2001
1
DSC-5613/3
©2001IntegratedDeviceTechnology,Inc.
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
TheIDT70V658is ahigh-speed64Kx36Asynchronous Dual-Port address,andI/Opinsthatpermitindependent,asynchronousaccessfor
Static RAM. The IDT70V658 is designed to be used as a stand-alone reads or writes to any location in memory. An automatic power down
2304K-bitDual-PortRAMoras acombinationMASTER/SLAVEDual- feature controlled by the chip enables (either CE0 or CE1) permit
Port RAM for 72-bit-or-more word system. Using the IDT MASTER/ theon-chipcircuitryofeachporttoenteraverylowstandbypowermode.
SLAVE Dual-Port RAM approach in 72-bit or wider memory system
The70V658cansupportanoperatingvoltageofeither3.3Vor2.5V
applicationsresultsinfull-speed,error-freeoperationwithouttheneedfor on one or both ports, controlled by the OPT pins. The power supply for
additionaldiscretelogic.
the core ofthe device (VDD)remains at3.3V.
This device provides two independent ports with separate control,
PinConfigurations(1,2,3,4)
1
2
3
4
5
6
7
8
9
11 12 13 14
10
16 17
15
I/O19L
DD
V
0L
17L
I/O
SS
V
A
B
C
D
E
F
18L
A
12L
8L
I/O
SS
NC
A
L
A4
A
L
V
NC
L
OPT
TDO
BE1L
SEM
INT
L
A
B
C
D
E
F
20R
I/O
SS
9L
V
18R
A
15R
I/O16L I/O
I/O
SS
SS
V
V
A5
L
TDI
13L
1L
NC
NC
A
A
A
SS
V
DDQR
CE
0L
V
BUSYL
BE2L
BE3L
A
A
10L
V
SS
19R
DDQL I/O
V
DD
14L
CE1L
A
2L
V
DD
I/O16R I/O15L
V
V
DDQR
A6
L
L
WL
R /
I/O22L
V
SS
I/O17R
I/O12L
I/O21L
20L
A
15L
A
11L
7L
V
DD
NC
V
DDQL
I/O14L I/O14R
I/O
A3
V
DD
BE0L
OEL
I/O23L I/O22R
V
DDQR I/O21R
I/O13R
V
SS
I/O13L
V
DDQL I/O23R
V
SS
12R
I/O
V
DDQR
I/O24L
I/O25L
V
SS
I/O11L
I/O10L
I/O26L
V
SS
I/O9L
V
DDQL
9R
G
H
J
I/O24R
I/O11R
G
H
J
70V658BF
BF-208(5)
V
DD
I/O26R
DDQR
V
DD
25R
I/O
V
I/O
SS
V
10R
I/O
V
DD
V
DDQL
SS
V
V
SS
V
DDQR
V
DD
V
SS
V
SS
208-Ball fpBGA
Top View(6)
I/O7R
I/O6R
V
DDQL
V
SS
I/O8R
V
SS
I/O28R
I/O27R
K
L
V
SS
K
L
I/O29R I/O28L
V
DDQR
I/O27L
V
SS
I/O
I/O
7L
6L
I/O8L
V
DDQL
I/O30R
V
SS
I/O29L
I/O
5R
V
SS
V
DDQR
M
N
P
R
T
M
N
P
R
T
I/O31L
V
SS
I/O3R
V
DDQL
I/O
4R
I/O31R I/O30L
I/O5L
I/O4L
32R
I/O
32L
DDQR
DD
R
4R
A
I/O
2L
I/O3L
V
SS
I/O
V
TRST
12R
8R
A
V
INT
35R
NC
A
I/O
BE1R
SEM
R
V
SS
V
DDQL
I/O1R
V
DDQR
SS
SS
13R
A
9R
V
V
A
5R
A
1R
2R
A
V
SS
TCK
NC
NC
BE2R
BE3R
I/O33L
I/O34R
CE0
R
BUSY
R
I/O0R
V
SS
V
SS
A
I/O2R
I/O1L
A
6R
A
14R
A
10R
CE1R
WR
R/
I/O33R I/O34L
V
DDQL TMS
V
DD
OPT
R
I/O0L
11R
A
7R
V
DD
A
3R
A
0R
A
S
M/
V
SS
V
DD
BE0R
OER
I/O35L
NC
A
15R
U
U
5613 tbl 02b
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V)
3. All VSS pins must be connected to ground.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3,4) (con't.)
I/O16L
156
1
2
3
4
5
6
7
8
I/O19L
I/O19R
I/O20L
I/O20R
VDDQL
I/O16R
155
I/O15L
154
I/O15R
153
VSS
152
VDDQL
151
V
SS
I/O14L
150
I/O21L
I/O14R
149
I/O
21R
I/O13L
148
9
I/O
22L
I/O13R
147
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O22R
DDQR
VSSQR
146
V
VDDQR
145
V
SS
I/O12L
144
I/O
23L
I/O12R
143
I/O
I/O24L
24R
23R
I/O11L
142
I/O11R
141
I/O
VSS
140
VDDQL
VSS
VDDQL
139
I/O10L
138
I/O25L
I/O25R
I/O26L
I/O26R
VDDQR
VSS
VDD
VDD
VSS
VSS
I/O10R
137
I/O9L
136
70V658DR
DR-208(5)
I/O9R
135
VSS
134
VDDQR
133
VDD
132
VDD
131
VSS
130
208-Pin PQFP
Top View(6)
VSS
129
VSS
128
VDDQL
VSS
VDDQL
127
I/O8R
126
I/O27R
I/O27L
I/O28R
I/O28L
VDDQR
VSS
I/O29R
I/O29L
I/O30R
I/O30L
VDDQL
VSS
I/O31R
I/O31L
I/O32R
I/O32L
VDDQR
I/O8L
125
I/O7R
124
I/O7L
123
VSS
122
VDDQR
121
I/O6R
120
I/O6L
119
I/O5R
118
I/O5L
117
VSS
116
VDDQL
115
I/O4R
114
I/O4L
113
I/O3R
112
I/O3L
111
VSS
110
VDDQR
109
V
SS
I/O2R
108
I/O
33R
I/O2L
107
I/O
33L
34R
I/O1R
106
I/O
I/O34L
I/O1L
105
5613 drw 02a
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V)
3. All VSS pins must be connected to ground.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
3
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
70V658BC
BC-256(5)
256-Pin BGA
Top View(6)
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
NC
TDI
NC
A11L
A8L
CE1L
A5L
A2L
A0L
BE2L
INTL
NC
A14L
NC
NC
OEL
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
I/O18L NC TDO
A12L
A9L
NC
A4L
A1L
NC
A15L
R/
NC I/O17L NC
BE3L
WL
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
I/O18R
A13L
A10L
I/O19L VSS
NC
A7L
A6L
A3L
I/O16L
BE1L BE0L SEML BUSY
L
OPTL I/O17R
D1
D2
D6
D9
D11
D3
D5
D7
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
VDDQL
VDDQL
VDDQR
VDDQR VDD I/O15R I/O15L I/O16R
I/O20L
VDDQL
VDDQR VDDQR
VDDQL
VDD
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
VDD VDD
VSS
VSS
VSS
VSS
VDD
VDD V
DDQR I/O13L
I/O21R I/O21L I/O22L VDDQL
I/O14R
I/O14L
F7
F5
F6
F9
F10
F1
F2
F3
F11
F13
F14
F15
F16
F8
F12
F4
VSS
I/O23L I/O22R I/O23R
VDD VSS
VSS
VSS
I/O12R I/O13R I/O12L
VDDQR
VSS
VDDQL
VSS
VDD
G1
G5
G2
G4
G6
G8
G9
G3
G14
G15
G16
G7
G10
G12
G13
G11
I/O24R
VSS
I/O24L
VDDQR
VSS
VSS
VSS
I/O25L
I/O10L I/O11L I/O11R
VSS
VSS
VSS
VDDQL
VSS
H11
H12
H16
H13
H7
H8
H9
H10
H14
H15
H5
H6
H3
H4
H1
H2
VSS VSS
I/O10R
VDDQL
I/O9R IO9L
VSS VSS
VSS
VSS
I/O26R VDDQR VSS
VSS
I/O26L I/O25R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O27L
VSS
I/O28R I/O27R VDDQL
VSS
VSS
VSS
VSS
VDDQR
VSS
VSS
VSS
I/O8R
I/O7R I/O8L
K6
K8
K10
K12
K13
K2
K4
K5
K7
K9
K11
K15
K16
K1
K3
K14
VSS
VSS
VSS
VSS
VDDQR
I/O29L
VDDQL VSS
VSS
VSS
VSS
I/O6L I/O7L
I/O29R
I/O28L
I/O6R
L7
L8
L11
L12
L13
L5
L6
L9
L10
L3
L4
L15
L16
L1
L2
L14
VSS
VSS
VSS VDD
VDDQL
I/O30R VDDQR VDD
VSS
VSS
VSS
I/O4R I/O5R
I/O30L I/O31R
I/O5L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1
M2
M3
M4
M16
M14
M15
VDD VDD
VSS
VSS
VSS
VSS
VDD VDD
VDDQL
I/O32R I/O32L I/O31L VDDQR
I/O4L
I/O3R I/O3L
N8
N12
N13
N16
N4
N5
N6
N7
N9
N10
N11
N15
N1
N2
N3
N14
VDDQL
VDDQL
I/O2R
I/O1R
VDD
VDD VDDQR VDDQR VDDQL
VDDQR VDDQR VDDQL
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
I/O35R I/O34L TMS NC A13R
A7R
A6R
I/O0L I/O0R I/O1L
BE1R BE0R SEMR BUSY
R
A10R
A3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
A15R A12R A9R
R/
M/
NC
BE3R CE0R
WR
S
I/O35L NC
NC
A4R
A1R OPTR
TRST
NC
T2
T3
T1
T4
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
TCK
NC
NC
NC
A14R
2R CE1R
NC
NC
BE
A11R
A8R
R
R
INT
A5R
A2R
A0R
OE
5613 drw 02c
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
,
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
4
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables
CE0L CE1L
CE0R CE1R
,
,
R/WL
R/WR
Read/Write Enable
Output Enable
OEL
OER
A0L - A15L
I/O0L - I/O35L
A0R - A15R
I/O0R - I/O35R
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
SEML
SEMR
INTL
INTR
Busy Flag
BUSYL
BE0L - BE3L
VDDQ L
OPTL
BUSYR
BE0R - BE3R
VDDQR
OPTR
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)(1)
(1,2)
Option for selecting VDDQX
M/S
Master or Slave Select
Power (3.3V)(1)
VDD
VSS
Ground (0V)
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
TDI
Test Data Input
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
TDO
TCK
TMS
TRST
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5613 tbl 01
5
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IRead/Write and Enable Control(1,2)
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CE1
X
L
R/W
X
X
X
L
MODE
OE
X
X
X
X
X
X
X
X
X
X
L
SEM CE0
BE3
X
X
H
H
H
H
L
BE2
X
X
H
H
H
L
BE1
X
X
H
H
L
BE0
X
X
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DIN
High-Z Deselected–Power Down
High-Z Deselected–Power Down
High-Z All Bytes Deselected
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
DIN
Write to Byte 0 Only
H
H
H
L
L
High-Z Write to Byte 1 Only
High-Z Write to Byte 2 Only
High-Z Write to Byte 3 Only
H
H
L
L
High-Z
High-Z
DIN
IN
D
H
H
L
L
High-Z
High-Z
DIN
H
L
L
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
H
L
H
L
L
High-Z
DIN
High-Z Write to Upper 2 bytes Only
L
L
L
DIN
DIN
DIN
Write to All Bytes
Read Byte 0 Only
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
High-Z
High-Z
High-Z
DOUT
High-Z
High-Z
DOUT
High-Z
DOUT
DOUT
L
H
H
H
L
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
L
H
H
L
High-Z
High-Z
DOUT
L
H
H
L
High-Z
High-Z
DOUT
L
H
L
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
L
H
L
H
L
High-Z
DOUT
High-Z Read Upper 2 Bytes Only
L
L
L
DOUT
DOUT
DOUT
Read All Bytes
H
L
L
L
L
High-Z
High-Z
High-Z
High-Z Outputs Disabled
5613 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II Semaphore Read/Write Control(1)
Inputs(1)
Outputs
(2)
R/W
H
I/O1-35
I/O0
Mode
CE
OE
L
BE3
BE2
L
BE1
L
BE0
L
SEM
L
H
L
X
X
DATAOUT
DATAOUT Read Data in Semaphore Flag(3)
H
L
X
X
X
L
L
X
DATAIN
Write I/O0 into Semaphore Flag
Not Allowed
↑
______
______
X
X
X
X
X
L
5613 tbl 03
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A0-A2.
2. CE = L occurs when CE0 = VIL and CE1 = VIH.
3. Each byte is controlled by the respective BEn. To read data BEn = VIL.
6
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage(1)
Ambient
RecommendedDCOperating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
Max.
3.45
2.6
0
Unit
V
Grade
Temperature
0OC to +70OC
-40OC to +85OC
GND
VDD
VDD
3.15 3.3
Commercial
0V
3.3V + 150mV
3.3V + 150mV
VDDQ
VSS
2.4
0
2.5
V
Industrial
0V
0
V
5613 tbl 04
(2)
Input High Voltage(3)
1.7
V
____
VDDQ + 100mV
VIH
NOTE:
(Address & Control Inputs)
1. This is the parameter TA. This is the "instant on" case temperature.
(3)
(2)
____
____
VIH
VIL
Input High Voltage - I/O
1.7
VDDQ + 100mV
V
Input Low Voltage
-0.5(1)
0.7
V
5613 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 100mV.
AbsoluteMaximumRatings(1)
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPTpinforthatportmustbesettoVIL (0V),andVDDQX forthatportmustbesupplied
as indicated above.
Symbol
Rating
Commercial
& Industrial
Unit
(2)
VTE RM
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
RecommendedDCOperating
Conditions with VDDQ at 3.3V
Storage
Temperature
TSTG
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
3.15 3.3
Max.
3.45
3.45
0
Unit
V
IOUT
DC Output Current
mA
VDD
5613 tbl 05
VDDQ
VSS
V
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
0
0
V
(2)
____
Input High Voltage
(Address & Control Inputs)
2.0
VDDQ + 150mV
V
VIH
(3)
(3)
____
____
(2)
VIH
Input High Voltage - I/O
2.0
VDDQ + 150mV
V
(1)
V
IL
Input Low Voltage
-0.3
0.8
V
5613 tbl 07
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
Max. Unit
CIN
VIN = 3dV
8
pF
(3 )
COUT
VOUT = 3dV
10.5
pF
5613 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
7
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V658S
Max.
Symbol
|ILI|
Parameter
Test Conditions
VDDQ = Max., VIN = 0V to VDDQ
Min.
Unit
µA
µA
V
(1)
___
Input Leakage Current
10
10
___
___
|ILO|
Output Leakage Current
CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
IOL = +4mA, VDDQ = Min.
VOL (3.3V) Output Low Voltage(2)
VOH (3.3V) Output High Voltage(2)
VOL (2.5V) Output Low Voltage(2)
VOH (2.5V) Output High Voltage(2)
0.4
___
IOH = -4mA, VDDQ = Min.
2.4
V
___
IOL = +2mA, VDDQ = Min.
0.4
V
___
IOH = -2mA, VDDQ = Min.
2.0
V
5613 tbl 09
NOTE:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V658S10
Com'l Only
70V658S12
Com'l
70V658S15
Com'l
& Ind
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
340
Max.
500
Typ.(4)
315
365
90
Max. Typ.(4)
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
440
CEL and CER= VIL,
Outputs Disabled,
S
S
S
S
S
S
S
S
S
S
465
515
125
150
325
365
15
300
350
____
____
(1)
IND
490
f = fMAX
ISB1
ISB2
ISB3
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
mA
CEL = CER = VIH
COM'L
IND
115
165
75
100
125
315
350
15
(1)
f = fMAX
____
____
100
115
200
225
3
(5)
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
COM'L
IND
225
340
175
200
____
____
(1)
f=fMAX
Full Standby Current Both Ports CEL and
COM'L
IND
3
15
3
(Both Ports - CMOS CER > VDD - 0.2V, VIN > VDD - 0.2V
____
____
or VIN < 0.2V, f = 0(2)
6
15
6
15
Level Inputs)
(5)
I
Full Standby Current
(One Port - CMOS
Level Inputs)
mA
SB4
CE"A" < 0.2V and CE"B" > VDD - 0.2V
VIN > VDD - 0.2V or VIN < 0.2V, Active
Port, Outputs Disabled, f = fMAX
COM'L
IND
220
335
195
220
320
360
170
195
310
345
____
____
(1)
5613 tbl 10
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
8
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
2.5V
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels
GND to 3.0V / GND to 2.5V
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
833Ω
1.5V/1.25V
1.5V/1.25V
DATAOUT
Figures 1 and 2
5613 tbl 11
5pF*
770
Ω
,
3.3V
590Ω
5pF*
50Ω
50Ω
,
DATAOUT
OUT
DATA
1.5V/1.25
10pF
435Ω
(Tester)
5613 drw 03
Figure 1. AC Output Test load.
,
5613 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
3
∆tAA
(Typical, ns)
2
1
•
•
•
•
,
20.5
50
80 100
200
30
-1
Capacitance (pF)
5613 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
9
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(5)
70V658S10
Com'l Only
70V658S12
Com'l
& Ind
70V658S15
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
AA
t
Address Access Time
10
10
5
12
12
6
15
15
7
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
____
____
____
____
____
____
____
____
____
tACE
tABE
tAOE
tOH
5
6
7
____
____
____
Output Hold from Address Change
Output Low-Z Time(1,2)
3
0
0
3
0
0
3
0
0
____
____
____
tLZ
tHZ
Output High-Z Time(1,2)
4
6
8
tPU
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
____
____
____
____
____
____
tPD
10
4
10
6
15
8
____
____
____
tSOP
tSAA
3
10
3
12
3
20
ns
5613 tbl 12
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
70V658S10
Com'l Only
70V658S12
Com'l
& Ind
70V658S15
Com'l
& Ind
Symbol
WRITE CYCLE
tWC
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Write Cycle Time
10
8
12
10
10
0
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
EW
t
tAW
tAS
8
0
tWP
8
10
0
12
0
tWR
tDW
tDH
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time(4)
0
6
8
10
0
0
0
(1,2)
____
____
____
tWZ
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM
4
4
4
____
____
____
tOW
tSWRD
tSPS
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
Flag Write to Read Time
SEM Flag Contention Window
ns
5613 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.
10
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE(6)
(4)
tAOE
OE
(4)
tABE
BEn
R/W
tOH
(1)
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3,4)
5613 drw 06
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE or BEn.
2. Timing depends on which signal is de-asserted first CE, OE or BEn.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
SB
50%
50%
.
5613 drw 07
I
11
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE SEM(9)
or
BEn(9)
(3)
(2)
(6)
tWR
tAS
tWP
W
R/
(7)
tOW
tWZ
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
5613 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
(9)
or
CE SEM
(6)
tAS
(3)
(2)
tWR
tEW
n(9)
BE
R/
W
tDW
tDH
DATAIN
5613 drw 09
NOTES:
1. R/W or CE or BEn = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
12
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM/BEn(1)
tOH
tSOP
tDW
IN
OUT
DATA
VALID(2)
I/O
DATA VALID
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
tSOP
Write Cycle
Read Cycle
5613 drw 10
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate BE controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O35) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
SIDE
R/W"B"
SEM"B"
"B"
5613 drw 11
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE control.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
13
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V658S10
Com'l Only
70V568S12
Com'l
& Ind
70V658S15
Com'l
& Ind
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
BUSY TIMING (M/S=VIH)
____
____
____
____
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
10
10
10
12
12
12
15
15
15
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
Access Time from Chip Enable Low
BUSY
10
12
15
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
____
____
____
10
12
15
____
____
____
8
10
12
BUSY TIMING (M/S=VIL)
BUSY Input to Write(4)
____
____
____
____
____
____
tWB
0
8
0
0
ns
ns
(5)
tWH
Write Hold After
10
12
BUSY
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
tWDD
tDDD
Write Pulse to Data Delay(1)
22
20
25
22
30
25
ns
Write Data Valid to Read Data Delay(1)
ns
5613 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
14
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
5613 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
(2)
R/W"B"
5613 drw 13
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
15
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1)
ADDR"A"
ADDRESSES MATCH
and "B"
"A"
CE
(2)
tAPS
CE"B"
tBAC
tBDC
"B"
BUSY
5613 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1)
"A"
"B"
"B"
ADDR
ADDRESS "N"
(2)
tAPS
ADDR
MATCHING ADDRESS "N"
BAA
BDA
t
t
BUSY
5613 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70V658S10
Com'l Only
70V658S12
Com'l
& Ind
70V658S15
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
tAS
Address Set-up Time
0
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
0
____
____
____
10
10
12
12
15
15
____
____
____
Interrupt Reset Time
ns
5613 tbl 15
16
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(4)
(3)
WR
t
tAS
"A"
CE
R/ "A"
W
(3)
INS
t
"B"
INT
5613 drw 16
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
(3)
tAS
"B"
CE
"B"
OE
(3)
tINR
"B"
INT
5613 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III Interrupt Flag(1,4)
Left Port
Right Port
R/
L
A15L-A0L
FFFF
X
R/
R
A15R-A0R
X
Function
Set Right INTR Flag
W
L
L
L
W
R
CE
OE
INT
CE
OE
R
INTR
(2)
L
X
X
X
L
X
X
L
X
X
X
L
X
X
X
L
X
L
L
X
X
L
L
(3)
X
FFFF
FFFE
X
H
Reset Right INTR Flag
Set Left INTL Flag
(3)
X
L
X
X
X
X
(2)
FFFE
H
X
Reset Left INTL Flag
5613 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
17
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV
Address BUSY Arbitration
Inputs
Outputs
AOL-A15L
AOR-A15R
(1)
(1)
Function
Normal
Normal
Normal
CEL
X
CER
X
BUSYL
BUSYR
NO MATCH
MATCH
H
H
H
H
H
X
X
H
MATCH
H
H
(3)
L
L
MATCH
(2)
(2)
Write Inhibit
5613 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V658
are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D35 Left
D0 - D35 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5613 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V658.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O35). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
The IDT70V658 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
locationinmemory.TheIDT70V658hasanautomaticpowerdownfeature
controlled by CE. The CE0 and CE1 control the on-chip power down
circuitrythatpermitstherespectiveporttogointoastandbymodewhen
notselected(CE =HIGH).Whenaportis enabled,access totheentire
memoryarrayispermitted.
FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left
port writes to memory location FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location FFFF. The
message (36 bits) at FFFE or FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations FFFE and FFFF are not used as mail boxes, but
as part of the random access memory. Refer to Truth Table III for
theinterruptoperation.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
18
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
andcorrupteddata inthe slave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
The IDT70V658 is an extremely fast Dual-Port 64K x 36 CMOS
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether Static RAM with an additional 8 address locations dedicated to binary
anduse anyBUSY indicationas aninterruptsource toflagthe eventof semaphore flags. These flags alloweitherprocessoronthe leftorright
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis side ofthe Dual-PortRAMtoclaima privilege overthe otherprocessor
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave for functions defined by the system designer’s software. As an ex-
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely ample, the semaphore can be used by one processor to inhibit the
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying other from accessing a portion of the Dual-Port RAM or any other
the BUSY pins HIGH. If desired, unintended write operations can be sharedresource.
prevented to a port by tying the BUSY pin for that port LOW.
The Dual-Port RAM features a fast access time, with both ports
The BUSY outputs on the IDT70V658 RAM in master mode, are being completely independent of each other. This means that the
push-pull type outputs and do not require pull up resistors to operate. activityontheleftportinnowayslows theaccess timeoftherightport.
Ifthese RAMs are beingexpandedindepth, thenthe BUSY indication Both ports are identical in function to standard CMOS Static RAM and
for the resulting array requires the use of an external AND gate.
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE, the Dual-Port RAM enable, and SEM, the
semaphore enable. The CE and SEM pins control on-chip power
downcircuitrythatpermits the respective porttogointostandbymode
whennotselected.
Systems which can best use the IDT70V658 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V658s
hardware semaphores, which provide a lockout mechanism without
requiringcomplexprogramming.
A16
CE0
CE0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
BUSY
R
R
BUSY
BUSY
L
L
CE1
CE1
R
MASTER
SLAVE
Dual Port RAM
Dual Port RAM
BUSY
BUSY
L
L
BUSY
BUSY
R
.
5613 drw 18
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70V658 RAMs.
Softwarehandshakingbetweenprocessors offers themaximumin
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V658 does not use its semaphore
flags to control any resources through hardware, thus allowing the
systemdesignertotalflexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speedsystems.
Width Expansion with Busy Logic
Master/SlaveArrays
When expanding an IDT70V658 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70V658 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthis method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen
The BUSY arbitration on a master is based on the chip enable and
19
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side
during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduring
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
verifiesitssuccessinsettingthelatchbyreadingit. Ifitwassuccessful,it
proceeds to assume control over the shared resource. If it was not
successfulinsettingthelatch,itdeterminesthattherightsideprocessor
has set the latch first, has the token and is using the shared resource.
The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquishedthetoken,theleftsideshouldsucceedingainingcontrol.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
sidewritesaonetothatlatch.
The eight semaphore flags reside within the IDT70V658 in a
separate memoryspace fromthe Dual-PortRAM. This address space
is accessedbyplacingalowinputontheSEM pin(whichacts as achip
select for the semaphore flags) and using the other control pins
(Address, CE R/W, and BEn) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When
accessing the semaphores, none of the other address pins has
anyeffect.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
is written into an unused semaphore location, that flag will be set to
a zero on that side and a one on the other side (see Truth Table V).
Thatsemaphorecannowonlybemodifiedbythesideshowingthezero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
fromtheothersideispending)andthencanbewrittentobybothsides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thor-
ough discussion on the use of this feature follows shortly.) A zero
written into the same location from the other side will be stored in the
semaphore request latch for that side until the semaphore is freed by
thefirstside.
SEMAPHORE
READ
SEMAPHORE
READ
5613 drw 19
Figure 4. IDT70V658 Semaphore Logic
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
secondside’s flagwillnowstay LOWuntilits semaphore requestlatch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
iswrittenintothatsemaphorerequestlatch.
Whena semaphore flagis read, its value is spreadintoalldata bits
so that a flag that is a one reads as a one in all data bits and a flag
containinga zeroreads as allzeros. The readvalue is latchedintoone
side’soutputregisterwhenthatside'ssemaphoreselect(SEM,BEn)and
output enable (OE) signals go active. This serves to disallow the
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE)
togoinactiveortheoutputwillneverchange.However,duringreadsBEn
functionsonlyasan outputforsemaphore.Itdoesnothaveany influence
onthesemaphorecontrollogic.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
The critical case of semaphore timing is when both sides request
a single tokenbyattemptingtowrite a zerointoitatthe same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
bothrequests arriveatthesametime,theassignmentwillbearbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misusedormisinterpreted, a software errorcaneasilyhappen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one,
all semaphores on both sides should have a one written into them
at initialization from both sides to assure that they will be free
when needed.
20
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
t
JCYC
t
JR
t
JF
t
JCL
t
JCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
t
JS
t
JH
Device Outputs(2)/
TDO
t
JRSR
tJCD
TRST
x
5613 drw 20
t
JRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
tJCYC
tJCH
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
____
____
____
ns
tJCL
40
ns
(1)
____
tJR
3
ns
(1)
____
tJF
3
ns
____
____
JRST
t
50
ns
tJRSR
tJCD
tJDC
tJS
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
____
25
ns
____
0
ns
____
____
15
15
ns
JH
t
JTAG Hold
ns
5613 tbl 19
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
21
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
IDT Device ID (27:12)
0x30B
0x33
1
Defines IDT part number
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
5613 tbl 20
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
5613 tbl 21
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1) .
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the by pass registe r (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
CLAMP
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
0011
0001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
RESERVED
All other codes
Several combinations are reserved. Do notuse codes other than those
identified above.
5613 tbl 22
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
22
IDT70V658S
Preliminary
High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0 C to +70 C)
°
°
Industrial (-40 C to +85 C)
°
°
BF
DR
BC
208-ball fpBGA (BF-208)
208-pin PQFP (DR-208)
256-ball BGA (BC-256)
10
12
15
Commercial Only
Commercial & Industrial
Commercial & Industrial
Speed in nanoseconds
S
Standard Power
70V658 2304K (64K x 36) Asynchronous Dual-Port RAM
5613 drw 21
PreliminaryDatasheet:Definition
"PRELIMINARY'datasheetscontaindescriptionsforproductsthatareinearlyrelease.
DatasheetDocumentHistory:
6/2/00:
8/7/00:
6/20/01:
InitialPublicOffering.
InsertedadditionalBEninformationonpages6,13,20.
Increased BUSY TIMINGparameterstBDA,tBAC,tBDC,tBDD forallspeedsonpage14.
ChangedmaximumvalueforJTAGACElectricalCharacteristicsfortJCD from20nsto25nsonpage21.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
23
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