IDT70V9169 [IDT]
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM;
| 型号： | IDT70V9169 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| 文件： | 总16页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70V9169/59L
HIGH-SPEED 3.3V 16/8K X 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
◆
Features:
Full synchronous operation on both ports
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:6.5/7.5/9ns(max.)
– Industrial: 7.5ns (max.)
– 3.5ns setup to clock and 0ns hold on all control, data, and
addressinputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timedwriteallowsfastcycletime
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V ( 0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83 MHz
◆
◆
Low-power operation
– IDT70V916/59L/59L
◆
Active:450mW(typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
◆
◆
◆
◆
◆
◆
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
Functional Block Diagram
R/WR
R/W
L
OEL
OER
CE0R
CE1R
CE0L
CE1L
1
0
1
0
0/1
0/1
1
0
0
1
FT/PIPE
L
0/1
0/1
FT/PIPE
R
I/O0R - I/O8R
I/O0L - I/O8L
I/O
Control
I/O
Control
(1)
(1)
A13L
A13R
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A
0R
CLK
A
0L
R
R
CLK
L
ADS
CNTEN
CNTRST
ADS
CNTEN
CNTRST
L
R
L
L
R
5655 drw 01
NOTE:
1. A13 is a NC for IDT70V9159.
FEBRUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC-5655/5
NOTE:
.
A13
s a
NC
or
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
T70V9159
Description:
Withaninputdataregister,theIDT70V9169/59 hasbeenoptimized
The IDT70V9169/59 is a high-speed 16/8K x 9 bit synchronous
forapplicationshavingunidirectionalorbidirectionaldataflowinbursts.An
automaticpowerdownfeature, controlledbyCE0 andCE1, permitsthe
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices
typicallyoperateononly450mWofpower.
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systemstobedesignedwithveryshortcycletimes.
Pin Configurations(1,2,3,4)
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
NC
NC
NC
NC
75
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
3
A
7R
A
A
A
7L
8L
9L
4
A
A
8R
9R
5
6
A10R
A
A
A
10L
11L
7
A
A
A
11R
8
12R
13R
12L
(1)
(1)
9
A
13L
70V9169/59PF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(5)
NC
NC
NC
NC
NC
NC
Vss
NC
NC
NC
NC
PN100
100-Pin TQFP
V
DD
(6)
Top View
NC
NC
NC
NC
CE0L
CE0R
CE1R
CNTRST
CE1L
R
CNTRST
R/W
OE
FT/PIPE
L
R/W
OE
R
L
R
L
L
FT/PIPE
Vss
NC
R
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
.
5655 drw 02
NOTES:
1. A13 is a NC for IDT70V9159.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.422
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(cont'd)(1,2,3,4)
70V9169/59PF
BF100(5)
100-PinfpBGA
Top View(6)
A5
A6
A7
A8
A9
A10
A1
A2
A3
A4
V
SS
NC
A
6R
4R
3R
A
9R
A
12R
NC
V
SS
R/W
R
V
SS
NC
B1
B2
B3
B5
B6
B7
B8
B4
B9
B10
A
A
5R
A
8R
A10R
NC
NC
NC
OER
NC I/O6R
C3
C5
C6
C7
C9
C1
C2
C4
C8
C10
NC
NC CE0R CE1R
I/O7R
A
NC
A7R
PL/FT
R
I/O3R
D1
E1
D2
D6
D7
D8
D9
D10
D3
D4
D5
(
1)
CLK
R
I/O5R
A
0R
A
1R
A
2R
A
11R
A
13R CNTRST
R
I/O8R
I/O1R
E3
E4
E5
E6
E7
E8
E9
E10
E2
CNTEN
R
A1L
ADS
L
V
SS I/O4R I/O2R I/O0R
V
DD
VSS ADS
R
F5
F6
F7
F8
F9
F10
F1
F2
F3
F4
VDD
V
DD
VSS
I/O2L I/O1L I/O0L
V
SS CLK
L
A0L
A3L
G5
G6
G9
G4
G7
G8
G10
G1
G2
G3
NC R/W
L
VSS
A
12L
NC I/O4L
I/O3L
CNTEN
L
NC
A
5L
H5
H6
H7
H9
H3
H4
H8
H10
H1
H2
(
1)
NC CE1L NC
I/O6L
A9L
A13L
I/O7L
I/O5L
A
2L
A4L
J7
J5
J6
J8
J9
J10
J1
J4
J2
J3
OE
L
VSS
NC
NC
V
SS I/O8L
NC
A
7L
A
10L
11L
NC
K5
K6
K7
K8
CNTRST
K9 K10
K2
K4
K3
K1
V
DD
L
PL/FTL NC
A8L
NC
VDD
CE0L
A6L
A
5655 drw 03
NOTES:
1. A13 is a NC for IDT70V9159.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
0L - A13L
A
0R - A13R
I/O0R - I/O8R
CLK
ADS
CNTEN
CNTRST
FT/PIPE
I/O0L - I/O8L
CLK
ADS
CNTEN
CNTRST
Data Input/Output
Clock
L
R
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (3.3V)
Ground (0V)
L
R
L
R
L
R
FT/PIPE
L
R
V
V
DD
SS
5655 tbl 01
NOTE:
1. A13 is a NC for IDT70V9159.
Truth Table I—Read/Write and Enable Control(1,2,3)
CLK
↑
CE
X
1
R/W
X
I/O0-8
High-Z
High-Z
DATAIN
DATAOUT
High-Z
Mode
Deselected—Power Down
OE
X
CE0
H
X
L
X
L
X
Deselected—Power Down
↑
X
H
H
H
L
Write
↑
L
L
H
Read
↑
H
X
L
X
Outputs Disabled
5655 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.442
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Previous Internal
External
Address
Internal
Address
Address
Used
MODE
CLK
↑
I/O(3)
DI/O (n) External Address Used
ADS CNTEN CNTRST
An
X
X
An
An
L(4)
H
X
H
H
An + 1
An + 1
L(5)
H
D
I/O(n+1) Counter Enabled—Internal Address generation
↑
X
An + 1
X
↑
H
H
D
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
A
0
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
↑
5655 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage
Symbol
Parameter
Supply Voltage
Ground
Min.
Typ.
Max.
Unit
V
Ambient
Grade
Commercial
Temperature(1)
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
V
V
DD
SS
3.0
3.3
3.6
3.3V
3.3V
+
+
0.3V
0
0
0
V
Industrial
0V
0.3V
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3V(2)
0.8
V
5655 tbl 04
-0.3(1)
V
____
V
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
5655 tbl 05
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD+0.3V.
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHZ)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
CIN
V
9
pF
(3)
OUT
C
V
10
pF
T
BIAS
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
5655 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
TSTG
Storage
Temperature
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
IOUT
DC Output Current
mA
3. COUT also references CI/O.
5655 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
6.42
5
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range ( VDD= 3.3V ± 0.3V)
70V9169/59L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
Max.
Unit
µA
µA
V
___
___
___
|
V
DD = 3.6V, VIN = 0V t
CE = VIH or CE = VIL, VOUT = 0V t
OL = +4mA
OH = -4mA
o
V
DD
5
5
|
1
o VDD
V
V
OL
OH
I
0.4
___
Output High Voltage
I
2.4
V
5655 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)
70V9169/59L6
Com'l Only
70V9169/59L7
Com'l & Ind
70V9169/59L9
Com'l Only
Symbol
Parameter
Test Condition
and CE = VIL
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
280
330
70
Typ.(4)
Max.
Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
L
L
L
L
L
L
175
330
155
155
40
135
230
CE
L
R
,
Outputs Disabled,
f = fMAX
(1)
____
____
____
____
IND
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
COM'L
IND
50
80
30
60
CE
L = CER = VIH
(1)
____
____
____
____
40
80
f = fMAX
ISB2
Standby
CE"A" = VIL and
COM'L
IND
115
185
105
170
95
155
(5)
Current (One
Port - TTL
Level Inputs)
CE"B" = VIH
Active Port Outputs
Disabled, f=fMAX
____
____
____
____
105
0.5
0.5
95
180
3.0
3.0
160
(1)
ISB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL
CE >VDD - 0.2V,
and
mA
mA
COM'L
IND
L
L
0.5
3.0
0.5
3.0
R
V
V
IN > VDD- 0.2V or
IN < 0.2V, f = 0(2)
____
____
____
____
ISB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
COM'L
IND
L
L
105
175
85
145
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
V
IN > VDD- 0.2V or
IN < 0.2V, Active Port,
____
____
____
____
95
175
V
Outputs Disabled, f = fMAX
(1)
5655 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD =3.3V,TA =25°C forTyp,andarenotproductiontested.ICC DC(f=0)=90mA(Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.462
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
2ns Max.
1.5V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
Figures 1, 2 & 3
5655 tbl 10
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
30pF
435Ω
5pF*
435Ω
5655 drw 03
5655 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
Figure 1. AC Output Test load.
*Including scope and jig.
8
7
6
5
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
,
4
3
2
1
2
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
5655 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
7
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) ( VDD= 3.3V ± 0.3V, TA = 0°C to +70°C)
70V9169/59L6
Com'l Only
70V9169/59L7
Com'l & Ind
70V9169/59L9
Com'l Only
Symbol
Parameter
Min.
19
Max.
Min.
22
Max.
Min.
25
15
12
12
6
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CYC1
CYC2
CH1
CL 1
CH2
CL 2
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
10
12
t
6.5
6.5
4
7.5
7.5
5
t
t
t
4
5
6
____
____
____
tR
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
t
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HA D
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Address Setup Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Address Hold Time
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
3.5
0
t
t
3.5
0
t
t
3.5
0
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
3.5
0
t
t
3.5
0
t
ADS Hold Time
t
3.5
0
CNTEN Setup Time
t
CNTEN Hold Time
t
3.5
CNTRST Setup Time
t
0
0
1
CNTRST Hold Time
____
____
____
t
Output Enable to Data Valid
6.5
7.5
9
(1)
____
____
____
t
Output Enable to Output Low-Z
2
2
2
t
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
1
7
1
7
1
7
____
____
____
t
15
18
20
____
____
____
t
6.5
7.5
9
____
____
____
t
2
2
2
2
2
2
2
2
2
(1)
t
Clock High to Output High-Z
9
9
9
(1)
____
____
____
t
Clock High to Output Low-Z
Port-to-Port Delay
____
____
____
____
____
____
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
24
9
28
10
35
15
ns
tCCS
ns
5655 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply
when FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.
6.482
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(3,6)
tCYC1
tCH1
tCL1
CLK
CE
0
tSC
tHC
tSC
tHC
CE1
R/W
tHW
tSW
tSA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
tCKLZ
tDC
(1)
tOHZ
tOLZ
OE(2)
tOE
5655 drw 07
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,6)
tCYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
tSC
t
HC
(4)
CE1
R/W
tHW
tSW
tSA
tHA
ADDRESS(5)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (6)
DATAOUT
Qn + 1
(1)
tCKLZ
(1)
(1)
t
OHZ
tOLZ
OE(2)
tOE
5655 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. "X' here denotes Left or Right port. The diagram is with respect to that port.
6.42
9
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
CKHZ
tCD2
tCD2
t
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tDC
tCKLZ
t
DC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
(3)
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
5655 drw 09
Timing Waveform with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
tHA
NO
MATCH
MATCH
SD HD
VALID
t
t
(6)
tCCS
tCD1
R/W "B"
tHW
t
SW
tHA
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(6)
t
CD1
tCWDD
VALID
VALID
tDC
t
DC
5655 drw 10
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V916/59L for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.1402
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
t
SC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD
t
HD
DATAIN
Dn + 2
(1)
tCKLZ
(1)
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
5655 drw 11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
(1)
CKLZ
tCD2
tCD2
t
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
5655 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
11
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
t
SW
t
HW
HA
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
t
SA
t
tSD
tHD
DATAIN
Dn + 2
t
CD1
t
CD1
t
CD1
tCD1
(2)
Qn
Qn + 3
Qn + 1
DATAOUT
(1)
CKLZ
(1)
tDC
tDC
t
t
CKHZ
NOP(5)
READ
READ
WRITE
5655 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE
0
1
tSC
tHC
CE
t
SW tHW
R/W
tSW tHW
(4)
An + 2
An + 4
An + 5
An + 3
Dn + 3
An
tHA
An +1
ADDRESS
tSA
t
SD tHD
DATAIN
Dn + 2
tOE
tDC
tCD1
tCD1
tCD1
(2)
Qn
Qn + 4
DATAOUT
(1)
CKLZ
(1)
t
tOHZ
tDC
OE
READ
WRITE
READ
5655 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1422
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD tHAD
ADS
t
SAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5655 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn
Qn + 4
Qn + 1
Qn + 2
DATAOUT
tDC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
5655 drw 16
NOTES:
1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.42
13
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
tSAD tHAD
ADS
CNTEN
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
5655 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS(4)
An + 2
An
An + 1
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
t
SW tHW
R/W
ADS
CNTEN
tSRST
tHRST
CNTRST
t
SD
t
HD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
.
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS n
READ
ADDRESS n+1
READ
ADDRESS 1
NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
CE0 = VIL; CE1 = VIH.
5655 drw 18
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ Address is written to during this cycle.
6.1442
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
The IDT70V9169/59 provides a true synchronous Dual-Port Static
TheIDT70V9169/59 featuresdualchipenables(refertoTruthTable
RAMinterface.Registeredinputsprovideminimalset-upandholdtimes I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
onaddress, data, andallcriticalcontrolinputs. Allinternalregistersare mentsforexternallogic.Figure4illustrateshowtocontrolthevariouschip
clocked on the rising edge of the clock signal, however, the self-timed enables in order to expand two devices in depth.
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock
signal.
The IDT70V9169/59 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Sincethebanksareallocated
An asynchronous output enable is provided to ease asynchronous atthediscretionoftheuser,theexternalcontrollercanbesetuptodrive
bus interfacing. Counter enable inputs are also provided to stall the theinputsignalsforthevariousdevicesasrequiredtoallowfor36-bitor
operationoftheaddresscountersforfastinterleavedmemoryapplications. widerapplications.
CE0 = VIL and CE1 = VIH for one clock cycle will power down the
internalcircuitrytoreducestaticpowerconsumption.Multiplechipenables
alloweasierbankingofmultipleIDT70V9169/59'sfordepthexpansion
configurations.WhenthePipelinedoutputmodeisenabled,twocyclesare
required with CE0 = VIL and CE1 = VIH to re-activate the outputs.
(1)
A14/A13
IDT70V9169/59
Control Inputs
IDT70V9169/59
Control Inputs
CE
0
CE
0
CE1
CE1
VDD
VDD
IDT70V9169/59
Control Inputs
IDT70V9169/59
Control Inputs
CE
1
CE
1
CE0
CE0
CNTRST
CLK
ADS
CNTEN
5655 drw 19
R/W
OE
Figure 4. Depth and Width Expansion with IDT70V9169/59L
NOTE:
1. A14 is for IDT70V9169, A13 is for IDT70V9159.
6.42
15
IDT70V9169/59L
High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
99
A
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I(1)
G(2)
Green
PF
BF
100-pin TQFP (PN100)
100-pin fpBGA (BF100)
Commercial Only
Commercial & Industrial
Commercial Only
6
7
9
Speed in nanoseconds
Low Power
L
144K (16K x 9-Bit) Synchronous Dual-Port RAM
72K (8K x 9-Bit) Synchronous Dual-Port RAM
70V9169
70V9159
5655 drw 20
NOTES:
1. ContactyourlocalsalesofficeforIndustrialtemprangeforotherspeeds,packagesandpowers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowersseeyoursalesoffice.
LEADFINISH(SnPb)partsareinEOLprocess. ProductDiscontinuationNotice-PDN#SP-17-02
IDT Clock Solution for IDT70V9169/59 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
IDT
PLL
Clock Device
IDT
IDT Dual-Port
Part Number
Input Duty
Cycle
Non-PLL Clock
Device
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
I/O
Requirement
FCT3805
FCT3805D/E
FCT3807
IDT2305
IDT2308
IDT2309
70V9169/59
3.3
LVTTL
9pF
40%
100
150ps
FCT3807D/E
5638 tbl 12
Datasheet Document History
07/08/02:
08/15/03:
InitialPublicRelease
RemovedPreliminarystatus
Page 16 Added IDT Clock Solution Table
01/29/09:
06/18/15:
Page 16 Removed "IDT" from orderable part number
Page 2 Removed IDT with reference to fabrication
Page 2 Removed date from 100-pin TQFP configuration
Page 2 & 16 The package code PN100-1 changed to PN100 to match standard package codes
Page3Removeddatefrom100-pinfpBGAconfiguration
Page6CorrectedtypointheTypicalOutputDeratingdrawing
Page16 AddedTapeandReelandGreenindicatorsandupdatedthefootnotestotheOrderingInformation
ProductDiscontinuationNotice-PDN#SP-17-02
02/21/18:
Last time buy expires June 15, 2018
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.1462
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