IDT70V9269L [IDT]
HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM; 高速3.3V 16K ×16的同步流水式双口静态RAM
| 型号： | IDT70V9269L |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| 文件： | 总15页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V 16K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9269S/L
Features:
True Dual-Ported memory cells which allow simultaneous
◆
additional logic
Full synchronous operation on both ports
◆
access of the same memory location
High-speed clock to data access
◆
–
4ns setup to clock and 1ns hold on all Control,
data, and address inputs
– Commercial:9/12/15ns (max.)
Low-power operation
◆
– Data input, address, and control registers
Fast 9ns clock to data out in the Pipelined output mode
–
– IDT70V9269S
– Self-timedwriteallowsfastcycletime
Active:429mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V9269L
Active:429mW(typ.)
Standby: 1.32mW (typ.)
Flow-through or Pipelined output mode on either port via
– 15ns cycle time, 66MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
◆
◆
the FT/PIPE pin
Counter enable and reset features
◆
◆
Available in a 128-pin Thin Quad Flatpack (TQFP) package
◆
Dual chip enables allow for depth expansion without
FunctionalBlockDiagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LBL
OEL
LBR
OER
0a 1a
0b 1b
1b 0b
1a 0a
a
0/1
0/1
FT/PIPEL
b
a
b
FT/PIPER
I/O8L-I/O15L
I/O8R-I/O15R
I/O0R-I/O7R
I/O
Control
I/O
Control
I/O0L-I/O7L
A13R
A13L
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A0R
CLKR
ADSR
A0L
CLKL
ADSL
CNTENR
CNTENL
CNTRSTL
CNTRSTR
3752 drw 01
JANUARY 2001
1
DSC 3752/6
©2000IntegratedDeviceTechnology,Inc.
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70V9269isahigh-speed16Kx16bitsynchronousDual-Port
Withaninputdataregister,theIDT70V9269hasbeenoptimizedfor
RAM. The memory array utilizes Dual-Port memory cells to allow applicationshavingunidirectionalorbidirectionaldataflowinbursts.An
simultaneousaccessofanyaddressfrombothports.Registersoncontrol, automaticpowerdownfeature,controlledbyCE0andCE1, permitsthe
data,andaddressin-putsprovideminimalsetupandholdtimes.Thetiming on-chip circuitry of each port to enter a very low standby power mode.
latitudeprovidedbythisapproachallowssystemstobedesignedwithvery Fabricated using IDT’s CMOS high-performance technology, these
shortcycletimes.
devices typicallyoperate ononly429mWofpower.
PinConfiguration(1,2,3)
I/O10R
I/O9R
GND
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
N/C
N/C
N/C
N/C
A9R
A8R
N/C
I/O8R
N/C
N/C
A7R
A6R
A5R
A4R
A3R
A2R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
9
10
92
91
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GND
I/O3R
VCC
I/O2R
I/O1R
I/O0R
GND
A1R
A0R
NC
CNTENR
CLKR
70V9269PRF
PK-128(4)
R
ADS
GND
VCC
VCC
I/O0L
I/O1L
GND
I/O2L
I/O3L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
ADSL
CLKL
128-Pin TQFP
Top View(5)
CNTENL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
27
28
29
30
31
32
33
34
35
36
37
38
N/C
N/C
I/O8L
N/C
A8L
A9L
N/C
N/C
N/C
N/C
VCC
I/O9L
I/O10L
3752 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables
CE0L, CE1L
CE0R, CE1R
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
A0L - A13L
I/O0L - I/O15L
CLKL
A0R - A13R
I/O0R - I/O15R
CLKR
Data Input/Output
Clock
Upper Byte Select
Lower Byte Select
Address Strobe Enable
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power
UBL
LBL
UBR
LBR
ADSL
ADSR
CNTEN
CNTEN
L
R
CNTRSTL
CNTRSTR
FT/PIPEL
FT/PIPER
VCC
GND
Ground
3752 tbl 01
Truth Table IRead/Write and Enable Control(1,2,3)
Upper Byte
I/O8-15
Lower Byte
I/O0-7
MODE
CLK
↑
CE1
X
L
R/W
X
X
X
L
OE
X
X
X
X
X
X
L
CE0
H
X
L
UB
X
X
H
L
LB
X
X
H
H
L
High-Z
High-Z
High-Z
DATAIN
High-Z
DATAIN
High-Z
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
↑
H
H
H
H
H
H
H
H
↑
L
↑
L
H
L
L
↑
L
L
L
↑
OUT
DATA
L
L
H
L
H
H
H
X
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
L
H
L
High-Z
DATAOUT
High-Z
↑
L
L
L
↑
H
L
L
L
Outputs Disabled
↑
3752 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.42
3
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2)
Previous
Address
Addr
Used
MODE
(3)
Address
CLK
I/O
ADS
CNTEN CNTRST
X
An
An
X
X
X
0
An
X
X
X
H
L
H
H
H
DI/O(0)
DI/O(n)
DI/O(p)
Counter Reset to Address 0
↑
↑
↑
↑
(4)
L
External Address Loaded into Counter
External Address Blocked—Counter disabled (Ap reused)
Ap
Ap
Ap
H
H
(5)
Ap + 1
L
DI/O(p+1) Counter Enabled—Internal Address generation
3752 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
RecommendDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage(1,2)
Symbol
Parameter
Min.
Typ.
Max.
3.6
0
Unit
V
Ambient
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
Vcc
VCC
Supply Voltage
3.0
3.3
3.3V+ 0.3V
3.3V+ 0.3V
GND Ground
0
0
V
0V
(2)
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
VCC+0.3V
0.8
V
3752 tbl 04
NOTE:
-0.3(1)
V
____
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
3752 tbl 05
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VCC + 0.3V.
AbsoluteMaximumRatings(1)
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
Symbol
Rating
Commercial
& Industrial
Unit
CIN
VIN = 3dV
9
pF
(2)
VTE RM
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
(3)
COUT
VOUT = 3dV
10
pF
3752 tbl 07
TBIAS
TSTG
Te m p e rature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
Storage
Te m p e rature
IOUT
DC Output Current
mA
3. COUT also references CI/O.
3752 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 0.3V.
6.42
4
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V9269S
70V9269L
Symbol
Parameter
Test Conditions
VCC = 3.6V, VIN = 0V to VCC
Min.
Max.
Min.
Max.
Unit
(1 )
___
___
___
___
Input Leakage Current
Output Leakage Current
Output Low Voltage
|ILI|
10
10
5
5
µA
µA
V
___
___
|ILO|
VOL
VOH
CE = VIH or CE1 = VIL, VOUT = 0V to VCC
IOL = +4mA
IOH = -4mA
0.4
0.4
___
___
Output High Voltage
2.4
2.4
V
3752 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperture and Supply Voltage Range(3,6,7) (VCC = 3.3V ± 0.3V)
70V9269X9
Com'l Only
70V9269X12
Com'l Only
70V9269X15
Com'l Only
Symbol
Parameter
Test Condition
CEL and CER= V ,
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
I
CC
Dynamic
Operating
Current (Both
Ports Active)
S
L
180
180
260
225
150
150
240
205
130
130
220
185
mA
IL
Outputs Disabled,
(1)
f = f
MAX
____
____
____
____
____
____
____
____
____
____
____
____
IND
S
L
I
Standby
COM'L
IND
S
L
50
50
75
65
40
40
65
50
30
30
55
35
mA
mA
SB1
CE = CE = V
IH
L
R
Current (Both
Ports - TTL
Level Inputs)
(1)
f = f
MAX
____
____
____
____
____
____
____
____
____
____
____
____
S
L
I
SB2
Standby
COM'L
IND
S
L
110
110
170
150
100
100
160
140
90
90
150
130
CE = V and
"A"
IL
IH
(5)
Current (One
Port - TTL
Level Inputs)
CE = V
"B"
Active Port Outputs Disabled,
____
____
____
____
____
____
____
____
____
____
____
____
(1)
S
L
f=f
MAX
I
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CE and
COM'L
IND
S
L
1.0
0.4
5
3
1.0
0.4
5
3
1.0
0.4
5
3
mA
mA
SB3
L
CE > V - 0.2V,
R
CC
V > V - 0.2V or
IN
CC
V < 0.2V, f = 0(2)
IN
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
COM'L
IND
S
L
100
100
160
140
90
90
150
130
80
80
140
120
CE < 0.2V and
"A"
(5)
CE > V - 0.2V
"B"
CC
V > V - 0.2V or
IN
CC
____
____
____
____
____
____
____
____
____
____
____
____
S
L
V < 0.2V, Active Port,
IN
(1)
Outputs Disable d, f = f
MAX
3752 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
5
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns
1.5V
1.5V
Figures 1, 2, and 3
3752 tbl 10
3.3V
3.3V
590Ω
590Ω
DATAOUT
OUT
DATA
30pF
435Ω
5pF*
435Ω
3752 drw 03
3752 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 1. AC Output Test load.
8
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
7
6
5
4
3
tCD1,
2
tCD
(Typical, ns)
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
,
-1
3752 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
6
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Tempurature Range
(Read and Write Cycle Timing)(3,4,5) (VCC = 3.3V ± 0.3v, TA = 0°C to +70°C)
70V9269X9
Com'l Only
70V9269X12
Com'l Only
70V9269X15
Com'l Only
Symbol
tCYC1
Parameter
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)(2)
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
25
15
12
12
6
30
20
12
12
8
35
25
12
12
10
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
(2)
Clock High Time (Flow-Through)
(2)
Clock Low Time (Flow-Through)
(2)
Clock High Time (Pipelined)
(2)
Clock Low Time (Pipelined)
6
8
10
____
____
____
Clock Rise Time
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
tSA
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
tSC
tHC
tSW
tHW
tSD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
Output Enable to Data Valid
1
1
1
____
____
____
12
12
15
(1)
____
____
____
tOLZ
tOHZ
tCD1
tCD2
tDC
Output Enable to Output Low-Z
2
2
2
(1)
Output Enable to Output High-Z
1
7
1
7
1
7
(2)
____
____
____
Clock to Data Valid (Flow-Through)
20
25
30
(2)
____
____
____
Clock to Data Valid (Pipelined)
9
12
15
____
____
____
Data Output Hold After Clock High
2
2
2
2
2
2
2
2
2
(1)
tCKHZ
tCKLZ
Clock High to Output High-Z
9
9
9
(1)
____
____
____
Clock High to Output Low-Z
Port-to-Port Delay
tCWDD Write Port Clock High to Read Data Delay
tCCS Clock-to-Clock Setup Time
____
____
____
____
____
____
35
15
40
15
50
20
ns
ns
70V9269 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device
characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPEX.
4. 'X' in part number indicates power rating (S or L).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
7
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-through Output on Either Port (FT/PIPEX = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
(4)
tHC
tHB
tSC tHC
CE1
tSB
tHB
UB, LB
R/W
tSB
tHW
tHA
tSW
tSA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCKHZ
tCD1
Qn
Qn + 1
Qn + 2
(1)
(1)
tDC
tCKLZ
(1)
tOHZ
tOLZ
tOE
OE (2)
3752 drw 06
Timing Waveform of Read Cycle for Pipelined Operation on Either Port
(FT/PIPEX = VIH)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
(4)
tHC
tHB
tHC
tHB
tSC
tSB
CE1
tSB
(6)
UB, LB
R/W
tHW
tHA
tSW
tSA
ADDRESS(5)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (6)
DATAOUT
Qn + 1
(1)
(1)
tCKLZ
(1)
tOHZ
tOLZ
tOE
OE(2)
NOTES:
3752 drw 07
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6.42
8
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-device Pipelined Read(1,2)
tCYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
tSA tHA
A6
A5
A4
A3
A2
A0
A1
tSC tHC
tSC tHC
(3)
tCD2
tCD2
tCKHZ
tDC
tCD2
(3)
Q0
Q3
A5
Q1
A3
DATAOUT(B1)
(3)
tDC
tCKHZ
tCKLZ
tSA tHA
A0
A6
A4
A2
A1
ADDRESS(B2)
tSC tHC
CE0(B2)
tSC tHC
(3)
tCD2
(3)
tCD2
(3)
tCKHZ
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
3752 drw 08
Timing Waveform of Left Port Write to Flow-through Right Port Read(4,5)
CLK L
tSW tHW
R/W L
tSA tHA
NO
ADDRESS L
DATAIN L
CLK R
MATCH
MATCH
tSD tHD
VALID
(6)
tCCS
tCD1
R/W R
tHW
tHA
tSW
tSA
NO
MATCH
ADDRESS R
DATAOUT R
MATCH
(6)
tCD1
tCWDD
VALID
VALID
tDC
tDC
3752 drw 09
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V9269 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.42
9
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
UB, LB
R/W
tSB
tHB
tSW tHW
tSW tHW
(4)
An + 4
An + 3
An
tSA tHA
An +1
An + 2
An + 2
tSD
ADDRESS
tHD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
3752 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB tHB
UB, LB
tSW tHW
W
R/
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
tSA tHA
tSD tHD
DATAIN
Dn + 2
(1)
tCD2
tCD2
tCKLZ
(2)
Qn
Qn + 4
DATAOUT
(1)
tOHZ
OE
READ
WRITE
READ
3752 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
10
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB tHB
UB, LB
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
tSA tHA
An + 3
An +1
An + 2
An + 2
tSD tHD
Dn + 2
ADDRESS
DATAIN
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
(1)
tDC
tCKLZ
tDC
tCKHZ
NOP(5)
READ
WRITE
3752 drw 12
TimingWaveformof Flow-throughRead-to-Write-to-Read(OEControlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB tHB
UB LB
,
tSW tHW
tSW tHW
W
R/
(4)
An + 5
An
tSA tHA
An + 4
An +1
An + 2
An + 3
Dn + 3
ADDRESS
DATAIN
tSD tHD
Dn + 2
tOE
tCD1
tDC
tCD1
tCD1
(2)
Qn
Qn + 4
tDC
DATAOUT
(1)
tCKLZ
(1)
tOHZ
OE
READ
WRITE
READ
3752 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or HIgh-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
11
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD2
Qn + 2(2)
Qx - 1(2)
Qn + 3
Qn + 1
Qn
Qx
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3752 drw 14
Timing Waveform of Flow-through Read with Address Counter Advance(1)
tCYC1
tCH1
tCL1
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
Qn + 3(2)
Qn + 4
Qx(2)
Qn
Qn + 1
Qn + 2
DATAOUT
tDC
READ
WITH
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
COUNTER
3752 drw 15
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address, i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.42
12
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
tSAD tHAD
ADS
CNTEN(7)
tSD tHD
Dn
Dn + 4
Dn + 1
Dn + 3
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
3752 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
(4)
An + 2
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
tSW tHW
R/W
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
3752 drw 17
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An + 1’. The transition show indicates the time required for the counter to advance. The ‘An +1’ Address is
written to during this cycle.
6.42
13
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
TheIDT70V9269providesatruesynchronousDual-PortStaticRAM
Depth and Width Expansion
TheIDT70V9269featuresdualchipenables(refertoTruthTable1)
interface. Registered inputs provide minimal set-up and hold times on inordertofacilitaterapidandsimpledepthexpansionwithnorequirements
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked for external logic. Figure 4 illustrates how to control the various chip
ontherisingedgeoftheclocksignal,however,theself-timedinternalwrite enables in order to expand two devices in depth.
pulseisindependentoftheLOWtoHIGHtransitionoftheclocksignal.
TheIDT70V9269canalsobeusedinapplicationsrequiringexpanded
An asynchronous output enable is provided to ease asynchronous width, as indicated in Figure 4. Since the banks are allocated at the
bus interfacing. Counter enable inputs are also provided to stall the discretionoftheuser,theexternalcontrollercanbesetuptodrivetheinput
operationoftheaddresscountersforfastinterleavedmemoryapplications. signals for the various devices as required to allow for 32-bit or wider
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown applications.
theinternalcircuitrytoreducestaticpowerconsumption.MultipleChip
EnablesalloweasierbankingofmultipleIDT70V9269'sfordepthexpan-
sionconfigurations.WhenthePipelinedoutputmodeisenabled,twocycles
are requiredwithCE0 LOWandCE1 HIGHtore-activate the outputs.
A14
IDT70V9269
IDT70V9269
CE0
CE0
CE1
CE1
VCC
VCC
Control Inputs
Control Inputs
IDT70V9269
IDT70V9269
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
R/W
3752 drw 18
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT70V9269
6.42
14
IDT70V9269S/L
High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I (1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PRF
128-pin TQFP (PK128-1)
9
12
15
Commercial Only
Speed in nanoseconds
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
70V9269 256K (16K x 16-Bit) Synchronous Dual-Port RAM
3752 drw 19
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
1/12/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Page14AddedDepthandWidthExpansionsection
Page 4 Deleted note 6 for Table II
FixedPinConfiguration
6/15/99:
8/20/99:
4/4/00:
Replaced IDT logo
AddedFT/PIPEtoleftport
Changed±200mVto0mVinnotes
Page 4 ChangedinformationinTruthTableII
Increasedstoragetemperatureparameters
ClarifiedTAparameter
1/17/01:
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
RemovedPreliminarystatus
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800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
15
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