IDT70V927S30PRFG8 [IDT]
Dual-Port SRAM, 32KX16, 30ns, CMOS, PQFP128, TQFP-128;
| 型号： | IDT70V927S30PRFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 32KX16, 30ns, CMOS, PQFP128, TQFP-128 静态存储器 |
| 文件： | 总14页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V 32K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70V927S/L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
Commercial: 25/30ns
Full synchronous operation on both ports
4ns setup to clock and 1ns hold on all control, data, and
address inputs
◆
◆
Data input, address, and control registers
Fast 25ns clock to data out
Low-power operation
IDT70V927S
Self-timed write allows fast cycle time
30ns cycle time, 33MHz operation
Active: 550mW (typ.)
Standby: 3.3mW (typ.)
IDT70V927L
Active: 550mW (typ.)
Standby: 660mW (typ.)
Flow-Through output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
◆
◆
◆
◆
◆
◆
Available in a 128 pin Thin Quad Flatpack
Functional Block Diagram
WR
R/
UBR
R/WL
UBL
CE0L
CE1L
CE0R
CE1R
LBL
LBR
OEL
OER
I/O8R-I/O15R
I/O0R-I/O7R
A14R
I/O8L-I/O15L
I/O0L-I/O7L
I/O
Control
I/O
Control
A14L
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A0R
A0L
CLKR
ADSR
CNTENR
CLKL
ADSL
CNTENL
CNTRSTL
CNTRSTR
3749 drw 01
SEPTEMBER 1999
1
DSC 3749/4
©1999IntegratedDeviceTechnology,Inc.
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Description
With an input data register, the IDT70V927 has been optimized for
The IDT70V927 is a high-speed 32K x 16 bit synchronous Dual-
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled byCE0and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDTs CMOS high-performance technology,
these devices typically operate on only 550mW of power.
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems to
be designed with very short cycle times.
Pin configurations(1,2,3)
I/O10R
I/O9R
GND
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
N/C
N/C
N/C
N/C
A9R
A8R
N/C
I/O8R
N/C
N/C
A7R
A6R
A5R
A4R
A3R
A2R
I/O7R
VCC
I/O6R
I/O5R
I/O4R
9
10
92
91
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GND
I/O3R
VCC
I/O2R
I/O1R
I/O0R
GND
VCC
I/O0L
I/O1L
GND
I/O2L
I/O3L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
A1R
A0R
N/C
CNTENR
CLKR
70V927PRF
PK-128(4)
ADSR
GND
VCC
ADSL
CLKL
128-Pin TQFP
Top View(5)
CNTEN
L
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
27
28
29
30
31
32
33
34
35
36
37
38
N/C
N/C
I/O8L
N/C
A8L
A9L
N/C
N/C
N/C
N/C
VCC
I/O9L
I/O10L
3749 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
, CE
WR
Names
Chip Enables
CE0L
, CE
1L
CE0R
1R
WL
R/
R/
Read/Write Enable
Output Enable
Address
OEL
OER
0L
14L
0R
14R
- A
A
- A
A
0L
15L
0R
15R
I/O - I/O
I/O - I/O
Data Input/Output
Clock
L
R
CLK
CLK
UBL
UBR
Upper Byte Select
Lower Byte Select
Address Strobe
Counter Enable
Counter Reset
Power
LBL
LBR
ADSL
ADSR
CNTENL
CNTRSTL
CNTENR
CNTRSTR
VCC
GND
Ground
3749 tbl 01
Truth Table IRead/Write and Enable Control(1,2,3)
Upper Byte
I/O8-15
Lower Byte
I/O0-7
CLK
↑
CE1
X
R/
W
Mode
DeselectedPower Down
OE
X
X
X
X
X
X
L
CE
H
X
L
0
UB
X
X
H
L
LB
X
X
H
H
L
X
High-Z
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DIN
L
X
X
L
DeselectedPower Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
↑
H
H
H
H
H
H
H
H
↑
L
↑
L
H
L
L
High-Z
DIN
↑
L
L
L
DIN
↑
L
L
H
L
H
H
H
X
DOUT
High-Z
DOUT
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
L
H
L
High-Z
DOUT
↑
L
L
L
DOUT
↑
H
X
L
L
L
High-Z
High-Z
Outputs Disabled
3749 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.42
3
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2)
Previous
Address
Address
CLK
↑
I/O
Mode
Counter Reset to Address 0
ADS
H
CNTEN
CNTRST
X
An
X
X
X
H
L
DI/O(0)
DI/O(n)
DI/O(n)
DI/O(n+1)
L(3)
H
H
H
H
H
External Address Utilized
↑
An
An
H
External Address BlockedCounter Disabled
↑
X
H
L(4)
Counter EnableInternal Address Generation
↑
3749 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. ADS is independent of all other signals including CE0, CE1, UB and LB.
4. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating
Recommended DC Operating
TemperatureandSupplyVoltage(1,2) Conditions
Symbol
Parameter
Supply Voltage
Ground
Min.
3.0
Typ.
Max.
Unit
V
Grade
Ambient
GND
Vcc
Temperature
VCC
3.3
3.6
Commercial
Industrial
0OC to +70OC
0V
0V
3.3V 0.3V
+
GND
VIH
0
0
0
VCC + 0.3V
0.8
V
-40OC to +85OC
3.3V + 0.3V
____
Input High Voltage
Input Low Voltage
2.2
V
3749 tbl 04
-0.3(2)
V
____
NOTES:
VIL
1. This is the parameter TA.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
3749 tbl 05
NOTES:
1. VTERM must not exceed Vcc + 0.3V.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
Max. Unit
CIN
VIN = 3dV
9
pF
(2)
VTE RM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
(3 )
COUT
VOUT = 3dV
10
pF
3749 tbl 07
NOTES:
Temperature
Under Bias
-55 to +125
-55 to +125
50
oC
oC
TBIAS
TSTG
IOUT
1. These parameters are determined by device characterization, but are not produc-
tion tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
Storage
Temperature
DC Output
Current
mA
37 49 tb l 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
6.42
4
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V927S
70V927L
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 3.3V, VIN = 0V to VCC
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
___
___
5
5
___
___
|ILO|
0
IH
1
IL OUT
CC
10
CE = V or CE = V , V = 0V to V
VOL
IOL = +4mA
IOH = -4mA
0.4
0.4
___
___
VOH
Output High Voltage
2.4
2.4
V
3749 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6,7) (VCC = 3.3V ± 0.3V)
70V927X25
Com'l Only
70V927X30
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
120
120
220
185
110
110
210
175
mA
CEL and CER= VIL
Outputs Open
f = fMAX
(1)
____
____
____
____
____
____
____
____
IND
S
L
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
30
30
50
40
30
30
50
40
mA
mA
CEL = CER = VIH
(1)
f = fMAX
____
____
____
____
____
____
____
____
S
L
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
90
90
130
115
80
80
120
105
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs
____
____
____
____
____
____
____
____
(1)
S
L
Open, f=fMAX
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
IND
S
L
1.0
0.2
5
3
1.0
0.2
5
3
mA
____
____
____
____
____
____
____
____
S
L
Full Standby Current
(One Port -
CMOS Level Inputs)
mA
CE"A" < 0.2V and
COM'L
IND
S
L
80
80
125
110
70
70
115
100
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port
____
____
____
____
____
____
____
____
S
L
(1)
Outputs Open, f = fMAX
3749 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
5
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
3749 tbl 10
3.3V
3.3V
590
Ω
590
Ω
DATAOUT
DATAOUT
30pF
435Ω
5pF*
435Ω
3749 drw 03
3749 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 1. AC Output Test load.
8
7
6
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
5
tCD1
(Typical, ns)
4
3
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
,
3749 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
6
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3,4) (VCC = 3.3V ± 0.3, TA = 0°C to +70°C)
70V927X25
Com'l Only
70V927X30
Com'l Only
Symbol
tCYC1
Parameter
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time (Flow-Through)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock Rise Time
30
12
35
12
____
____
____
____
____
____
tCH1
tCL1
tR
12
12
____
____
3
3
____
____
tF
Clock Fall Time
3
3
____
____
tSA
Address Setup Time
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
Address Hold Time
tSC
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
tHC
tSB
tHB
tSW
tHW
tSD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
ADS Setup Time
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
1
1
CNTRST Hold Time
____
____
Output Enable to Data Valid
Output Enable to Output Low-Z(1)
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)
Data Output Hold After Clock High
Clock High to Output High-Z (1)
Clock High to Output Low-Z (1)
12
15
____
____
tOLZ
tOHZ
tCD1
tDC
2
2
1
7
1
7
____
____
25
30
____
____
2
2
2
2
2
2
tCKHZ
tCKLZ
Port-to-Port Delay
tCWDD Write Port Clock High to Read Data Delay
tCCS Clock-to-Clock Setup Time
9
9
____
____
____
____
____
____
40
15
50
20
ns
ns
3749 tbl 11
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
This parameter is guaranteed by device characterization, but is not production tested.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
3. 'X' in part number indicates power rating (S or L).
4. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
7
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
(4)
tHC
tHB
tSC
tSB
tHC
tHB
CE1
UB, LB
R/W
tSB
tHW
tHA
tSW
tSA
(5)
ADDRESS
An
An + 1
An + 2
An + 3
(1)
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
DATAOUT
(1)
(1)
tDC
tCKLZ
(1)
tOHZ
tOLZ
tOE
OE(2)
3749 drw 06
Timing Waveform of a Bank Select Flow-Through Read(6,7)
tCYC1
tCH1
tCL1
CLK
tSA tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
tSC tHC
CE0(B1)
tSC tHC
(1)
tCD1
tCD1
tCKHZ
tCD1
(1)
tCD1
(1)
Q0
A1
Q3
Q5
A6
Q1
A2
DATAOUT(B1)
ADDRESS(B2)
(1)
tDC
tCKLZ
tCKLZ
tDC
tCKHZ
tSA tHA
A0
A5
A4
A3
tSC tHC
CE0(B2)
tSC tHC
(1)
(1)
tCD1
(1)
tCKHZ
tCD1
(1)
tCKHZ
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
3749 drw 07
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
6. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V927 for this waveform, and are setup for depth expansion in this example.
ADDRESS(B1) = ADDRESS(B2) in this situation.
7. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
8
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Flow-Through Right Port Read(1,2)
CLK L
tSW tHW
R/W L
tSA tHA
NO
ADDRESS L
DATAIN L
CLK R
MATCH
MATCH
tSD tHD
VALID
(3)
tCCS
tCD1
R/W R
tHW
tHA
tSW
tSA
NO
MATCH
MATCH
ADDRESS R
DATAOUT R
(3)
tCD1
tCWDD
VALID
VALID
tDC
tDC
3749 drw 08
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.42
9
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
tSC tHC
tSB tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
tSD tHD
Dn + 2
ADDRESS
tSA tHA
DATAIN
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
CKHZ
NOP(5)
(1)
tDC
tDC
READ
t
tCKLZ
WRITE
3749 drw 09
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 5
An
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSA tHA
tSD tHD
DATAIN
Dn + 2
tOE
tCD1
tDC
tCD1
tCD1
(2)
Qn + 4
tDC
Qn
DATAOUT
OE
(1)
tCKLZ
(1)
tOHZ
READ
WRITE
READ
3749 drw 10
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
10
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-ThroughReadwithAddressCounter Advance(1)
tCYC1
tCH1
tCL1
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
tSAD tHAD
tSCN tHCN
ADS
CNTEN
tCD1
Qn + 3(4)
Qn + 4
Qx(4)
tDC
Qn
Qn + 1
Qn + 2
DATAOUT
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
3749 drw 11
Timing Waveform of Write with Address Counter Advance(2)
tCYC1
tCH1
tCL1
CLK
tSA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An + 4
An(5)
An + 2
An + 1
An + 3
tSAD tHAD
ADS
CNTEN
tSD tHD
Dn
Dn + 4
Dn + 1
Dn + 3
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
3749 drw 12
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
5. CNTEN = VIL advances Internal Address from An to An +1. The transition shown indicates the time required for the counter to advance. The An +1Address is written
to during this cycle.
6.42
11
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Counter Reset(1)
tCYC1
tCH1
tCL1
CLK
tSA tHA
(3)
An +
An
An + 1
ADDRESS
INTERNAL(2)
ADDRESS
Ax (5)
An + 1
0
1
An
tSW tHW
R/W
tSA tHA
ADS
CNTEN
tSCN tHCN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(4)
An + 1
An
Q1
Q0
DATAOUT
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
READ
ADDRESS n+1
3749 drw 13
NOTES:
CE0, UB, LB = VIL; CE1 = VIH.
1.
2. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
4. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
5. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. ADDR0 will be accessed. Extra cycles are
shown here simply for clarification.
6.42
12
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
TheIDT70V927providesatruesynchronousDual-PortStaticRAM
interface. Registered inputs provide minimal set-up and hold times on
address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulseisindependentoftheLOWtoHIGHtransitionofthe
clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
The IDT70V927 features dual chip enables (refer to Truth Table 1)
in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the various
chip enables in order to expand two devices in depth.
The IDT70V927 can also be used in applications requiring ex-
panded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to
drive the input signals for the various devices as required to allow for
32-bit or wider applications.
A HIGHonCE0oraLOWonCE1 foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V927's for depth
expansion configurations.
A14
IDT70V927
IDT70V927
CE0
CE0
CE1
CE1
VCC
VCC
Control Inputs
Control Inputs
IDT70V927
IDT70V927
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
3749 drw 14
R/
W
,
LB UB
Figure 4. Depth and Width Expansion with IDT70V927
OE
6.42
13
IDT70V927S/L
Preliminary
High-Speed 32K x 16 Synchronous Dual-Port Flow-Through Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
(1)
I
PRF
128-pin TQFP (PK128-1)
25
30
Commercial Only
Speed in nanoseconds
Commercial Only
S
L
Standard Power
Low Power
70V927 512K (32K x 16-Bit) Synchronous Dual-Port RAM
3749 drw 15
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
PreliminaryDatasheet:Definition
"PRELIMINARY" datasheets contain descriptions for products that are in early release.
Datasheet Document History
12/16/98:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Pages 11 & 12 Updated timing waveforms
Page13AddedDepthandWidthExpansionsection
Page 4 Deleted note 5 for Table II
6/15/99:
9/27/99:
Page 2 Changed pin 111 to GND
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
831-754-4613
DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
14
相关型号：
IDT70V9289L12PRFG
Dual-Port SRAM, 64KX16, 25ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, TQFP-128
IDT
©2020 ICPDF网 联系我们和版权申明