IDT70V9389L9PRFGI8 [IDT]
Dual-Port SRAM, 64KX18, 20ns, CMOS, PQFP128, TQFP-128;
| 型号： | IDT70V9389L9PRFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 64KX18, 20ns, CMOS, PQFP128, TQFP-128 静态存储器 |
| 文件： | 总15页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
IDT70V9389L
HIGH-SPEED 3.3V 64K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:7.5/9/12ns (max.)
Low-power operation
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
addressinputs
◆
◆
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timedwriteallowsfastcycletime
– IDT70V9389L
Active:500mW(typ.)
Standby: 1.5mW (typ.)
– 12ns cycle time, 83MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆
◆
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
Available in a 128-pin Thin Quad Flatpack (TQFP)
FunctionalBlockDiagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LBL
LBR
OEL
OER
1b 0b
0a 1a
0b 1b
1a 0a
a
FT/PIPEL
0/1
0/1
b
a
b
FT/PIPER
I/O9L-I/O17L
I/O0L-I/O8L
I/O9R-I/O17R
I/O0R-I/O8R
I/O
Control
I/O
Control
A15R
A15L
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A0R
A0L
CLKL
ADSL
CLKR
ADSR
CNTENR
CNTENL
CNTRSTL
CNTRSTR
4856 drw 01
JUNE 2000
1
©2000IntegratedDeviceTechnology,Inc.
DSC-4856/2
IDT70V938L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70V9389isahigh-speed64Kx18bitsynchronousDual-Port
Withaninputdataregister,theIDT70V9389hasbeenoptimizedfor
RAM. The memory array utilizes Dual-Port memory cells to allow applicationshavingunidirectionalorbidirectionaldataflowinbursts.An
simultaneousaccessofanyaddressfrombothports.Registersoncontrol, automaticpowerdownfeature,controlledbyCE0andCE1, permitsthe
data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming on-chip circuitry of each port to enter a very low standby power mode.
latitudeprovidedbythisapproachallowssystemstobedesignedwithvery Fabricated using IDT’s CMOS high-performance technology, these
shortcycletimes.
devices typicallyoperate ononly500mWofpower.
PinConfiguration(1,2,3)
12R
I/O
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
NC
NC
NC
NC
I/O11R
GND
NC
9R
A
10R
I/O
A8R
9R
I/O
7R
6R
5R
A
A
A
I/O8R
I/O7R
CC
V
9
10
6R
I/O
I/O5R
4R
A4R
A3R
A2R
11
12
13
14
15
16
17
18
19
20
21
22
23
I/O
GND
1R
A
3R
I/O
VCC
A0R
NC
CNTENR
2R
I/O
R
CLK
1R
I/O
70V9389PRF
PK-128-1(4)
I/O0R
GND
VCC
ADSR
GND
CC
V
0L
I/O
I/O
ADSL
128-Pin TQFP
Top View(5)
L
1L
CLK
GND
CNTENL
2L
I/O
I/O
NC
24
25
26
3L
0L
A
GND
I/O4L
I/O5L
1L
A
A2L
3L
27
28
29
30
31
32
33
34
35
36
37
38
A
6L
I/O
A4L
I/O7L
VCC
I/O8L
A5L
6L
A
A7L
9L
I/O
70
69
68
67
66
65
8L
A
A
10L
I/O
9L
NC
VCC
NC
NC
NC
NC
11L
I/O
12L
I/O
4856 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V9389L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables
CE0L, CE1L
CE0R, CE1R
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
A0L - A15L
I/O0L - I/O17L
CLKL
A0R - A15R
I/O0R - I/O17R
CLKR
Data Input/Output
Clock
Upper Byte Select
Lower Byte Select
Address Strobe Enable
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power
UBL
LBL
UBR
LBR
ADSL
ADSR
CNTEN
CNTEN
L
R
CNTRSTL
CNTRSTR
FT/PIPEL
FT/PIPER
VCC
GND
Ground
4856 tbl 01
Truth Table IRead/Write and Enable Control(1,2,3)
Upper Byte
I/O9-17
Lower Byte
I/O0-8
MODE
CLK
↑
CE1
X
L
R/W
X
X
X
L
OE
X
X
X
X
X
X
L
CE0
H
X
L
UB
X
X
H
L
LB
X
X
H
H
L
High-Z
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
↑
H
H
H
H
H
H
H
H
↑
L
↑
L
H
L
L
High-Z
DATAIN
DATAOUT
High-Z
DATAOUT
High-Z
↑
L
L
L
↑
L
L
H
L
H
H
H
X
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
L
H
L
↑
L
L
L
↑
H
X
L
L
L
Outputs Disabled
4856 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.42
3
IDT70V938L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2,6)
Previous
Address
Addr
Used
MODE
(3)
Address
CLK
I/O
ADS
CNTEN CNTRST
X
An
An
X
X
X
0
An
X
X
X
H
L
H
H
H
DI/O(0)
DI/O(n)
DI/O(p)
Counter Reset to Address 0
↑
↑
↑
↑
(4)
L
External Address Loaded into Counter
External Address Blocked—Counter disabled (Ap reused)
Ap
Ap
Ap
H
H
(5)
Ap + 1
L
DI/O(p+1) Counter Enabled—Internal Address generation
4856 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
RecommendedOperating
TemperatureandSupplyVoltage(1)
RecommendedDCOperating
Conditions
Symbol
Parameter
Min.
3.0
0
Typ.
Max.
3.6
0
Unit
V
Ambient
Grade
Commercial
Temperature(2)
0OC to +70OC
-40OC to +85OC
GND
0V
Vcc
VCC
Supply Voltage
3.3
3.3V + 0.3V
3.3V + 0.3V
GND Ground
0
V
Industrial
0V
____
(2)
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
VCC+0.3V
0.8
V
4856 tbl 04
(1)
____
NOTES:
-0.3
V
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
4856 tbl 05
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VCC +0.3V.
AbsoluteMaximumRatings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHZ)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
VIN = 3dV
Max. Unit
(2)
VTE RM
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
CIN
9
pF
(3)
COUT
VOUT = 3dV
10
pF
TBIAS
TSTG
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
4856 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
Storage
Temperature
IOUT
DC Output Current
mA
4856 tbl 06
3. COUT also references CI/O.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 0.3V.
6.42
4
IDT70V9389L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V9389L
Symbol
|ILI|
Parameter
Test Conditions
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
___
Input Leakage Current
Output Leakage Current
Output Low Voltage
VCC = 3.6V, VIN = 0V to VCC
|ILO|
IH
1
IL OUT
CC
5
CE = V or CE = V , V = 0V to V
VOL
IOL = +4mA
0.4
___
VOH
Output High Voltage
IOH = -4mA
2.4
V
4856 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3,6) (VCC = 3.3V ± 0.3V)
70V9389L7
Com'l Only
70V9389L9
Com'l Only
70V9389L12
Com'l Only
Symbol
Parameter
Test Condition
CEL and CER= VIL,
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
CC
I
Dynamic Operating
Current (Both
Ports Active)
mA
L
L
L
L
L
L
200
310
180
260
150
230
Outputs Disabled,
____
____
____
____
____
____
(1)
MAX
IND
f = f
SB1
I
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
COM'L
IND
65
130
50
100
40
80
CEL = CER = VIH
(1)
MAX
f = f
____
____
____
____
____
____
SB2
I
Standby
COM'L
IND
140
245
110
190
100
175
CE"A" = VIL and
(5)
Current (One
Port - TTL
Level Inputs)
CE"B" = VIH
____
____
____
____
____
____
Active Port Outputs Disabled,
(1)
MAX
f=f
SB3
CEL and
I
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports
mA
mA
COM'L
IND
L
L
0.4
3
0.4
3
0.4
3
CE > V - 0.2V,
R
CC
CC
____
____
____
____
____
____
IN
IN
V
> V - 0.2V or
(2)
V
< 0.2V, f = 0
SB4
I
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L
IND
L
L
130
235
100
180
90
165
(5)
CE"B" > VCC - 0.2V
____
____
____
____
____
____
IN
IN
V
CC
V
> V - 0.2V or
< 0.2V, Active Port,
(1)
MAX
Outputs Disabled, f = f
4856 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
5
IDT70V938L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1, 2, and 3
4856 tbl 10
3.3V
3.3V
590Ω
590
Ω
DATAOUT
DATAOUT
30pF
435Ω
5pF*
435Ω
4856 drw 03
4856 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
Figure 1. AC Output Test load.
*Including scope and jig.
8
7
6
5
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD1,
tCD2
(Typical, ns)
4
3
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
.
4856 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
6
IDT70V9389L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VCC = 3.3V ± 0.3V, TA = 0°C to +70°C)
70V9389L7
Com'l Only
70V9389L9
Com'l Only
70V9389L12
Com'l Only
Symbol
Parameter
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)(2)
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tCYC1
22
12
7.5
7.5
5
25
15
12
12
6
30
20
12
12
8
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
(2)
Clock High Time (Flow-Through)
(2)
Clock Low Time (Flow-Through)
(2)
Clock High Time (Pipelined)
(2)
Clock Low Time (Pipelined)
5
6
8
____
____
____
Clock Rise Time
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
tSA
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
tSC
tHC
tSW
tHW
tSD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
Setup Time
CNTRST
0
1
1
CNTRST Hold Time
____
____
____
Output Enable to Data Valid
9
12
12
(1)
____
____
____
tOLZ
tOHZ
tCD1
tCD2
tDC
Output Enable to Output Low-Z
2
2
2
(1)
Output Enable to Output High-Z
1
7
1
7
1
7
(2)
____
____
____
Clock to Data Valid (Flow-Through)
18
20
25
(2)
____
____
____
Clock to Data Valid (Pipelined)
7.5
9
12
____
____
____
Data Output Hold After Clock High
2
2
2
2
2
2
2
2
2
(1)
tCKHZ
tCKLZ
Clock High to Output High-Z
9
9
9
(1)
____
____
____
Clock High to Output Low-Z
Port-to-Port Delay
____
____
____
____
____
____
tCWDD
tCCS
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
28
10
35
15
40
15
ns
ns
4856 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply
when FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.
4. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
7
IDT70V938L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,7)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
tSC tHC
(4)
CE1
tSB
tHB
tHB
tSB
UB, LB
R/W
tSW tHW
tSA tHA
An
ADDRESS(5)
DATAOUT
An + 1
An + 2
An + 3
tDC
(1)
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
tDC
tCKLZ
tOHZ
(1)
tOLZ
OE (2)
tOE
4856 drw 06
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,7)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
(4)
tHC
tHB
tSC tHC
CE1
tSB
(6)
tHB
tSB
UB, LB
R/W
tHW
tHA
tSW
tSA
ADDRESS(5)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
(6)
DATAOUT
Qn + 1
Qn + 2
(1)
tCKLZ
(1)
tOHZ
(1)
tOLZ
tOE
OE(2)
4856 drw 07
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X' here denotes Left or Right port. The diagram is with respect to that port.
6.42
8
IDT70V9389L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
tSA tHA
A6
A5
A4
A3
A2
A0
A1
tSC tHC
tSC tHC
(3)
tCD2
tCKHZ
tCD2
(3)
tCD2
Q0
Q3
A5
Q1
DATAOUT(B1)
ADDRESS(B2)
(3)
tDC
tCKLZ
DC
tCKHZ
t
tSA tHA
A0
A6
A4
A3
A2
A1
tSC tHC
CE0(B2)
tSC tHC
(3)
tCD2
(3)
tCKHZ
tCD2
(3)
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
4856 drw 08
Timing Waveform with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW tHW
R/W "A"
tSA tHA
NO
ADDRESS "A"
DATAIN "A"
CLK "B"
MATCH
MATCH
tSD tHD
VALID
(6)
tCCS
tCD1
R/W "B"
tHW
tHA
tSW
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(6)
tCD1
tCWDD
VALID
VALID
tDC
tDC
4856 drw 09
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9289 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.42
9
IDT70V938L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
tSC tHC
tSB
tHB
UB LB
,
tSW tHW
R/W
tSW tHW
(4)
An + 4
An + 3
An
tSA tHA
An +1
An + 2
An + 2
ADDRESS
tSD
tHD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
4856 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB tHB
UB LB
,
tSW tHW
An + 2
R/W
tSW tHW
(4)
An + 4
An
tSA tHA
An +1
An + 3
Dn + 3
An + 5
ADDRESS
tSD
tHD
DATAIN
Dn + 2
(1)
tCD2
tCD2
tCKLZ
(2)
Qn
Qn + 4
DATAOUT
(1)
tOHZ
OE
READ
WRITE
READ
4856 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
10
IDT70V9389L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
tSC tHC
tSB tHB
,
UB LB
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
tSD tHD
Dn + 2
ADDRESS
tSA tHA
DATAIN
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
(1)
tDC
tCKLZ
tDC
tCKHZ
NOP(5)
READ
WRITE
4856 drw 12
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB LB
,
tSW tHW
tSW tHW
R/W
(4)
An + 5
An
tSA tHA
An + 4
tOE
An +1
An + 2
An + 3
Dn + 3
ADDRESS
tSD tHD
DATAIN
Dn + 2
tDC
tCD1
tCD1
tCD1
(2)
Qn + 4
tDC
Qn
DATAOUT
(1)
tCKLZ
(1)
tOHZ
OE
READ
WRITE
READ
4856 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
11
IDT70V938L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD2
Qn + 2(2)
Qn + 3
Qx - 1(2)
Qn + 1
Qn
Qx
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
4856 drw 14
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
tCYC1
tCH1
tCL1
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
tSAD tHAD
tSCN tHCN
ADS
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
4856 drw 15
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.42
12
IDT70V9389L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
tSAD tHAD
ADS
CNTEN(7)
tSD tHD
Dn
Dn + 4
Dn + 1
Dn + 3
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
4856 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS(4)
An + 2
An + 1
INTERNAL(3)
ADDRESS
Ax(6)
0
1
An
An + 1
tSW tHW
R/W
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
4856 drw 17
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ Address is written to during this cycle.
6.42
13
IDT70V938L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
TheIDT70V9389providesatruesynchronousDual-PortStaticRAM
Depth and Width Expansion
The IDT70V9389features dualchipenables (refertoTruthTable I)
interface. Registered inputs provide minimal set-up and hold times on inordertofacilitaterapidandsimpledepthexpansionwithnorequirements
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked for external logic. Figure 4 illustrates how to control the varioius chip
ontherisingedgeoftheclocksignal,however,theself-timedinternalwrite enables in order to expand two devices in depth.
pulseisindependentoftheLOWtoHIGHtransitionoftheclocksignal.
TheIDT70V9389canalsobeusedinapplicationsrequiringexpanded
An asynchronous output enable is provided to ease asynchronous width, as indicated in Figure 4. Since the banks are allocated at the
bus interfacing. Counter enable inputs are also provided to staff the discretionoftheuser,theexternalcontrollercanbesetuptodrivetheinput
operationoftheaddresscountersforfastinterleavedmemoryapplications. signals for the various devices as required to allow for 36-bit or wider
CE0=VIH orCE1=VILforoneclockcyclewillpowerdowntheinternal applications.
circuitrytoreducestaticpowerconsumption.Multiplechipenablesallow
easierbankingofmultipleIDT70V9389'sfordepthexpansionconfigura-
tions.WhenthePipelinedoutputmodeisenabled,twocyclesarerequired
withCE0 =VIL andCE1 =VIHtore-activate the outputs.
A16
IDT70V9389
IDT70V9389
CE0
CE0
CE1
CE1
VCC
VCC
Control Inputs
Control Inputs
IDT70V9389
IDT70V9389
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
R/W
4856 drw 18
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT70V9389
6.42
14
IDT70V9389L
High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I (1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PRF
128-pin TQFP (PK128-1)
7
9
12
Commercial Only
Commercial Only
Commercial Only
Speed in nanoseconds
L
Low Power
70V9389 1152K (64K x 18-Bit) Synchronous Dual-Port RAM
4856 drw 19
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
PreliminaryDatasheet:Definition
"PRELIMINARY"datasheetscontaindescriptionsforproductsthatareinearlyrelease.
DatasheetDocumentHistory
9/30/99:
11/12/99:
6/23/00:
InitialPublicRelease
Replaced IDT logo
Page 3 ChangedinformationinTruthTableII
Page 4 Increasedstoragetemperatureparameters
ClarifiedTAparameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
CORPORATE HEADQUARTERS
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for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
15
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