IDT71024S20TYI8 [IDT]
Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32;
| 型号： | IDT71024S20TYI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32 静态存储器 光电二极管 |
| 文件： | 总8页 (文件大小：680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Static RAM
1 Meg (128K x 8-Bit)
IDT71024S/MS
Features
Description
◆
128K x 8 advanced high-speed CMOS static RAM
Commercial (0°C to +70°C), Industrial (–40°C to +85°C)
Equal access and cycle times
TheIDT71024isa1,048,576-bithigh-speedstaticRAMorganizedas
128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneeds.
◆
◆
— CommercialandIndustrial:12/15/20ns
Two Chip Selects plus one Output Enable pin
Bidirectional inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 300 and 400 mil Plastic SOJ.
◆
◆
The IDT71024 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71024 are TTL-compat-
ible, and operation is from a single 5V supply. Fully static asynchro-
nous circuitry is used; no clocks or refreshes are required for
operation.
◆
◆
The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32-
pin 400 mil Plastic SOJ.
Functional Block Diagram
A0
•
•
•
•
•
•
1,048,576-BIT
MEMORY ARRAY
ADDRESS
DECODER
A16
8
8
I/O0–I/O
7
¥
I/O CONTROL
8
WE
OE
CONTROL
LOGIC
CS1
CS2
2964 drw 01
OCTOBER 2008
1
©2007IntegratedDeviceTechnology,Inc.
DSC-2964/17
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configuration
Symbol
Rating
Value
Unit
V
NC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
A
CS
WE
CC
15
(2)
V
TERM
Terminal Voltage with Respect to GND –0.5 to +7.0
A16
A14
A12
2
T
BIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
–55 to +125
–55 to +125
1.25
oC
T
STG
oC
A7
A6
A5
A4
A3
A2
A1
A0
A
A
A
A
13
8
SO32-2
SO32-3
P
T
W
9
11
I
OUT
DC Output Current
50
mA
OE
A10
9
2964 tbl 02
NOTES:
10
11
12
13
14
15
16
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
CS
I/O
I/O
I/O
I/O
I/O
1
7
I/O0
6
I/O
I/O
GND
1
5
2. VTERM mustnotexceedVCC +0.5V.
2
4
3
2964 drw 02
SOJ
Top View
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Truth Table(1,2)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max.
Unit
Inputs
CIN
V
7
8
pF
I/O
Function
WE
X
X
X
X
H
H
L
CS
1
CS
X
2
OE
X
X
X
X
H
L
CI/O
V
pF
H
High-Z Deselected – Standby (ISB
High-Z Deselected – Standby (ISB1
High-Z Deselected – Standby (ISB
)
2964 tbl 03
(3)
V
HC
X
X
L
X
)
NOTE:
1. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.
L
)
(3)
LC
V
High-Z Deselected – Standby (ISB1
High-Z Outputs Disabled
DATAOUT Read Data
)
H
H
H
Recommended DC Operating
Conditions
L
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ.
Max.
5.5
0
Unit
V
L
X
DATAIN Write Data
2964 tbl 01
VCC
4.5
5.0
NOTES:
1. H = VIH, L = VIL, X = Don't care.
2. VLC = 0.2V, VHC = VCC –0.2V.
3. Other inputs ≥VHC or ≤VLC.
0
0
V
____
V
IH
Input High Voltage
Input Low Voltage
2.2
VCC+0.5
V
–0.5(1)
0.8
V
____
VIL
2964 tbl 04
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature
0°C to +70°C
–40°C to +85°C
GND
VCC
Commercial
Industrial
0V
5.0V ± 0.5V
5.0V ± 0.5V
0V
2964 tbl 05
6.42
2
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
IDT71024
Symbol
Parameter
Input Leakage Current
Test Condition
CC = Max., VIN = GND to VCC
CC = Max., CS = VIH, VOUT = GND to VCC
OL = 8mA, VCC = Min.
OH = –4mA, VCC = Min.
Min.
Max.
Unit
µA
µA
V
___
|ILI|
V
5
5
___
___
|ILO
|
Output Leakage Current
Output Low Voltage
Output High Voltage
V
1
VOL
I
0.4
___
VOH
I
2.4
V
2964 tbl 06
DC Electrical Characteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
71024S12
71024S15
71024S20
Symbol
Parameters
Dynamic Operating Current,
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Unit
ICC
160
40
160
155
40
155
140
40
140
40
mA
CS ≥ VIH and CS ≤ VIL, Outputs Open,
2
1
(2)
V
CC = Max., f = fMAX
ISB
Standby Power Supply Current (TTL Level)
CS ≥ VIH or CS ≤ VIL, Outputs Open,
CC = Max., f=fMAX
40
10
40
10
mA
mA
1
2
(2)
V
ISB1
Full Standby Power Supply Current
(CMOS Level), CS ≥ VHC or
CS ≤ VLC, Outputs Open,
CC = Max., f = 0(2) , VIN ≤ VLC or VIN ≥ VHC
10
10
10
10
1
2
V
2964 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address
input lines are changing.
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
5V
See Figures 1 and 2
2964 tbl 08
480Ω
255Ω
5V
OUT
DATA
480Ω
5pF*
OUT
DATA
2964 drw 04
30pF
255Ω
*Including jig and scope capacitance.
2964 drw 03
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
6.42
3
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71024S12
71024S15
71024S20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
RC
AA
ACS
Read Cycle Time
12
—
—
3
—
12
12
—
6
15
—
—
3
—
15
15
—
7
20
—
—
3
—
20
20
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Access Time
t
Chip Select Access Time
(1)
CL Z
t
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
OutputDisable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
(1)
tCHZ
0
0
0
tOE
—
0
6
—
0
7
—
0
8
(1)
(1)
tOLZ
—
5
—
5
—
7
tOHZ
0
0
0
tOH
4
—
—
12
4
—
—
15
4
—
—
20
(1)
PU
t
0
0
0
(1)
PD
t
—
—
—
Write Cycle
t
WC
AW
CW
AS
WP
WR
Write Cycle Time
12
10
10
0
—
—
—
—
—
—
—
—
—
5
15
12
12
0
—
—
—
—
—
—
—
—
—
5
20
15
15
0
—
—
—
—
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-Up Time
t
t
t
Write Pulse Width
8
12
0
15
0
t
Write Recovery Time
0
tDW
Data Valid to End-of-Write
Data Hold Time
7
8
9
tDH
0
0
0
(1)
OW
t
Output Active from End-of-Write
Write Enable to Output in High-Z
3
3
4
(1)
WHZ
t
0
0
0
ns
2964 tbl 09
NOTE:
1. This parameterguaranteedwiththeACload(Figure2)bydevicecharacterization,butis notproductiontested.
6.42
4
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
tAA
OE
tOE
(5)
t
OLZ
CS1
CS
2
(3)
tACS
(5)
(5)
t
OHZ
(5)
t
CLZ
t
CHZ
HIGH IMPEDANCE
DATAOUT VALID
DATAOUT
tPD
tPU
Vcc
Icc
SUPPLY
CURRENT
I
SB
2964 drw 05
Timing Waveform of Read Cycle No. 2(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
tOH
PREVIOUS DATAOUT VALID
DATAOUT VALID
DATAOUT
2964 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuouslyselected, CS1 is LOW,CS2 is HIGH.
3. AddressmustbevalidpriortoorcoincidentwiththelaterofCS1 transitionLOWandCS2transitionHIGH;otherwisetAA isthelimitingparameter.
4. OEisLOW.
5. Transitionismeasured±200mVfromsteadystate.
6.42
5
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1
(WE Controlled Timing)(1,4,6)
tWC
ADDRESS
tAW
tCW
CS1
CS2
(2)
tWR
(6)
tAS
tWP
WE
(5)
tCHZ
(5)
OW
(5)
t
tWHZ
HIGH IMPEDANCE
(3)
(3)
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
2964 drw 07
Timing Waveform of Write Cycle No. 2
(CS1 AND CS2 Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS1
CS2
(2)
WR
t
tAS
tCW
WE
tDH
tDW
DATAIN
DATAIN VALID
2964 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.
2. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. IftheCS1LOWtransitionortheCS2 HIGHtransitionoccurssimultaneouslywithoraftertheWE LOWtransition,theoutputsremaininahighimpedancestate. CS1 andCS2 must
both be active during the tCW write period.
5. Transitionismeasured±200mVfromsteadystate.
6. OEis continuouslyHIGH. DuringaWEcontrolledwritecyclewithOELOW,tWP mustbegreaterthanorequaltotWHZ+tDW toallowtheI/Odriverstoturnoffanddatatobeplaced
onthe bus forthe requiredtDW. IfOEis HIGHduringa WEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is the specifiedtWP.
6.42
6
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
71024
S
XX
X
X
M
X
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
G
Restricted hazardous substance device
TY
Y
300-mil SOJ (SO32-2)
400-mil SOJ (SO32-3)
12
15
20
Speed in nanoseconds
First generation or current die step
Current generation die step (optional)
Blank
M
2964 drw 09
6.42
7
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
9/30/99
Updatedtonewformat
Pg. 1, 3, 4, 7
Pg. 1–4, 7
Added12nsindustrialspeedgradeoffering
Removedmilitarytemperatureofferings
Removed 17ns and 25ns speed grades
Pg. 3
Pg. 6
Pg. 8
Pg. 4
Pg. 3
Pg. 3
Revised ICC and ISB1 for 15ns and 20ns industrial speed grades
Removed Note 1, reordered notes and footnotes
AddedDatasheetDocumentHistory
1/6/2000
2/18/00
Changed tWP(min) for 12ns speed grade from 10ns to 8ns.
RevisedIccandISB forIndustrialTemperatureofferingstomeetcommercialspecifications
RevisedISBtoaccomidatespeed functionaility
3/14/00
08/09/00
02/01/01
01/30/04
05/22/06
02/13/07
10/23/08
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
Pg. 7
Pg.3
Pg.7
Pg.7
Added"Restrictedhazardoussubstancedevice"totheorderinginformation.
AddeddrawingOutputCapacitiveDeratingdrawing.
AddedMgenerationdiesteptodatasheetorderinginformation.
Removed"IDT"fromtheorderablepartnumber.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
6.42
8
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
相关型号：
IDT71024S20YGI
Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32
IDT
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