IDT7132LA20CB [IDT]
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM; HIGH -SPEED 2K ×8双端口静态RAM
| 型号： | IDT7132LA20CB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM |
| 文件： | 总11页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7132SA/LA
IDT7142SA/LA
HIGH-SPEED
2K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed access
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port
Static RAMs. The IDT7132 is designed to be used as a stand-
alone 8-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7142 “SLAVE” Dual-Port in 16-bit-or-
more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
— Military: 25/35/55/100ns (max.)
— Commercial: 25/35/55/100ns (max.)
— Commercial: 20ns only in PLCC for 7132
• Low-power operation
— IDT7132/42SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
— IDT7132/42LA
Both devices provide two independent ports with separate
control, address, and l/O pins that permit independent, asyn-
chronousaccessforreadsorwritestoanylocationinmemory.
An automatic power down feature, controlled by CE permits
Active: 550mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• MASTER IDT7132 easily expands data bus width to 16-or- the on-chip circuitry of each port to enter a very low standby
more bits using SLAVE IDT7142
power mode.
• On-chip port arbitration logic (IDT7132 only)
• BUSY output flag on IDT7132; BUSY input on IDT7142
• Battery backup operation —2V data retention
• TTL-compatible, single 5V ±10% power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD, Class B
• Standard Military Drawing # 5962-87002
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 550mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each Dual-Port typically consuming 200µW
from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin
sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and
• Industrial temperature range (–40°C to +85°C) is available, 48-lead flatpacks. Military grade product is manufactured in
tested to miliary electrical specifications
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
OER
OEL
CE
L
CE
R
R/WR
R/W
L
I/O0L- I/O7L
I/O0R-I/O7R
(1,2)
I/O
Control
I/O
Control
BUSY (1,2)
L
BUSY
R
A
10L
0L
A
A
10R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
11
11
NOTES:
1. IDT7132 (MASTER): BUSY is open
drain output and requires pullup
resistor of 270Ω.
ARBITRATION
LOGIC
CEL
CER
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup
resistor of 270Ω.
2692 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2692/8
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.02
1
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (1,2)
INDEX
CE
R/W
BUSY
L
L
L
10L
1
48
47 CE
46 R/W
45 BUSY
44
43 OE
V
CC
R
2
3
R
6
5
4
3
2
48 47 46 45 44 43
1
A
4
R
A
A
A
A
A
A
A
0R
1R
2R
3R
4R
5R
6R
A
1L
2L
3L
4L
5L
6L
7L
8L
9L
7
42
41
40
39
38
37
36
35
34
33
32
31
OE
L
5
A
10R
R
0R
A
A
A
A
A
A
A
A
8
A
A
A
A
A
A
A
A
A
A
0L
1L
2L
3L
4L
5L
6L
7L
8L
9L
6
9
7
42
41
40
39
38
37
36
35
34
33
A
A
A
A
A
A
A
A
A
A
10
11
12
13
14
15
16
17
18
8
1R
2R
3R
4R
5R
6R
7R
8R
9R
IDT7132/42
L48-1
&
IDT7132/
7142
9
10
11
12
13
14
15
16
17
18
F48-1
P48-1
&
C48-2
48-PIN LCC/ FLATPACK
TOP VIEW (3)
A
A
7R
8R
A
9R
I/O0L
I/O1L
I/O2L
DIP
TOP
I/O0L
I/O1L
I/O2L
I/O3L 19
I/O4L 20
I/O5L 21
I/O6L 22
I/O7L 23
GND 24
I/O7R
I/O6R
32 I/O7R
31 I/O6R
30 I/O5R
29 I/O4R
28 I/O3R
27 I/O2R
26 I/O1R
25 I/O0R
VIEW (3)
19 20 21 22 23 24 25 26 27 28 29 30
2692 drw 03
INDEX
2692 drw 02
NOTES:
7
6
5
4
3
2
52 51 50 49 48 47
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
1
8
46
A
1L
2L
3L
4L
5L
6L
7L
8L
9L
OER
9
45
44
43
42
41
40
39
38
37
36
35
34
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0R
10
11
12
13
14
15
16
17
18
19
20
1R
2R
3R
4R
5R
6R
7R
8R
9R
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
IDT7132/42
J52-1
Rating
Commercial
Military
Unit
52-PIN PLCC
TOP VIEW (3)
(2)
VTERM
Terminal Voltage -0.5 to +7.0 -0.5 to +7.0
with Respect to
GND
V
I/O0L
I/O1L
I/O2L
I/O3L
TA
Operating
Temperature
0 to +70
-55 to +125
°C
°C
°C
N/C
TBIAS
TSTG
Temperature
Under Bias
-55 to +125 -65 to +135
-55 to +125 -65 to +150
I/O7R
21 22 23 24 25 26 27 28 29 30 31 32 33
Storage
2692 drw 04
Temperature
IOUT
DC Output
Current
50
50
mA
NOTES:
2692 tbl 01
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc +
0.5V.
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
VCC
Supply Voltage
Supply Voltage
4.5
0
5.0
0
5.5
V
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
GND
0
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
-0.5(1)
—
—
6.0(2)
0.8
V
V
Grade
Military
Commercial
Temperature
-55°C to +125°C
0°C to +70°C
GND
VCC
2692 tbl 03
NOTES:
0V
5.0V ± 10%
5.0V ± 10%
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
0V
2692 tbl 02
6.02
2
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (VCC = 5.0V ± 10%)
7132X20(2) 7132X25(3) 7132X35 7132X55 7132X100
7142X25(3) 7142X35 7142X55 7142X100
Symbol
Parameter
Test Conditions
Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
ICC
Dynamic Operating
Current (Both Ports
Active)
CEL and CER = VIL, MIL.
Outputs open,
SA
LA
—
—
—
—
110 280
110 220
80 230
80 170
80 165
80 120
65 190 65 190 mA
65 140 65 140
65 155 65 155
65 110 65 110
(4)
f = fMAX
COM'L. SA 110 250 110 220
LA 110 200 110 170
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH, MIL.
f = fMAX
SA
LA
—
—
—
—
65
45
30
30
30
30
80
60
65
45
25
25
25
25
80
60
65
45
20 65
20 45
20 65
20 35
20 65
20 45
20 55
20 35
mA
(4)
COM'L. SA 30
LA 30
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
MIL.
SA
LA
—
—
—
—
65 160
65 125
50 150
50 115
50 125
40 125 40 125 mA
40 90 40 90
40 110 40 110
(7)
CE"B" = VIH
Active Port Outputs COM'L. SA 65 165 65 150
(4)
Open, f = fMAX
LA 65 125 65 115
50
90
40 75
40 75
Full Standby Current CEL and
(Both Ports - All
CMOS Level Inputs
MIL.
SA
LA
—
—
—
—
1.0 30
0.2 10
1.0 30
0.2 10
1.0 15
1.0 30
0.2 10
1.0 15
1.0 30
0.2 10
1.0 15
mA
CER > VCC -0.2V,
VIN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15
VIN < 0.2V,f = 0(5)
LA 0.2
5
0.2
5
0.2
4
0.2
40 110 40 110 mA
40 85 40 80
40 100 40 95
40 70 40 70
4
0.2
4
Full Standby Current CE"A" < 0.2V and
(One Port - All
CE"B" > VCC -0.2V(7)
CMOS Level Inputs) VIN > VCC -0.2V or COM'L. SA 60 155 60 145
MIL.
SA
LA
—
—
—
—
60 155
60 115
45 145
45 105
45 110
VIN < 0.2V,
LA 60 115 60 105
45
85
Active Port Outputs
(4)
Open, f = fMAX
NOTES:
2689 tbl 04
1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
3. Not available in DIP packages.
4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = 5V, TA=+25°C for Typ. and is not production tested. Vcc DC = 100mA (Typ.)
7. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
7132SA
7132LA
7142SA
7142LA
Symbol
Parameter
Test Conditions
VCC = 5.5V,
Min.
Max.
Max.
Max.
Unit
|lLl|
Input Leakage
Current(1)
—
10
—
5
µA
VIN = 0V to VCCIN = GND to VCC
|lLO|
Output Leakage
Current(1)
VCC = 5.5V,
—
10
—
5
µA
CE= VIH, VOUT = 0V to VCCC
VOL
VOL
Output Low Voltage
(l/O0-l/O7)
lOL = 4mA
lOL= 16mA
—
—
0.4
0.5
—
—
—
0.4
0.5
—
V
V
Open Drain Output
Low Voltage (BUSY, INT)
lOL = 16mA
VOH
Output High Voltage
Supply Current
lOH = -4mA
VIN > VCC -0.2V or < 0.2V
2.4
2.4
V
NOTE:
2689 tbl 05
1. At Vcc < 2.0V leakages are undefined.
6.02
3
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lDT7132LA/IDT7142LA
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDR
VCC for Data Retention
Data Retention Current
2.0
—
—
—
V
ICCDR
VCC = 2.0V, CE ≥ VCC -0.2V
Mil.
100
100
4000
1500
µA
µA
VIN ≥ VCC -0.2V or VIN ≤ 0.2V Com’l.
—
(3)
tCDR
Chip Deselect to Data
Retention Time
0
—
—
—
—
ns
(3)
(2)
tR
Operation Recovery
Time
tRC
ns
2692 tbl 06
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
AC TEST CONDITIONS
DATA RETENTION WAVEFORM
Input Pulse Levels
GND TO 3.0V
5ns
DATA RETENTION MODE
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
VCC
V
DR
≥
2.0V
Figures 1, 2, and 3
4.5V
4.5V
2692 tbl 07
tCDR
t
R
VDR
CE
V
IH
V
IH
2692 drw 05
5V
5V
1250Ω
1250Ω
DATA OUT
775Ω
DATA OUT
30pF*
775Ω
5pF*
100pF for 55 and 100ns versions
2692 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig
5V
270Ω
BUSY or INT
30pF*
100pF for 55 and 100ns versions
Figure 3. BUSY and INT
AC Output Test Load
6.02
4
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
7132X20(2) 7132X25(5) 7132X35
7142X25(5) 7142X35
7132X55
7142X55
7132X100
7142X100
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time(1,4)
Output High-Z Time(1,4)
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
20
—
—
—
20
20
11
—
—
10
—
20
25
—
—
—
3
—
25
25
12
—
—
10
—
25
35
—
—
—
3
—
35
35
20
—
—
15
—
35
55
—
—
—
3
—
55
55
25
—
—
25
—
50
100
—
—
—
10
5
—
ns
100 ns
100 ns
tACE
tAOE
tOH
tLZ
40
—
—
40
—
50
ns
ns
3
0
0
0
5
ns
tHZ
tPU
—
0
—
0
—
0
—
0
—
0
ns
ns
tPD
—
—
—
—
—
ns
NOTES:
2689 tbl 08
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1)
t
RC
ADDRESS
t
AA
tOH
t
OH
PREVIOUS DATA VALID
DATA VALID
DATAOUT
BUSYOUT
2692 drw 07
(2,3)
t
BDDH
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read
operations, BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6.02
5
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(3)
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
tACE
CE
OE
AOE(4)
t
HZ(2)
t
(2)
HZ
(1)
t
t
LZ
VALID DATA
DATAOUT
t
LZ(1)
(4)
PD
t
t
PU
ICC
CURRENT
50%
50%
I
SS
2692 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = VIH, and the address is valid prior to or coincidental with CE transition Low.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
(2)
(6)
7132X20
7132X25
7132X35
7132X55
7142X55
7132X100
7142X100
(6)
7142X25
7142X35
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC
tEW
tAW
tAS
Write Cycle Time(3)
20
15
15
0
15
0
10
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
25
20
20
0
15
0
12
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
35
30
30
0
25
0
15
—
0
—
0
—
—
—
—
—
—
—
15
—
15
—
55
40
40
0
30
0
20
—
0
—
0
—
—
—
—
—
—
—
25
—
30
—
100
90
90
0
55
0
40
—
0
—
0
—
—
—
—
—
—
—
40
—
40
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Valid to End of Write
Address Set-up Time
tWP
tWR
tDW
tHZ
Write Pulse Width(4)
Write Recovery Time
Data Valid to End of Write
Output High Z Time(1)
tDH
tWZ
tOW
Data Hold Time
Write Enabled to Output in High Z(1)
Output Active From End of Write(1)
NOTES:
2692 tbl 09
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. 0°C to +70°C temperature range only, PLCC package only.
3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
5. “X” in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
CAPACITANCE(1) (TA = +25°C,f = 1.0MHz)
Symbol
Parameter
Conditions(2) Max. Unit
CIN
Input Capacitance
Output Capacitance
VIN = 3dV
VIN = 3dV
11
11
pF
pF
COUT
NOTES:
2692 tbl 10
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.02
6
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/W CONTROLLED TIMING)(1,5,8)
t
WC
ADDRESS
OE
(7)
t
HZ
t
AW
CE
(7)
(2)
WP
(6)
AS
(3)
t
t
t
WR
tHZ
R/W
(7)
t
OW
t
WZ
(4)
(4)
DATA OUT
DATA IN
t
DW
tDH
2692 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CE CONTROLLED TIMING)(1,5)
tWC
ADDRESS
CE
tAW
(6)
AS
(2)
tEW
(3)
t
tWR
R/W
tDW
tDH
DATA IN
2692 drw 10
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
6.02
7
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)8M824S258M824S30 7132158M824S4
7132X20(1) 7132X25(8)
7142X25(8)
7132X35
7132X55 7132X100
7142X35
7142X55 7142X100
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Busy Timing (For Master lDT7130 Only)
tBAA
tBDA
tBAC
tBDC
tWDD
tWH
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(2)
—
—
—
—
—
12
—
5
20
20
20
20
50
—
35
—
25
—
—
—
40
30
—
—
—
—
—
15
—
5
20
20
20
20
50
—
35
—
35
—
—
—
50
35
—
—
—
—
—
20
—
5
20
20
20
20
60
—
35
—
35
—
—
—
60
35
—
—
—
—
—
20
—
5
30
30
30
30
80
—
55
—
50
—
—
—
80
55
—
—
—
—
—
20
—
5
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
120
—
Write Hold After BUSY(6)
tDDD
tAPS
tBDD
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
BUSY Disable to Valid Data(4)
100
—
—
5
—
5
—
5
—
5
—
5
65
Busy Timing (For Slave IDT7140 Only)e
tWB
tWH
Write to BUSY Input(5)
Write Hold After BUSY(6)
Write Pulse to Data Delay(2)
Write Data Valid to Read Data Delay(2)
0
0
0
0
0
—
—
ns
ns
12
—
—
15
—
—
20
—
—
20
—
—
20
—
—
tWDD
tDDD
120
100
ns
ns
NOTES:
2689 tbl 11
1. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. “X” in part numbers indicates power rating (S or L).
8. Not available in DIP package
(1,2,3)
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY
tWC
ADDR’A’
MATCH
t
WP
R/W’A’
t
DW
t
DH
DATAIN’A’
VALID
(1)
tAPS
ADDR’B’
BUSY’B’
MATCH
tBDD
tBDA
tWDD
DATAOUT’B’
VALID
tDDD
NOTES:
2692 drw 11
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port 'B' is opposite from port 'A'.
6.02
8
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSY(3)
t
WP
R/W
L
tWB
BUSY
R
(1)
tWH
R/W
R
(2)
2692 drw 12
NOTES:
1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
(1)
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING
ADDR
ADDRESSES MATCH
'A' and 'B'
CE'B'
(2)
t
APS
CE'A'
t
BAC
tBDC
BUSY'A'
2692 drw 13
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1)
t
RC or tWC
ADDR'A'
ADDR'B'
BUSY'B'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
t
APS
tBAA
tBDA
2692 drw 14
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
6.02
9
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
TRUTH TABLES
The IDT7132/IDT7142 provides two ports with separate
control,addressandI/Opinsthatpermitindependentaccess
for reads or writes to any location in memory. The IDT7132/
IDT7142 has an automatic power down feature controlled by
CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
notselected(CE=VIL). Whenaportisenabled, accesstothe
entire memory array is permitted.
TABLE I — NON-CONTENTION
READ/WRITE CONTROL(4)
Left or Right Port(1)
R/W CE OE
D0–7
Function
X
H
X
Z
Port Disabled and in Power-
Down Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down
Mode, ISB1 or ISB3
L
L
L
L
X
L
DATAIN Data Written Into Memory(2)
DATAOUT Data in Memory Output on Port(3)
BUSY LOGIC
H
H
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
H
Z
High Impedance Outputs
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
2654 tbl 12
TABLE II — ADDRESS BUSY ARBITRATION
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the
BUSYpin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the BUSY pins High.
If desired, unintended write operations can be prevented to
a port by tying the busy pin for that port low.
Inputs
Outputs
A0L-A10L
CER A0R-A10R BUSYL
(1)
(1)
CEL
X
BUSYR
Function
Normal
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
Normal
X
MATCH
H
H
Normal
Write Inhibit(3)
L
MATCH
(2)
(2)
2654 tbl 13
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are
inputs for IDT7140 (slave). BUSYX outputs on the IDT7130 are open
drain,notpush-pulloutputs. Onslavesthe BUSYX inputinternallyinhibits
writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
eitherBUSYL orBUSYR = Low will result. BUSYL andBUSYR outputs can
not be low simultaneously.
The busy outputs on the IDT7132/IDT7142 RAM in master
mode, are pull-up type outputs and do not require pull up
resistors to operate. If these RAMs are being expanded in
depth, then the busy indication for the resulting array re-
quires the use of an external AND gate.
3. Writes to the left port are internally ignored when BUSYL outputs are
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when BUSYR outputs are driving Low regard-
less of actual logic level on the pin.
6.02
10
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, onemasterpartisusedtodecidewhichsideoftheRAM
array will receive a busy indication, and to output that indica-
tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAM the busy
pin is an output if the part is used as a master (M/Spin = VIH),
and the busy pin is an input if the part used as a slave (M/Spin
= VIL) as shown in Figure 4.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busyononeothersideofthearray. Thiswouldinhibitthewrite
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/W signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
LEFT
RIGHT
R/W
R/W
R/W
R/W
IDT7132
MASTER
BUSY
BUSY
BUSY
BUSY
270 Ω
270 Ω
+5V
+5V
R/W
R/W
IDT7142
SLAVE
BUSY
BUSY
2692 drw 15
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and IDT7142 (Slave) RAMs.
ORDERING INFORMATION
IDT
XXXX
A
999
A
A
Device Type Power Speed Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
C
J
L48
F
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
20
25
35
55
100
Commercial PLCC Only
Speed in nanoseconds
LA
SA
Low Power
Standard Power
7132
7142
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
2692 drw 16
6.02
11
相关型号：
IDT7132LA20J8
Dual-Port SRAM, 2KX8, 20ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
IDT
IDT7132LA20JG
Dual-Port SRAM, 2KX8, 20ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52
IDT
IDT7132LA20JG8
Dual-Port SRAM, 2KX8, 20ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52
IDT
©2020 ICPDF网 联系我们和版权申明