IDT7134LA20JI [IDT]
HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM; 高速4K ×8双端口静态SRAM
| 型号： | IDT7134LA20JI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM |
| 文件： | 总11页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
IDT7134SA/LA
4K x 8 DUAL-PORT
STATIC SRAM
Description
Features
◆
The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designedtobeusedinsystemswhereon-chiphardwareportarbitration
is not needed. This part lends itself to those systems which cannot
tolerate wait states or are designed to be able to externally arbitrate or
withstand contention when both sides simultaneously access the
same Dual-Port RAM location.
High-speed access
Military: 25/35/45/55/70ns (max.)
Industrial: 55ns (max.)
Commercial: 20/25/35/45/55/70ns (max.)
Low-power operation
◆
IDT7134SA
TheIDT7134providestwoindependentportswithseparatecontrol,
address, and I/O pins that permit independent, asynchronous access
forreadsorwritestoanylocationinmemory.Itistheusersresponsibility
to ensure data integrity when simultaneously accessing the same
memory location from both ports. An automatic power down feature,
controlled by CE, permits the on-chip circuitry of each port to enter a
very low standby power mode.
FabricatedusingIDTsCMOShigh-performancetechnology,these
Dual-Port typically operate on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery.
Active: 700mW (typ.)
Standby: 5mW (typ.)
IDT7134LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
Fully asynchronous operation from either port
Battery backup operation2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
Military product compliant to MIL-PRF-38535 QML
◆
◆
◆
◆
◆
◆
Industrial temperature range (40°C to +85°C) is available for
The IDT7134 is packaged on either a sidebraze or plastic 48-pin
DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade
product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML, making it ideally suited to military temperature
applicationsdemandingthehighestlevelofperformanceandreliability.
selected speeds
Functional Block Diagram
R/WL
CEL
R/WR
CER
L
OE
OER
COLUMN
COLUMN
I/O0L- I/O7L
I/O0R- I/O7R
I/O
I/O
LEFT SIDE
RIGHT SIDE
ADDRESS
DECODE
LOGIC
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
A0L- A11L
A0R- A11R
2720 drw 01
JUNE 1999
1
DSC-2720/9
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3)
CEL
CC
CER
1
2
3
4
5
6
7
8
9
10
48
47
V
INDEX
R/WL
46 R/WR
45 A11R
10R
11L
A
7
6
5
4
3
2
52 51 50 49 48 47
10L
OEL
A
1
8
46
A1L
A2L
3L
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
44
43
A
9
45
44
43
42
41
40
39
38
37
36
35
34
A0L
OER
A1L
42 A0R
41 A1R
2R
10
11
12
13
14
15
16
17
18
19
20
A
2L
A3L
A4L
A
IDT7134P or C
A4L
A5L
(4)
P48-1
40
A
&
C48-2
39 A3R
38 A4R
37 A5R
6R
(4)
IDT7134J
J52-1(4)
A5L 11
6L
6L
A
A
A
12
13
14
15
16
17
18
19
20
21
22
23
48-Pin
Top
7L
A7L
A8L
36
A
(5)
View
52-Pin PLCC
Top View(5)
A8L
A9L
35 A7R
34 A8R
33 A9R
9L
A
0L
I/O
I/O0L
1L
2L
3L
4L
5L
6L
7L
7R
32 I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
31 I/O6R
30 I/O5R
29 I/O4R
1L
I/O
9R
A
I/O2L
I/O3L
N/C
I/O7R
3R
28 I/O
21 22 23 24 25 26 27 28 29 30 31 32 33
27 I/O2R
26 I/O1R
25 I/O0R
GND 24
2720 drw 03
,
2720 drw 02
INDEX
6
5
4
3
2
48 47 46 45 44 43
1
42
A1L
A2L
7
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
41
40
39
38
37
36
35
34
33
32
31
8
A3L
A4L
A5L
A6L
A7L
A8L
A9L
9
10
11
12
13
14
15
16
17
18
IDT7134L48 or F
L48-1(4)
&
F48-1(4)
48-Pin LCC/Flatpack
Top View(5)
I/O0L
I/O1L
I/O2L
,
NOTES:
19 20 21 22 23 24 25 26 27 28 29 30
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x .61 in x .19 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
J52-1 package body is approximately .75 in x .75 in x .17 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approxiamtely .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of actual part-marking.
2720 drw 04
2
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended Operating
TemperatureandSupplyVoltage(1,2)
Symbol
Rating
Commercial
& Industrial
Military
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
Military
-55OC to +125OC
0OC to +70OC
0V
0V
0V
5.0V + 10%
5.0V + 10%
5.0V + 10%
TBIAS
TSTG
Temperature
Under Bias
-55 to +125
-55 to +125
1.5
-65 to +135
-65 to +150
1.5
oC
oC
W
Commercial
Industrial
-40OC to +85OC
Storage
Temperature
2720 tbl 03
NOTES:
1. This is the parameter TA.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
(3)
PT
Power
Dissipation
DC Output
Current
50
50
mA
IOUT
2720 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%.
3. VTERM = 5.5V.
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max. Unit
VCC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
VIH
Ground
0
0
6.0(2)
0.8
____
Input High Voltage
Input Low Voltage
2.2
____
VIL
-0.5(1)
V
Capacitance(1) (TA = +25°C, f = 1.0MHz)
2720 tbl 04
NOTES:
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
CIN
VIN = 3dV
11
11
pF
COUT
VOUT = 3dV
pF
2720 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5V ± 10%)
7134SA
7134LA
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
CE - VIH, VOUT = 0V to VCC
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
5
5
___
___
___
___
___
___
|ILO|
10
I
OL
= 6mA
0.4
0.4
VOL
IOL = 8mA
IOH = -4mA
0.5
0.5
V
___
___
VOH
Output High Voltage
2.4
2.4
V
2720 tbl 05
NOTES:
1. At Vcc < 2.0V input leakages are undefined.
3
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2,4) (VCC = 5.0V ± 10%)
7134X20
7134X25
Com'l &
Military
7134X35
Com'l &
Military
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
SA
LA
170
170
280
240
160
160
280
220
150
150
260
210
mA
CE = VIL
Outputs Open
(3)
f = fMAX
____
____
____
____
MIL &
IND
SA
LA
160
160
310
260
150
150
300
250
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
SA
LA
25
25
100
80
25
25
80
50
25
25
75
45
mA
mA
mA
mA
CEL and CER = VIH
(3)
f = fMAX
____
____
____
____
MIL &
IND
SA
LA
25
25
100
80
25
25
75
55
Standby Current
(One Port - TTL
Level Inputs)
COM'L
SA
LA
105
105
180
150
95
95
180
140
85
85
170
130
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(3)
f=fMAX
____
____
____
____
MIL &
IND
SA
LA
95
95
210
170
85
85
200
160
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
COM'L
SA
LA
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
____
____
____
____
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE"A" or
COM'L
SA
LA
105
105
170
130
95
95
170
120
85
85
160
110
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
____
____
____
____
MIL &
IND
SA
LA
95
95
210
150
85
85
190
130
(3)
f = fMAX
2720 tbl 06a
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
SA
LA
140
140
240
200
140
140
240
200
140
140
240
200
mA
CE = VIL
Outputs Open
(3)
f = fMAX
MIL &
IND
SA
LA
140
140
280
240
140
140
270
220
140
140
270
220
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
SA
LA
25
25
70
40
25
25
70
40
25
25
70
40
mA
mA
mA
mA
CEL and CER = VIH
(3)
f = fMAX
MIL &
IND
SA
LA
25
25
70
50
25
25
70
50
25
25
70
50
Standby Current
(One Port - TTL
Level Inputs)
COM'L
SA
LA
75
75
160
130
75
75
160
130
75
75
160
130
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(3)
f=fMAX
MIL &
IND
SA
LA
75
75
190
150
75
75
180
150
75
75
180
150
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
COM'L
SA
LA
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE"A" or
COM'L
SA
LA
75
75
150
100
75
75
150
100
75
75
150
100
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
MIL &
IND
SA
LA
75
75
180
120
75
75
170
120
75
75
170
120
(3)
f = fMAX
2720 tbl 06b
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
4
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Characteristics Over All Temperature Ranges
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol
VDR
ICCDR
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
VCC for Data Re te ntio n
VCC = 2V
2.0
___
Data Retention Current
µA
CE > VHC
MIL. & IND.
COM'L.
100
4000
___
VIN > VHC or < VLC
100
1500
(3)
___
___
tCDR
Chip Dese lect to Data Retention Time
Operation Recovery Time
0
ns
(3)
(2)
___
___
tR
tRC
ns
2720 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
4.5V
DR ≥
V
2V
tCDR
IH
tR
DR
V
CE
IH
V
V
2720 drw 05
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1 and 2
2720 tbl 08
+5V
1250
+5V
Ω
1250Ω
DATAOUT
DATAOUT
775Ω
30pF
Ω
775
5pF *
,
,
2720 drw 06
2720 drw 07
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
5
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(3,4)
7134X20
Com'l Only
7134X25
Com'l &
Military
7134X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
tAA
tACE
tAOE
tOH
tLZ
Read Cycle Time
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
Address Access Time
Chip Enable Access Time
20
20
25
25
35
35
____
____
____
____
____
____
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time (1,2)
15
15
20
____
____
____
0
0
0
____
____
____
0
0
0
Output High-Z Time (1,2)
15
15
20
____
____
____
tHZ
tPU
tPD
Chip Enable to Power Up Time (2)
Chip Disable to Power Down Time (2)
0
0
0
____
____
____
____
____
____
20
25
35
ns
2720 tbl 09a
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
45
55
70
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
tAA
Address Access Time
45
45
55
55
70
70
____
____
____
____
____
____
tACE
tAOE
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time (1,2)
25
30
40
____
____
____
OH
t
0
0
0
____
____
____
tLZ
tHZ
5
5
5
Output High-Z Time (1,2)
20
25
30
____
____
____
Chip Enable to Power Up Time (2)
Chip Disable to Power Down Time (2)
0
0
0
____
____
____
PU
t
____
____
____
tPD
45
50
50
ns
2720 tbl 09b
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (SA or LA).
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
6
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
tRC
ADDRESS
(5)
tAA
tOH
OH
t
PREVIOUS DATA VALID
DATA VALID
DATAOUT
2720 drw 08
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
tACE
CE
(2)
(4)
tHZ
tAOE
OE
(2)
(1)
tHZ
tLZ
VALID DATA(4)
DATAOUT
(1)
tLZ
tPU
tPD
ICC
CURRENT
50%
50%
ISB
2720 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
7
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5,7)
7134X20
Com'l Only
7134X25
Com'l &
Military
7134X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
20
15
15
0
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
tWP
tWR
tDW
tHZ
15
0
20
0
25
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
15
15
20
____
____
____
15
15
20
____
____
____
tDH
0
0
3
(1,2)
____
____
____
tWZ
tOW
tWDD
tDDD
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,3)
Write Pulse to Data Delay(4)
15
15
20
____
____
____
3
3
3
____
____
____
40
30
50
30
60
35
Write Data Valid to Read Data Delay (4,6)
ns
____
____
____
2720 tbl 10a
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
Write Cycle Time
45
40
40
0
55
50
50
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
tAW
tAS
tWP
40
0
50
0
60
0
tWR
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
tDW
20
25
30
____
____
____
tHZ
20
25
30
____
____
____
tDH
3
3
3
(1,2)
____
____
____
tWZ
Write Enable to Output in High-Z
20
25
30
tOW
tWDD
tDDD
NOTES:
Output Active from End-of-Write(1, 2,3)
Write Pulse to Data Delay(4)
3
3
3
____
____
____
____
____
____
70
45
80
55
90
70
Write Data Valid to Read Data Delay(4,6)
ns
____
____
____
2720 tbl 10b
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port-to-Port Read.
5. 'X' in part number indicates power rating (SA or LA).
6. tDDD = 35ns for military temperature range.
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
8
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read(1,2,3)
tWC
ADDR "A"
MATCH
tWP
tAW
(1)
R/
W "A"
tDW
DATAIN "A"
ADDR "B"
VALID
MATCH
tWDD
VALID
DATAOUT "B"
tDDD
2720 drw 10
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. OE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(6)
tAS
OE
(3)
tWR
tAW
CE
(7)
(2)
tHZ
tWP
R/W
(7)
(7)
tWZ
tHZ
(7)
tLZ
tOW
(4)
(4)
DATAOUT
tDH
tDW
DATAIN
2720 drw 11
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,4)
tWC
ADDRESS
tAW
CE
(5)
(2)
(3)
tAS
tEW
tWR
R/
W
tDW
tDH
DATAIN
2720 drw 12
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal (CE or R/W) is asserted last.
Truth Table I Read/Write Control
Functional Description
Left or Right Port(1)
The IDT7134 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control(OE).Inthereadmode,theportsOEturnsontheoutputdrivers
whensetLOW.Non-contentionREAD/WRITEconditionsareillustrated
in the table below.
R/W
D0-7
Function
CE OE
X
H
X
Z
Port Deselected and in Power-Down
Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = H, Power Down
Mode ISB1 or ISB3
L
H
X
L
L
X
L
DATAIN
Data on port written into memory
DATAOUT Data in memory output on port
High impedance outputs
X
H
Z
2720 tbl 11
NOTE:
1. A0L - A11L ≠ A0R - A11R
"H" = VIH, "L" = VIL, "X" = Dont Care, and "Z" = High Impedance
10
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXX
A
999
A
A
Device Type Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0 C to +70 C)
°
°
(1)
I
Industrial (-40 C to +85 C)
°
°
B
Military (-55 C to +125 C)
°
°
Compliant to MIL-PRF-38535 QML
P
48-pin Plastic DIP (P48-1)
48-pin Ceramic DIP (C48-2)
52-pin PLCC (J52-1)
C
J
L48
F
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
20
25
35
45
55
70
Commercial Only
Commercial & Military
Commercial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial & Military
Speed in nanoseconds
LA
SA
Low Power
Standard Power
32K (4K x 8-Bit) Dual-Port RAM
7134
2720 drw 13
NOTE:
1. Industrial temperature is available for PLCC packages in standard power.
For other speeds, packages and powers contact your sales office.
Datasheet Document History
3/25/99
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 Added additional notes to pin configurations
Changed drawing format
6/9/99:
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-5166
fax: 408-492-8674
for Tech Support:
831-754-4613
DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
11
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