IDT7134LA20J_技术文档

IDT7134SA/LA

HIGH-SPEED

4K x 8 DUAL-PORT

STATIC RAM

Integrated Device Technology, Inc.

systems which cannot tolerate wait states or are designed to

be able to externally arbitrate or withstand contention when

both sides simultaneously access the same Dual-Port RAM

location.

TheIDT7134providestwoindependentportswithseparate

control, address, and I/O pins that permit independent,

asynchronous access for reads or writes to any location in

memory. It is the user’s responsibility to ensure data integrity

when simultaneously accessing the same memory location

from both ports. An automatic power down feature, controlled

by CE, permits the on-chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT’s CMOS high-performance

technology, these Dual-Port typically on only 500mW of

power. Low-power (LA) versions offer battery backup data

retentioncapability,witheachporttypicallyconsuming200µW

from a 2V battery.

The IDT7134 is packaged on either a sidebraze or plastic

48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Ceramic

Flatpack. Militarygradeproductismanufacturedincompliance

with the latest revision of MIL-STD-883, Class B, making it

ideally suited to military temperature applications demanding

the highest level of performance and reliability.

FEATURES:

• High-speed access

— Military: 25/35/45/55/70ns (max.)

— Commercial: 20/25/35/45/55/70ns (max.)

• Low-power operation

— IDT7134SA

Active: 500mW (typ.)

Standby: 5mW (typ.)

— IDT7134LA

Active: 500mW (typ.)

Standby: 1mW (typ.)

• Fully asynchronous operation from either port

• Battery backup operation—2V data retention

• TTL-compatible; single 5V (±10%) power supply

• Available in several popular hermetic and plastic packages

• Military product compliant to MIL-STD-883, Class B

• Industrialtemperaturerange(–40°Cto+85°C)isavailable,

tested to military electrical specifications

DESCRIPTION:

The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM

designed to be used in systems where on-chip hardware port

arbitration is not needed. This part lends itself to those

FUNCTIONAL BLOCK DIAGRAM

R/

CE

W

L

R/

CE

W

R

OEL

OER

COLUMN

I/O

COLUMN

I/O

I/O0L- I/O7L

I/O0R- I/O7R

LEFT SIDE

ADDRESS

DECODE

LOGIC

RIGHT SIDE

ADDRESS

DECODE

LOGIC

MEMORY

ARRAY

A0L- A11L

A

0R- A11R

2720 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OCTOBER 1996

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

DSC-2720/4

1

6.04

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS^(1,2)

CE

L

1

48

VCC

INDEX

R/W

2

47 CER

3

46 R/W

R

A

A¹1¹0^LL

4

45

44

A

11R

10R

R

7

6

5

4

3

2

52 51 50 49 48 47

1

46

45

44

43

42

41

40

39

38

37

36

35

34

OE

L

5

8

A

1L

OER

A

0L

6

43 OE

9

A

2L

3L

A

0R

A

1L

7

42

41

40

39

38

37

36

35

34

33

A

0R

10

11

12

13

14

15

16

17

18

19

20

1R

2R

3R

4R

5R

6R

7R

8R

9R

A2L

3L

8

1R

2R

3R

4R

5R

6R

7R

8R

9R

IDT7134

P48–1

&

A

4L

5L

9

4L

10

11

12

13

14

15

16

IDT7134

J52-1

PLCC

A

5L

6L

7L

A

6L

7L

8L

9L

C48–2

DIP

A

8L

TOP VIEW (3)

TOP

A9L

(3)

VIEW

I/O0L

I/O1L

I/O2L

I/O3L

I/O1L 17

I/O2L 18

I/O3L 19

I/O4L 20

I/O5L 21

I/O6L 22

I/O7L 23

GND 24

32 I/O7R

31 I/O6R

30 I/O5R

29 I/O4R

28 I/O3R

27 I/O2R

26 I/O1R

25 I/O0R

N/C

I/O7R

21 22 23 24 25 26 27 28 29 30 31 32 33

2720 drw 02

2720 drw 03

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Symbol

Rating

Com’l.

Mil.

Unit

INDEX

(2)

VTERM

Terminal Voltage

with Respect

to Ground

–0.5 to +7.0 –0.5 to +7.0

V

6

5

4

3

2

48 47 46 45 44 43

1

A

1L

7

42

41

40

39

38

37

36

35

34

33

32

31

A

0R

1R

2R

3R

4R

5R

6R

7R

8R

9R

A

2L

3L

4L

8

TA

Operating

0 to +70

–55 to +125 °C

A

9

Temperature

A

10

11

12

13

14

15

16

17

18

IDT7134

L48-1

TBIAS

TSTG

Temperature

Under Bias

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +150 °C

A5L

&

A

6L

7L

F48-1

LCC/Flatpack

Storage

A

Temperature

A

8L

9L

(3)

TOP VIEW

(3)

PT

Power Dissipation

DC Output Current

1.5

50

1.5

50

W

I/O0L

I/O1L

I/O2L

IOUT

mA

I/O7R

I/O6R

2720 tbl 01

NOTES:

19 20 21 22 23 24 25 26 27 28 29 30

1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

abovethoseindicatedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or

10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc

+0.5V.

2720 drw 04

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of actual part-marking.

CAPACITANCE⁽¹⁾(TA = +25°C, f = 1.0MHz)

Symbol

CIN

Parameter

Conditions⁽²⁾Max. Unit

Input Capacitance

Output Capacitance

VIN = 3dv

11

pF

COUT

VOUT = 3dv

pF

2720 tbl 02

NOTES:

1. This parameter is determined by device characterization but is not

production tested.

2. 3dv references the interpolated capacitance when the input and output

signals switch from 0V to 3V and from 3V to 0V.

6.04

2

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Ambient

RECOMMENDEDDCOPERATINGCONDITIONS

Symbol

Parameter

Supply Voltage

Ground

Min. Typ. Max. Unit

VCC

4.5

0

5.0

0

5.5

V

Grade

Military

Commercial

Temperature

–55°C to +125°C

0°C to +70°C

GND

VCC

GND

VIH

0

0V

5.0V ± 10%

Input High Voltage

2.2

—

6.0⁽²⁾

0V

5.0V ± 10%

VIL

Input Low Voltage

–0.5⁽¹⁾

—

0.8

V

2720 tbl 03

NOTES:

2720 tbl 04

1. VIL (min.) > –1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 0.5V.

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE (VCC = 5V ± 10%)

IDT7134SA

IDT7134LA

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

|ILI|

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

VCC = 5.5V, VIN = 0V to VCC

CE = VIH, VOUT = 0V to VCC

IOL = 6mA

—

10

—

5

µA

V

|ILO|

VOL

5

—

0.4

0.5

—

0.4

0.5

—

IOL = 8mA

—

V

VOH

Output High Voltage

IOH = –4mA

2.4

V

NOTE:

1. At Vcc ≤ 2.0V input leakages are undefined.

2720 tbl 05

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE⁽¹⁾(VCC = 5.0V ± 10%)

7134X20⁽⁴⁾

Test Conditions Version Typ.⁽²⁾Max. Typ.⁽²⁾Max. Typ.⁽²⁾Max. Typ.⁽²⁾Max. Typ.⁽²⁾Max. Typ.⁽²⁾Max. Unit

7134X25

7134X35

7134X45

7134X55

7134X70

Symbol

Parameter

Dynamic Operating CE = VIL

ICC

MIL.

S

L

—

160 310 150

160 260 150

300 140

250 140

280 140 270 140 270 mA

240 140 220 140 220

Current

Outputs Open

(3)

(Both Ports Active)

f = fMAX

COM’L. S 170 280 160 280 150

260 140

210 140

240 140 240 140 240

200 140 200 140 200

L

170 240 160 220 150

ISB1

ISB2

ISB3

ISB4

Standby Current

(Both Ports—TTL

CEL and CER = VIH MIL.

f = fMAX

S

L

—

25

100 25

75

55

25

70

50

25

70

50

25

70

50

mA

(3)

80

25

Level Inputs)

COM’L. S

L

25

110

80

25

80

50

25

75

45

25

70

40

25

70

40

25

70

40

Standby Current

(One Port—TTL

CE_"A"= V_ILand

CE_"B"= V_IH

MIL.

S

L

—

95

210 85

170 85

200 75

160 75

190

150

75 180

75 150

75 180 mA

75 150

Level Inputs)

Active Port Outputs COM’L. S 105 180

95

180 85

140 85

170 75

130 75

160

130

75 160

75 130

75 160

75 130

(3)

Open, f = fMAX

Full Standby Current Both Ports CEL and MIL.

(Both Ports—All CER ≥ VCC - 0.2V

L

105 150

S

L

—

1.0

0.2

30 1.0

10 0.2

30 1.0

10 0.2

30

10

1.0

0.2

30

10

1.0 30

0.2 10

mA

CMOS Level Inputs) VIN ≥ VCC - 0.2V or COM’L. S 1.0

15

4.5

1.0

0.2

15 1.0

4.0 0.2

15 1.0

4.0 0.2

15

4.0

1.0

0.2 4.0

15

1.0 15

0.2 4.0

VIN ≤ 0.2V, f = 0⁽³⁾

L

0.2

Full Standby Current One Port CE_"A"or

(One Port—All

MIL.

S

L

—

95

210 85

150 85

190 75

130 75

180

120

75 170

75 120

75 170 mA

75 120

CE_"B"≥ VCC - 0.2V

CMOS Level Inputs) VIN ≥ VCC - 0.2V or COM’L. S 105 170

95

170 85

120 85

160 75

110 75

150

100

75 150

75 100

75 150

75 100

VIN ≤ 0.2V

L

105 130

Active Port Outputs

(3)

Open, f = fMAX

NOTES:

2720 tbl 06

1. “X” in part number indicates power rating (SA or LA).

2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.

3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level

standby ISB3.

4. (Commercial only) 0°C to +70°C temperature range.

6.04

3

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V

Symbol

VDR

Parameter

VCC for Data Retention

Data Retention Current

Test Condition

VCC = 2V

Min. Typ.⁽¹⁾Max.

Unit

V

2.0

—

ICCDR

CE ≥ VHC

MIL.

100

4000

1500

µA

VIN ≥ VHC or < VLC

COM’L.

—

(3)

tCDR

Chip Deselect to Data Retention Time

Operation Recovery Time

0

—

ns

(3)

tR

(2)

tRC

ns

NOTES:

2720 tbl 07

1. VCC = 2V, TA = +25°C, and are not production tested.

2. tRC = Read Cycle Time.

3. This parameter is guaranteed by device characterization, but not production tested.

DATA RETENTION WAVEFORM

DATA RETENTION MODE

DR ≥ 2V

V

CC

4.5V

V

tCDR

tR

VDR

CE

V

IH

VIH

2720 drw 05

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

5ns

1.5V

Figures 1 and 2

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

2720 tbl 08

+5V

1250Ω

DATAOUT

775Ω

30pF *

5pF *

2720 drw 06

2720 drw 07

Figure 2. Output Test Load

Figure 1. AC Output Test Load

(for tLZ, tHZ, tWZ, tOW)

*Including scope and jig

6.04

4

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE⁽⁴⁾

7134X20⁽³⁾

7134X25

7134X35

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

tRC

tAA

Read Cycle Time

20

—

0

—

20

15

—

25

—

0

—

25

15

—

35

—

0

—

35

20

—

ns

Address Access Time

tACE

tAOE

tOH

tLZ

Chip Enable Access Time

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^{(1, 2)}

0

tHZ

tPU

tPD

Output High-Z Time^{(1, 2)}

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

—

0

15

—

20

—

0

15

—

25

—

0

20

—

35

ns

—

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE⁽⁴⁾(CONT'D)

7134X45

7134X55

7134X70

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

tRC

tAA

Read Cycle Time

45

—

0

—

45

25

—

20

—

55

—

0

—

55

30

—

25

—

70

—

0

—

70

40

—

30

—

ns

Address Access Time

tACE

tAOE

tOH

tLZ

Chip Enable Access Time

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^{(1, 2)}

Output High-Z Time^{(1, 2)}

Chip Enable to Power Up Time⁽²⁾

5

tHZ

tPU

—

0

—

0

—

0

tPD

Chip Disable to Power Down Time⁽²⁾

—

45

—

50

—

50

ns

NOTES:

2720 tbl 09

1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. (Commercial only) 0°C to +70°C temperature range only.

4. “X” in part number indicates power rating (SA or LA).

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE^{(1, 2, 3)}

t

RC

ADDRESS

DATAOUT

t

AA

t

OH

tOH

PREVIOUS DATA VALID

DATA VALID

2720 drw 08

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = VIH.

6.04

5

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE^{(1, 3)}

tACE

CE

t

AOE⁽⁴⁾

tHZ⁽²⁾

OE

t

LZ⁽¹⁾

tHZ⁽²⁾

(4)

DATAOUT

VALID DATA

t

LZ⁽¹⁾

t

PU

t

PD

I

CC

CURRENT

50%

I

SB

2720 drw 09

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = VIH.

4. Start of valid data depends on which timing becomes effective , tAOE, tACE or tAA

5. tAA for RAM Address Access and tSAA for Semaphore Address Access.

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE⁽⁶⁾

7134X20⁽⁵⁾

7134X25

7134X35

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

tWC

tEW

tAW

tAS

Write Cycle Time

Chip Enable to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

Write Pulse Width

20

15

0

—

15

—

25

20

0

—

15

—

35

30

0

—

20

—

ns

tWP

tWR

tDW

tHZ

15

0

20

0

25

0

Write RecoveryTime

Data Valid to End-of-Write

Output High-Z Time^{(1, 2)}

Data Hold Time⁽³⁾

15

—

0

15

—

0

20

—

3

tDH

tWZ

Write Enabled to Output in High-Z^{(1, 2)}

—

15

—

15

—

20

ns

tOW

tWDD

Output Active from End-of-Write^{(1, 2, 3)}

Write Pulse to Data Delay⁽⁴⁾

Write Data Valid to Read Data Delay^{(4, 7)}

3

—

40

30

3

—

50

30

3

—

60

35

ns

—

tDDD

ns

NOTES:

2720 tbl 10

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.

5. (Commercial only), 0°C to +70°C temperature range .

6. “X” in part number indicates power rating (SA or LA).

7. tDDD = 35ns for military temperature range.

6.04

6

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE⁽⁶⁾(CONT'D)

7134X45

7134X55

7134X70

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

tWC

tEW

tAW

tAS

Write Cycle Time

45

40

0

—

20

—

55

50

0

—

25

—

70

60

0

—

30

—

ns

Chip Enable to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

Write Pulse Width

tWP

tWR

tDW

tHZ

40

0

50

0

60

0

Write RecoveryTime

Data Valid to End-of-Write

Output High-Z Time^{(1, 2)}

Data Hold Time⁽³⁾

20

—

3

25

—

3

30

—

3

tDH

tWZ

Write Enabled to Output in High-Z^{(1, 2)}

—

20

—

25

—

30

ns

tOW

tWDD

tDDD

Output Active from End-of-Write^{(1, 2, 3)}

Write Pulse to Data Delay⁽⁴⁾

Write Data Valid to Read Data Delay⁽⁴⁾

3

—

70

45

3

—

80

55

3

—

90

70

—

ns

2720 tbl 10

NOTES:

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.

5. (Commercial only), 0°C to +70°C temperature range .

6. “X” in part number indicates power rating (SA or LA).

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ ⁽¹⁾

tWC

ADDR "A"

MATCH

tWP

tAW

R/

W "A"

tDW

DATAIN "A"

ADDR "B"

VALID

MATCH

tWDD

DATAOUT "B"

VALID

tDDD

2720 drw 10

NOTES:

1. Write cycle parameters should be adhered to, in order to ensure proper writing.

2. CEL = CER = VIL. OE"B" = VIL.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6.04

7

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING^{(1, 5, 8)}

t

WC

ADDRESS

OE

(6)

AS

t

(3)

WR

t

AW

t

CE

(7)

(2)

t

HZ

tWP

R/W

(7)

tHZ

(7)

t

WZ

t

LZ

t

OW

(4)

DATAOUT

DATAIN

t

DH

t

DW

2720 drw 11

TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING^{(1, 5)}

tWC

ADDRESS

CE

tAW

(6)

(2)

tEW

(3)

1.20 in

tAS

t

WR

R/W

tDW

tDH

DATAIN

2720 drw 12

NOTES:

1. R/W or CE must be High during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.

3. tWR is measured from the earlier of CE or R/W going High to the end-of-write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal ( CE or R/W )is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output

Test Load (Figure 2).

8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to

be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be

as short as the specified tWP.

6.04

8

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE I – READ/WRITE CONTROL⁽²⁾

FUNCTIONAL DESCRIPTION

Left or Right Port⁽¹⁾

The IDT7134 provides two ports with separate control,

address, and I/O pins that permit independent access for

readsorwritestoanylocationinmemory.Thesedeviceshave

an automatic power down feature controlled by CE. The CE

controls on-chip power down circuitry that permits the

respective port to go into standby mode when not selected

(CE high). When a port is enabled, access to the entire

memory array is permitted. Each port has its own Output

Enable control (OE). In the read mode, the port’s OEturns on

the output drivers when set LOW. Non-contention READ/

WRITE conditions are illustrated in the table below.

R/W

CE OE

D0-7

Function

X

H

L

X

Z

Port Disabled and in Power

Down Mode, ISB2 or ISB4

X

L

Z

CER = CEL = H, Power Down

Mode, ISB1 or ISB3

DATAIN

Data on port written into

memory

H

X

L

DATAOUT Data in memory output on port

High impedance outputs

X

H

Z

2720 tbl 11

NOTES:

1. AOL - A11L ≠ AOR - A11R

2. "H" = HIGH, "L" = LOW, "X" = Don’t Care, and "Z" = High-impedance

ORDERING INFORMATION

IDT

XXXX

A

999

A

Device Type Power

Speed

Package

Process/

Temperature

Range

Blank

B

Commercial (0°C to +70°C)

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

P

48-pin Plastic DIP (P48-1)

48-pin Ceramic DIP (C48-2)

52-pin PLCC (J52-1)

C

J

L48

F

48-pin LCC (L48-1)

48-pin Ceramic Flatpack (F48-1)

Commercial Only

20

25

35

45

55

70

Speed in nanoseconds

LA

SA

Low Power

Standard Power

32K (4K x 8-Bit) Dual-Port RAM

7134

2720 drw 13

6.04

9


型号：	IDT7134LA20J
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM HIGH -SPEED 4K ×8双端口静态RAM
文件：	总9页 (文件大小：113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT7134LA20J [IDT]

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