IDT7140LA25PFGI8 [IDT]
Dual-Port SRAM, 1KX8, 25ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64;
| 型号： | IDT7140LA25PFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 1KX8, 25ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64 静态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7130SA/LA
IDT7140SA/LA
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Features
◆
◆
On-chip port arbitration logic (IDT7130 Only)
High-speed access
◆
◆
◆
◆
◆
◆
◆
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
– Military: 25/35/55/100ns (max.)
– Industrial: 55/100ns (max.)
– Commercial: 20/25/35/55/100ns (max.)
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
Low-power operation
– IDT7130/IDT7140SA
— Active: 550mW (typ.)
— Standby: 5mW (typ.)
– IDT7130/IDT7140LA
— Active: 550mW (typ.)
— Standby: 1mW (typ.)
◆
Available in 48-pin DIP and LCC, 52-pin PLCC, and 64-pin
STQFP and TQFP
◆
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
Functional Block Diagram
OEL
R
OE
CEL
CER
R/WL
R/WR
,
0L
7L
I/O - I/O
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
(1,2)
BUSYL
BUSYR
A9L
A0L
A9R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0R
10
10
ARBITRATION
and
INTERRUPT
LOGIC
L
CE
CER
R
OE
L
OE
R/WR
L
R/W
(2)
(2)
INTR
INTL
2689 drw 01
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
JUNE 2000
1
DSC-2689/10
©2000IntegratedDeviceTechnology,Inc.
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Description
of each port to enter a very low standby power mode.
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-
more-bit memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate con-
trol, address, and I/O pins that permit independent asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on chip circuitry
Fabricated using IDT's CMOS high-performance tech-nology,
these devices typically operate on only 550mW of power. Low-
power (LA) versions offer battery backup data retention capability,
with each Dual-Port typically consuming 200µW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze
or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP
and STQFP. Military grade products are manufactured in compli-
ance with the latest revision of MIL-PRF-38535 QML, making it
ideally suited to military temperature applications demanding the
highest level of performance and reliability.
Pin Configurations(1,2,3)
CEL
1
48
47
46
45
VCC
R/WL
BUSYL
INTL
OEL
A0L
CER
R/WR
BUSYR
INTR
OER
A0R
2
3
4
5
44
43
6
A1L
7
42
A2L
8
IDT7130/40 41
P or C
A1R
A3L
9
40 A2R
P48-1(4)
&
A4L
10
11
12
13
39
38
A3R
A4R
C48-2(4)
A5L
37 A5R
36 A6R
A6L
48-Pin
DIP
A7L
(5)
A8L 14Top View 35
A7R
A9L
15
34 A8R
33
I/O0L 16
A9R
I/O1L
I/O2L
17
18
32 I/O7R
31 I/O6R
30 I/O5R
29 I/O4R
28 I/O3R
INDEX
I/O3L 19
I/O4L 20
6 5 4 3 2
48 47 46 45 44 43
I/O5L
21
1
7
8
9
42
41
40
39
38
37
36
35
34
33
32
31
A0R
A1L
I/O6L 22
I/O7L 23
GND 24
27
I/O2R
A2L
A3L
A1R
A2R
26 I/O1R
25 I/O0R
,
2689 drw 02
10
11
12
13
14
15
16
17
18
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
A4L
IDT7130/40L48 or F
L48-1(4)
&
A5L
A6L
F48-1(4)
A7L
48-Pin LCC/ Flatback
Top View(5)
A8L
A9L
I/O0L
I/O1L
I/O2L
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. P48-1 package body is approximately .55 in x .61 in x .19 in.
19 20 21 22 23 24 25 26 27 28 29 30
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
,
2689 drw 03
2
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
INDEX
7 6 5 4 3 2
52 51 50 49 48 47
1
8
46
45
44
43
42
41
40
39
38
37
36
35
34
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
9
10
11
12
13
14
15
16
17
18
19
20
IDT7130/40J
J52-1(4)
52-Pin PLCC
Top View(5)
1L
I/O
9R
A
2L
I/O
N/C
I/O3L
I/O7R
21 22 23 24 25 26 27 28 29 30 31 32 33
2689 drw 04
INDEX
1
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
N/C
A7L
A8L
A9L
N/C
I/O0L
I/O1L
I/O2L
48
OER
A0R
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
47
46
45
44
43
42
41
40
A1R
A2R
A3R
A4R
A5R
A6R
N/C
A7R
A8R
A9R
N/C
N/C
IDT7130/40TF or PF
PP64-1 & PN64-1(4)
64-Pin STQFP
64-Pin TQFP
Top View(5)
39
38
37
36
35
34
I/O7R
I/O6R
33
,
2689 drw 05
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10 mm x 10 mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Symbol
Rating
Commercial
& Industrial
Military
Unit
Symbol
Parameter
Min.
Typ. Max. Unit
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
VCC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND Ground
0
0
Temperature
Under Bias
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
oC
oC
TBIAS
TSTG
IOUT
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
Storage
Temperature
2689 tbl 02
NOTES:
DC Output
Current
mA
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
2689 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Recommended Operating
Temperature and Supply Voltage(1,2)
Grade
Ambient
Temperature
GND
Vcc
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Military
-55OC to +125OC
0OC to +70OC
0V
0V
0V
5.0V 10%
+
Commercial
Industrial
5.0V+ 10%
-40OC to +85OC
5.0V 10%
+
Capacitance (TA = +25°C, f = 1.0MHz)
STQFP and TQFP Packages Only
2689 tbl 03
NOTES:
Symbol
CIN
Parameter(1 )
Input Capacitance
Output Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
9
pF
COUT
10
pF
2689 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7130SA
7140SA
7130LA
7140LA
Symbol
|ILI|
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
Unit
µA
µA
(1)
___
___
Input Leakage Current
VCC = 5.5V, VIN = 0V to VCC
5
5
(1)
___
___
Output Leakage Current
|ILO|
10
V
CC
- 5.5V,
CE = VIH, VOUT = 0V to VCC
___
___
___
___
VOL
VOL
Output Low Voltage (I/O0-I/O7)
IOL = 4mA
0.4
0.5
0.4
0.5
V
V
Open Drain Output
Low Voltage (BUSY, INT)
IOL = 16mA
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
2689 tbl 04
NOTE:
1. At Vcc < 2.0V leakages are undefined.
4
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5,7) (VCC = 5.0V ± 10%)
7130X20(2)
7140X20(2)
Com'l Only
7130X25
7140X25
Com'l &
Military
7130X35
7140X35
Com'l &
Military
Symbol
Parameter
Test Condition
= VIL
Version
COM'L
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dynamic Ope rating
Curre nt
(Both Ports Active )
SA
LA
110
110
250
200
110
110
220
170
110
110
165
120
mA
CE
L
and CE
R
,
Outputs Disable d
(3)
f = fMAX
____
____
____
____
MIL &
IND
SA
LA
110
110
280
220
110
110
230
170
I
SB1
Standby Curre nt
(Both Ports - TTL
Le ve l Inp uts)
COM'L
SA
LA
30
30
65
45
30
30
65
45
25
25
65
45
mA
mA
mA
CE
L
R
and CE = VIH
(3)
f = fMAX
____
____
____
____
MIL &
IND
SA
LA
30
30
80
60
25
25
80
60
(6)
I
SB2
Standby Curre nt
(One Port - TTL
Le ve l Inp uts)
COM'L
SA
LA
65
65
165
125
65
65
150
115
50
50
125
90
CE"A" = VIL and CE"B" = VIH
Active Port OutputsDisable d,
(3)
f=fMAX
____
____
____
____
MIL &
IND
SA
LA
65
65
160
125
50
50
150
115
I
SB3
Full S tandby Curre nt
COM'L
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
4
CE and
CEL
R
> VCC - 0.2V,
(Both Ports
-
CMOS Le ve l Inputs )
V
IN > VCC - 0.2V or
V
IN < 0.2V, f = 0(4)
____
____
____
____
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full S tandby Curre nt
(One Port -
CMOS Le ve l Inputs )
COM'L
SA
LA
60
60
155
115
60
60
145
105
45
45
110
85
mA
CE < 0.2V and
CE"BA" > VCC - 0.2V
(6)
V
IN > VCC - 0.2V or VIN < 0.2V
____
____
____
____
MIL &
IND
SA
LA
60
60
155
115
45
45
145
105
Active Port Outputs Dis able d,
(3)
f = fMAX
2689 tbl 06a
7130X55
7130X100
7140X55
Com'l, Ind
& Military
7140X100
Com'l, Ind
& Military
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dynamic Ope rating
Curre nt
(Both Ports Active )
COM'L
SA
110
110
155
110
110
110
155
110
mA
CE
L
R
and CE = VIL,
LA
Outputs Disable d
(3)
f = fMAX
MIL &
IND
SA
LA
110
110
190
140
110
110
190
140
I
SB1
Standby Curre nt
(Both Ports - TTL
Le ve l Inp uts)
COM'L
SA
LA
20
20
65
35
20
20
55
35
mA
mA
mA
CE
L
R
and CE = VIH
(3)
f = fMAX
MIL &
IND
SA
LA
20
20
65
45
20
20
65
45
(6)
I
SB2
Standby Curre nt
(One Port - TTL
Le ve l Inp uts)
COM'L
SA
LA
40
40
110
75
40
40
110
75
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Dis able d,
(3)
f=fMAX
MIL &
IND
SA
LA
40
40
125
90
40
40
125
90
I
SB3
Full S tandby Curre nt
COM'L
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
CE and
CEL
R
> VCC - 0.2V,
(Both Ports
-
CMOS Le ve l Inputs )
V
IN > VCC - 0.2V or
V
IN < 0.2V, f = 0(4)
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full S tandby Curre nt
(One Port -
CMOS Le ve l Inputs )
COM'L
SA
LA
40
40
100
70
40
40
95
70
mA
CE < 0.2V and
CE"BA" > VCC - 0.2V
(6)
V
IN > VCC - 0.2V or VIN < 0.2V
MIL &
IND
SA
LA
40
40
110
85
40
40
110
80
Active Port Outputs Dis able d,
(3)
f = fMAX
2689 tb l 0 6b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC and TQFP packages only.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tCYC, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
5
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Characteristics (LA Version Only)
7130LA/7140LA
Symbol
VDR
ICCDR
Parameter
VCC for Data Retention
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
2.0
___
Data Retention Current
µA
MIL. & IND.
COM'L.
100
4000
___
VCC = 2.0V, CE > VCC -0.2V
100
1500
(3)
___
___
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
VIN > VCC -0.2V or VIN < 0.2V
(3)
(2)
___
___
tR
tRC
ns
2689 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
DR
V
2.0V
≥
4.5V
4.5V
tCDR
tR
VDR
CE
VIH
VIH
,
2692 drw 06
6
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
1.5V
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
Figures 1,2 and 3
2689 tbl 08
5V
5V
Ω
1250
1250Ω
OUT
DATA
OUT
DATA
Ω
775
30pF*
775Ω
5pF*
*100pF for 55 and 100ns versions
Figure 2. Output Test Load
Figure 1. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* including scope and jig
5V
270Ω
BUSY or INT
30pF*
*100pF for 55 and 100ns versions
2689 drw 07
Figure 3. BUSY and INT
AC Output Test Load
7
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(3,5)
7130X20(2)
7140X20(2)
Com'l Only
7130X25
7140X25
Com'l &
Military
7130X35
7140X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
tAA
tACE
Address Access Time
Chip Enable Access Time
20
20
25
25
35
35
____
____
____
____
____
____
AOE
t
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,4)
11
12
20
____
____
____
tOH
tLZ
tHZ
tPU
tPD
3
3
3
____
____
____
0
0
0
Output High-Z Time(1,4)
10
10
15
____
____
____
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
0
0
0
____
____
____
____
____
____
20
25
35
ns
2689 tbl 09a
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
tAA
tACE
tAOE
tOH
tLZ
Read Cycle Time
55
100
ns
ns
ns
ns
ns
ns
ns
ns
____
____
Address Access Time
55
55
100
100
____
____
____
____
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,4)
25
40
____
____
3
10
____
____
5
5
Output High-Z Time(1,4)
25
40
____
____
tHZ
tPU
tPD
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
0
0
____
____
____
____
50
50
ns
2689 tbl 09b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. PLCC, TQFP and STQFP packages only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Industrial temperature: for other speeds, packages and powers contact your sales office.
8
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
PREVIOUS DATA VALID
DATA VALID
OUT
DATA
BUSYOUT
2689 drw 08
(2,3)
BDDH
t
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
t
ACE
CE
OE
(2)
(4)
t
AOE
tHZ
(2)
(1)
tHZ
LZ
t
DATAOUT
VALID DATA
(1)
(4)
tLZ
50%
tPD
tPU
ICC
CURRENT
ISS
50%
2689 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
9
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(5,6)
(2)
7130X20
7130X25
7140X25
Com'l &
Military
7130X35
7140X35
Com'l &
Military
(2)
7140X20
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time(3)
20
15
15
0
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(4)
tWP
tWR
tDW
tHZ
15
0
15
0
25
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1)
Data Hold Time
10
12
15
____
____
____
10
10
15
____
____
____
tDH
tWZ
tOW
0
0
0
(1)
____
____
____
Write Enable to Output in High-Z
Output Active from End-of-Write(1)
10
10
15
____
____
____
0
0
0
ns
2689 tbl 10a
7130X55
7130X100
7140X55
Com'l, Ind
& Military
7140X100
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time(3)
55
40
40
0
100
90
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(4)
tWP
tWR
tDW
tHZ
30
0
55
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1)
Data Hold Time
20
40
____
____
25
40
____
____
tDH
tWZ
tOW
0
0
(1)
____
____
Write Enable to Output in High-Z
Output Active from End-of-Write(1)
25
40
____
____
0
0
ns
2689 tbl 10b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but
is not production tested.
2. PLCC, TQFP and STQFP packages only.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data
to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
10
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE
(2)
(3)
(7)
(6)
tWP
tWR
tHZ
tAS
R/W
OUT
IN
(7)
tOW
tDH
tWZ
(4)
(4)
DATA
tDW
DATA
2689 drw 10
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
tAW
CE
(2)
(6)
(3)
tEW
tWR
tAS
R/W
tDW
tDH
IN
DATA
2689 drw 11
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the HIGH impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
11
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7,9)
(1)
7130X20
7130X25
7130X35
7140X35
Com'l &
Military
(1)
7140X20
7140X25
Com'l &
Military
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER IDT 7130)
____
____
____
____
____
____
____
____
____
____
____
____
BAA
t
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BDA
t
BAC
t
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY(6)
BDC
t
20
20
20
____
____
____
WH
t
12
15
20
(2)
____
____
____
WDD
t
Write Pulse to Data Delay
40
50
60
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
BUSY Disable to Valid Data(4)
30
35
35
____
____
____
DDD
t
____
____
____
APS
t
5
5
5
____
____
____
BDD
t
25
35
35
BUSY INPUT TIMING (For SLAVE IDT 7140)
(5)
____
____
____
____
____
____
WB
t
Write to BUSY Input
0
0
0
ns
ns
ns
Write Hold After BUSY(6)
12
15
20
WH
t
(2)
____
____
____
WDD
t
Write Pulse to Data Delay
40
30
50
35
60
35
Write Data Valid to Read Data Delay(2)
ns
____
____
____
DDD
t
2689 tbl 11a
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER IDT 7130)
____
____
____
____
____
____
____
____
BAA
t
30
30
30
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address]
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
BDA
t
BAC
t
BDC
t
30
50
BUSY(6)
____
____
WH
t
Write Hold After
20
20
(2)
____
____
WDD
t
Write Pulse to Data Delay
80
120
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
55
100
____
____
DDD
t
____
____
APS
t
5
5
____
____
BUSY Disable to Valid Data(4)
BDD
t
55
65
BUSY
INPUT TIMING (For SLAVE IDT 7140)
(5)
____
____
____
____
WB
t
Write to BUSY Input
0
0
ns
ns
ns
WH
t
BUSY(6)
Write Hold After
20
20
(2)
____
____
WDD
t
Write Pulse to Data Delay
80
55
120
100
Write Data Valid to Read Data Delay(2)
ns
____
____
DDD
t
2689 tbl 11b
NOTES:
1. PLCC, TQFP and STQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. 'X' in part numbers indicates power rating (S or L).
8. Industrial temperature: for other speeds, packages and powers contact your sales office.
12
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDH
tDW
DATAIN"A"
VALID
(1)
tAPS
ADDR"B"
BUSY"B"
MATCH
tBDD
tBDA
tBAA
tWDD
DATAOUT"B"
VALID
tDDD
2689 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(3)
tWP
R/W"A"
tWB
BUSY"B"
(1)
tWH
,
R/W"B"
(2)
2689 drw 13
NOTES:
1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
13
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
ADDRESSES MATCH
'A' AND 'B'
CE'B'
(2)
tAPS
CE'A'
tBDC
tBAC
BUSY'A'
2689 drw 14
Timing Waveform by BUSY Arbitration Controlled
by Address Match Timing(1)
tRC OR tWC
ADDR'A'
ADDR'B'
BUSY'B'
NOTES:
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
tAPS
tBAA
tBDA
2689 drw 15
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(2,3)
7130X20(1)
7140X20(1)
Com'l Only
7130X25
7140X25
Com'l &
Military
7130X35
7140X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
tAS
Address Set-up Time
0
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
0
____
____
____
20
20
25
25
25
25
____
____
____
Interrupt Reset Time
ns
2689 tbl 12a
NOTES:
1. PLCC, TQFP and STQFP package only.
2. 'X' in part numbers indicates power rating (SA or LA).
3. Industrial temperature: for other speeds, packages and powers contact your sales office.
14
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
tAS
Address Set-up Time
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
____
____
45
45
60
60
____
____
Interrupt Reset Time
ns
2689 tbl 12b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. Industrial temperature: for other speeds, packages and powers contact your sales office.
Timing Waveform of Interrupt Mode(1)
INT Set:
tWC
(2)
ADDR'A'
INTERRUPT ADDRESS
(4)
(3)
tWR
tAS
R/W'A'
(3)
tINS
INT'B'
2689 drw 16
INT Clear:
tRC
ADDR'B'
INTERRUPT CLEAR ADDRESS
(3)
tAS
OE'B'
INT'A'
(3)
INR
t
2689 drw 17
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
15
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Truth Tables
Truth Table I Non-Contention Read/Write Control(4)
Inputs(1)
0-7
R/W
X
D
Function
Port Disabled and in Power-Down Mode, ISB2 or ISB4
CE
H
H
L
OE
X
X
X
L
Z
X
Z
DATAIN
DATAOUT
Z
R
L
IH
SB1
SB3
CE = CE = V , Power-Down Mode, I or I
Data on Port Written into Memory(2)
Data in Memory Output on Port(3)
High Impedance Outputs
L
H
L
H
L
H
2689 tbl 13
NOTES:
1. A0L – A10L • A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II Interrupt Flag(1,4)
Left Port
Right Port
R/WL
L
A9L-A0L
3FF
X
R/WR
X
A9R-A0R
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
CEL
L
OEL
X
INTL
X
CER
X
OER
X
INTR
(2)
L
(3)
X
X
X
X
X
L
L
3FF
3FE
X
H
(3)
X
X
X
X
L
L
L
X
X
X
(2)
X
L
L
3FE
H
X
X
X
Reset Left INTL Flag
2689 tbl 14
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Truth Table III Address BUSY
Arbitration
Inputs
Outputs
A0L-A9L
A0R-A9R
(1)
(1)
Function
Normal
Normal
Normal
CEL
X
CER
X
BUSYL
H
BUSYR
NO MATCH
MATCH
H
H
H
X
H
X
H
MATCH
H
H
(3)
L
L
MATCH
(2)
(2)
Write Inhibit
2689 tbl 15
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for
IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull
outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L'iftheinputs totheoppositeportwerestablepriortotheaddress andenableinputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will
result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
16
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Functional Description
RAMs are being expanded in depth, then the BUSY indication for the
The IDT7130/IDT7140 provides two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7130/IDT7140 has an
automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE = VIH). When a port is enabled,
access to the entire memory array is permitted.
resulting array does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
Whenexpandingan RAMarrayinwidthwhileusingbusylogic,one
master part is used to decide which side of the RAM array will receive
a busy indication, and to output that indication. Any number of slaves
to be addressed in the same address range as the master, use the
busy signal as a write inhibit signal. Thus on the IDT7130/IDT7140
RAMs the BUSY pin is an output if the part is Master (IDT7130), and
the BUSY pin is an input if the part is a Slave (IDT7140) as shown in
Figure 3.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessage center)is assignedtoeachport. The leftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
3FE(HEX), whereawriteis definedas the CER =R/WR =VILperTruth
Table II. The left port clears the interrupt by access address location
3FE access when CEL = OEL =VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port writes to
memory location 3FF (HEX) and to clear the interrupt flag (INTR), the
rightportmustaccess the memorylocation3FF. The message (8bits)
at 3FE or 3FF is user-defined, since it is an addressable SRAM
location.Iftheinterruptfunctionisnotused,addresslocations3FEand
3FF are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table II for the interrupt operation.
5V
CE
CE
SLAVE
Dual Port
RAM
MASTER
Dual Port
RAM
5V
270Ω
BUSYL
BUSYL
BUSYR
BUSYR
270Ω
CE
CE
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
BUSYL
BUSYL
BUSYR
BUSYR
BUSYR
BUSYL
Busy Logic
2689 drw 18
Busy Logic provides a hardware indication that both ports of the
RAMhave accessedthe same locationatthe same time. Italsoallows
one of the two accesses to proceed and signals the other side that the
RAMis “Busy”.TheBUSYpincanthenbeusedtostalltheaccess until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe
event of an illegal or illogical operation. In slave mode the BUSY pin
operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7130 (Master) and IDT7140 (Slave)RAMs.
If two or more master parts were used when expanding in width,
asplitdecisioncouldresultwithonemasterindicatingbusyononeside
of the array and another master indicating busy on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
TheBUSYarbitration,onaMaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actualwrite pulse canbe initiatedwitheitherthe R/Wsignalorthe byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
The BUSY outputs on the IDT7130 RAM (Master) are open drain
type outputs and require open drain resistors to operate. If these
17
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXX
A
999
A
A
Device Type Power Speed Package
Process/
Temperature
Range
BLANK
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
(1)
I
B
°
°
Military (-55 C to +125 C)
Compliant to MIL-PRF-38535 QML
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
P
C
J
48-pin LCC (L48-1)
L48
F
48-pin Ceramic Flatpack (F48-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
PF
TF
20
25
35
55
100
Commercial PLCC, TQFP and STQFP Only
Commercial & Military
Speed in nanoseconds
Commercial & Military
Commercial, Industrial & Military
Commercial, Industrial & Military
LA
SA
Low Power
Standard Power
7130
7140
8K (1K x 8-Bit) MASTER Dual-Port RAM
8K (1K x 8-Bit) SLAVE Dual-Port RAM
2689 drw 19
NOTE:
1. Industrial temperature range is available on selected PLCC packages in standard temperature.
For other speeds, packages and powers contact your sales office.
Datasheet Document History
3/15/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
Changed drawing format
6/8/99:
8/2/99:
Page 2 Correctedpackage numberinnote 3
Page 2 Fixed pin 1 in DIP pin configuration
Replaced IDT logo
Page 4 Increasedstoragetemperatureparameters
ClarifiedTAparameter
9/29/99:
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