IDT7164L35YGI8 [IDT]
Standard SRAM, 8KX8, 35ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, SOJ-28;
| 型号： | IDT7164L35YGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 8KX8, 35ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, SOJ-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Static RAM
64K (8K x 8-Bit)
IDT7164S
IDT7164L
Features
Description
◆
High-speed address/chip select access time
TheIDT7164isa65,536bithigh-speedstaticRAMorganizedas8K
x8.Itisfabricatedusinghigh-performance,high-reliabilityCMOStech-
nology.
– Military:20/25/35/45/55/70/85/100ns(max.)
– Industrial:20/25ns(max.)
– Commercial: 20/25ns (max.)
Addressaccesstimesasfastas20nsareavailableandthecircuitoffers
a reduced power standby mode. When CS1 goes HIGH or CS2 goes
LOW,thecircuitwillautomaticallygoto,andremainin,alow-powerstand-
by mode. The low-power (L) version also offers a battery backup data
retention capability at power supply levels as low as 2V.
All inputs and outputs of the IDT7164 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
◆
Low power consumption
◆
Battery backup operation – 2V data retention voltage
(L Version only)
◆
Produced with advanced CMOS high-performance
technology
◆
Inputs and outputs directly TTL-compatible
◆
Three-state outputs
◆
Available in 28-pin DIP, CERDIP and SOJ
◆
Military product compliant to MIL-STD-883, Class B
TheIDT7164ispackagedina28-pin300milCERDIP,a28-pin600
mil CERDIP, 300mil Plastic DIP and 300mil SOJ
◆
Green parts available, see ordering information
Militarygradeproductismanufacturedincompliancewith MIL-STD-
883,ClassB,makingitideallysuitedtomilitarytemperatureapplications
demandingthehighestlevelofperformanceandreliability.
Functional Block Diagram
A
0
VCC
GND
65,536 BIT
MEMORY ARRAY
ADDRESS
DECODER
A
12
7
0
I/O
0
I/O CONTROL
7
I/O
CS
CS
OE
WE
1
2
CONTROL
LOGIC
2967 drw 01
DECEMBER 2016
1
©2016 Integrated Device Technology, Inc.
DSC-2967/17
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
PinConfigurations
Symbol
Rating
Com'l.
Mil.
Unit
(2)
V
WE
CS
CC
V
TE RM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
NC
1
28
27
26
25
24
A12
2
2
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
0
1
2
3
Operating
0 to +70
-55 to +125
-65 to +135
oC
oC
A
A
A
8
4
TA
9
Temperature
5
CD28
SD28
11
6
23
22
Temperature
Under Bias
-55 to +125
TBIAS
OE
7
PJG28
PTG28
A10
8
21
20
TSTG
Storage Temperature -55 to +125
-65 to +150
oC
W
CS
1
9
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
10
11
12
13
14
19
18
17
16
P
T
Power Dissipation
DC Output Current
1.0
50
1.0
50
I/O
I/O
I/O
IOUT
mA
2967 tbl 02
NOTES:
15
GND
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
2967 drw 02
DIP/SOJ
Top View
Pin Descriptions
Truth Table(1,2,3)
WE
X
CS1
OE
X
CS
X
2
I/O
Function
Name
Description
Address
H
X
High-Z
High-Z
High-Z
Deselected - Standby (ISB
)
)
A0 - A12
X
L
X
Deselected - Standby (ISB
I/O0
- I/O
CS
CS
7
Data Input/Output
Chip Select
Chip Select
Write Enable
Output Enable
Ground
X
V
HC or
X
Deselected - Standby (ISB1
)
V
HC
1
V
V
LC
2
X
H
H
L
X
L
L
L
LC
X
H
L
High-Z
High-Z
Deselected - Standby (ISB1)
WE
OE
H
Output Disabled
Read Data
H
H
DATAOUT
DATAIN
GND
X
Write Data
V
CC
Power
2967 tbl 03
NOTES:
2967 tbl 01
1. CS2 will power-down CS1, but CS1 will not power-down CS2.
2. H = VIH, L = VIL, X = don't care.
3. VLC = 0.2V, VHC = VCC - 0.2V
Recommended DC Operating
Conditions
Recommended Operating
Symbol
Parameter
Supply Voltage
Ground
Min.
4.5
Typ.
Max.
5.5
Unit
V
Temperature and Supply Voltage
V
CC
5.0
Grade
Temperature
-55OC to +125OC
-40OC to +85OC
0OC to +70OC
GND
0V
Vcc
GND
0
0
0
V
Military
5V ± 10%
5V ± 10%
5V ± 10%
____
V
IH
Input HIGH Voltage
Input LOW Voltage
2.2
-0.5(1)
V
CC + 0.5
0.8
V
Industrial
0V
____
V
IL
V
Commercial
0V
2967 tbl 05
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
2967 tbl 04
2
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 0V
OUT = 0V
Max.
Unit
CIN
V
8
8
pF
CI/O
V
pF
2967 tbl 06
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S20
7164L20
7164S25
7164L25
Com'l.
100
90
Ind.
110
100
170
150
20
Mil.
110
100
180
160
20
Com'l.
90
Ind.
110
100
170
150
20
Symbol
Parameter
Power
Mil.
110
100
180
160
20
Unit
ICC1
Operating Power Supply Current
2
mA
S
L
S
L
S
L
CS
1
= VIL, CS
= VIH, Outputs Open
V
CC = Max., f
=
0(2)
90
ICC2
Dynamic Operating Current
CS = VIL, CS = VIH, Outputs Open
CC = Max., f = fMAX
mA
mA
mA
170
150
20
170
150
20
1
2
(2)
V
ISB
Standby Power Supply Current
(TTL Level), CS1 > VIH, CS2 < VIL,
Outputs Open, VCC = Max., f = fMAX
(2)
3
3
5
3
3
5
ISB1
Full Standby Power Supply Current
(CMOS Level), f = 0(2), VCC = Max.
S
L
15
15
20
1
15
15
20
1
1. CS
2. CS
1
2
> VHC and CS
< VLC
2 > VHC, or
0.2
0.2
0.2
0.2
2967 tbl 07
7164S35 7164S45 7164S55 7164S70 7164S85/100
7164L35 7164L45 7164L55 7164L70 7164L85/100
Mil.
100
90
Mil.
100
90
Mil.
100
90
Mil.
100
90
Symbol
Parameter
Power
Mil.
100
90
Unit
ICC1 Operating Power Supply Current
mA
S
L
S
L
S
L
CS1 = VIL, CS = VIH, Outputs Open
CC = Max., f
2
=
V
0(2)
ICC2
Dynamic Operating Current
CS = VIL, CS = VIH, Outputs Open
CC = Max., f = fMAX
mA
mA
mA
160
140
20
160
130
20
160
125
20
160
120
20
160
120
20
1
2
(2)
V
ISB
Standby Power Supply Current
(TTL Level), CS > VIH, CS
Outputs Open, VCC = Max., f = fMAX
1
2 < VIL,
(2)
5
5
5
5
5
I
SB1 Full Standby Power Supply Current
(CMOS Level), f = 0(2), VCC = Max.
1. CS > VHC and CS > VHC, or
2. CS < VLC
S
L
20
1
20
1
20
1
20
1
20
1
1
2
2
2967 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
6.42
3
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DC Electrical Characteristics (VCC = 5.0V ± 10%)
IDT7164S
Max.
IDT7164L
Symbol
Parameter
Test Conditions
Min.
Min.
Max.
Unit
____
____
____
____
Input Leakage Current
|ILI|
V
= Max.,
MIL.
10
5
5
2
VICNC= GND to VCC
COM'L. & IND
µA
____
____
____
____
|ILO
|
Output Leakage Current
Output Low Voltage
V
= Max., CS
1
= VIH
,
MIL.
10
5
5
2
VOCCUT = GND to VCC
COM'L. & IND
µA
V
____
____
____
____
V
V
OL
I
OL = 8mA, VCC = Min.
OL = 10mA, VCC = Min.
OH = -4mA, VCC = Min.
0.4
0.4
I
0.5
____
0.5
____
OH
Output High Voltage
I
2.4
2.4
V
2967 tbl 09
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ.(1)
Max.
V
CC
@
V
CC
@
Symbol
Parameter
Test Condition
Min.
2.0V
____
3.0V
____
2.0V
____
3.0V
____
Unit
V
____
V
DR
V
CC for Data Retention
2.0
____
Data Retention Current
MIL.
10
10
15
15
200
60
300
90
µA
ICCDR
____
COM'L. & IND
(3)
____
____
____
____
t
CDR
Chip Deselect to Data
Retention Time
0
ns
1. CS > V
CS1 > VHC, or
2. CS2
2
< VHLCC
____
____
____
____
____
____
(3)
(2)
Operation Recovery Time
Input Leakage Current
ns
tR
t
RC
(3)
____
2
2
µA
II I
LI
2967 tbl 10
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
5ns
1.5V
1.5V
See Figures 1 and 2
2967 tbl 11
5V
5V
480Ω
480Ω
DATAOUT
255Ω
DATAOUT
5pF*
255Ω
30pF*
,
,
2967 drw 04
2967 drw 03
Figure 2. AC Test Load
Figure 1. AC Test Load
(for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)
*Includes scope and jig capacitances
4
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
7164S20
7164L20
7164S25
7164L25
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Read Cycle
____
____
t
RC
Read Cycle Time
20
25
ns
ns
ns
____
____
tAA
Address Access Time
19
20
25
25
____
____
____
____
(1)
ACS1
Chip Select-1 Access Time
t
(1)
ACS2
Chip Select-2 Access Time
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
____
____
(2)
CLZ1,2
Chip Select-1, 2 to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select-1,2 to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
5
5
t
____
____
tOE
8
12
____
____
(2)
OLZ
0
0
t
____
____
(2)
CHZ1,2
9
13
t
____
____
(2)
OHZ
8
10
t
____
____
tOH
5
5
____
____
(2)
PU
0
0
t
____
____
(2)
PD
20
25
t
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
CW1,2
AW
AS
WP
WR1
WR2
Write Cycle Time
20
15
15
0
25
18
18
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
15
0
21
0
t
Write Recovery Time (CS , WE)
1
t
Write Recovery Time (CS
2)
5
5
____
____
(2)
WHZ
Write Enable to Output in High-Z
Data to Write Time Overlap
8
10
t
____
____
t
DW
DH1
DH2
10
0
13
0
____
____
____
____
t
Data Hold from Write Time (CS , WE)
1
t
Data Hold from Write Time (CS
2)
5
5
____
____
(2)
OW
Output Active from End-of-Write
4
4
ns
t
2967 tbl 12
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
6.42
5
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (con't.)(VCC = 5.0V ± 10%, Military Temperature Ranges)
7164S35
7164L35
7164S45
7164L45
7164S55
7164L55
7164S70
7164L70
7164S85/100
7164L85/100
Symbol
Parameter
Unit
Max.
Min.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
____
____
____
____
____
t
RC
Read Cycle Time
35
45
55
70
85/100
ns
ns
ns
____
____
____
____
____
tAA
Address Access Time
35
35
45
45
55
55
70
70
85/100
85/100
____
____
____
____
____
____
____
____
____
____
(1)
ACS1
Chip Select-1 Access Time
t
(1)
ACS2
Chip Select-2 Access Time
40
45
55
70
85/100
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
____
____
____
____
____
(2)
CLZ1,2
Chip Select-1, 2 to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select-1,2 to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
5
5
5
5
5
t
____
____
____
____
____
tOE
18
25
30
35
40
____
____
____
____
____
(2)
OLZ
0
0
0
0
0
t
____
____
____
____
____
(2)
CHZ1,2
15
20
25
30
35
t
____
____
____
____
____
(2)
OHZ
15
20
25
30
35
t
____
____
____
____
____
tOH
5
5
5
5
5
____
____
____
____
____
(2)
PU
0
0
0
0
0
t
____
____
____
____
____
(2)
PD
35
45
55
70
85/100
t
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
CW1,2
AW
AS
WP
WR1
WR2
Write Cycle Time
35
25
25
0
45
33
33
0
55
50
50
0
70
60
60
0
85/100
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
75
t
0
t
25
0
25
0
50
0
60
0
75
t
Write Recovery Time (CS
1
, WE)
0
t
Write Recovery Time (CS
2)
5
5
5
5
5
____
____
____
____
____
(2)
WHZ
Write Enable to Output in High-Z
Data to Write Time Overlap
14
18
25
30
35
t
____
____
____
____
____
t
DW
DH1
DH2
15
0
20
0
25
0
30
0
35
0
____
____
____
____
____
____
____
____
____
____
t
Data Hold from Write Time (CS , WE)
1
t
Data Hold from Write Time (CS
2)
5
5
5
5
5
____
____
____
____
____
(2)
OW
Output Active from End-of-Write
4
4
4
4
4
ns
t
2967 tbl 13
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
6
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
tOH
tAA
OE
tOE
(5)
t
OLZ
CS2
t
(5)
ACS2
(5)
tCHZ2
tCLZ2
CS1
(5)
OHZ
tACS1
t
(5)
(5)
CLZ1
t
tCHZ1
DATAOUT
DATA VALID
2967 drw 05
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC
ADDRESS
t
AA
t
OH
t
OH
DATAOUT
DATA VALID
2967 drw 06
Timing Waveform of Read Cycle No. 3(1,3,4)
CS1
CS2
t
ACS2
(5)
(5)
(5)
(5)
t
CHZ2
t
CLZ2
tACS1
t
CHZ1
t
CLZ1
DATAOUT
DATA VALID
tPU
I
CC
POWER
SUPPLY
CURRENT
I
SB
t
PD
NOTES:
1. WE is HIGH for Read cycle.
2967 drw 07
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
7
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,5)
t
WC
ADDRESS
CS2
CS1
(2)
WR1
t
tAW
tAS
WE
(3)
(5)
(6)
OW
tWP
t
DATAOUT
DATAIN
tDH1,2
t
DW
(6)
tWHZ
DATA VALID
2967 drw 08
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1)
tWC
ADDRESS
(2)
WR2
tAS
t
CS2
(2)
WR1
tCW
t
(4)
CS1
tAW
WE
tDW
tDH1,2
DATAIN
DATA VALID
2967 drw 09
NOTES:
1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2.
2. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to
turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum
write pulse width is as short as the specified tWP.
6. Transition is measured ±200mV from steady state.
8
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
VCC
4.5V
4.5V
VDR ≥ 2V
t
CDR
tR
CS
VIH
VIH
VDR
2967 drw 10
OrderingInformation
7164
X
XX
XXX
X
X
X
Device Power Speed
Type
Package
Process/
Temperature
Range
Tube
Tape and Reel
Blank
8
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Compliant with MIL-STD-883, Class B
G(2)
Green
Y
300 mil SOJ (PJG28)
TP
D
300 mil Plastic DIP (PTG28)
600 mil CERDIP (CD28)
300 mil CERDIP (SD28)
TD
20
25
35
45
55
70
85
100
Commercial, Industrial & Military
Commercial, Industrial & Military
Military Only
Military Only
Military Only
Military Only
Military Only
Military Only
Speed in nanoseconds
S
L
Standard Power
Low Power
2967 drw 11
NOTES:
1. Contactyourlocalsalesofficeforindustrialtemprangeforotherspeeds,packagesandpowers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
6.42
9
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DatasheetDocumentHistory
01/13/00
Updatedtonewformat
Pp. 1, 2, 3, 5, 10
Pp. 1, 3, 9
Pp. 1, 3, 6, 10
Pg. 3
AddedIndustrialTemperaturerangeofferings
Removedcommercial70nsspeedgradeoffering
Added100nsspeedgradespecificationdetails
RevisednotesandfootnotesinDCElectricaltables
Pp. 5, 6
RevisednotesandfootnotesinACElectricaltables
Pg. 8
Removed Note 1 from Write Cycle No. 1 and No. 2 diagrams; renumbered notes and footnotes
SeparatedOrderingInformationintocommercial,industrial,andmilitaryofferings
AddedDatasheetDocumentHistory
Pp. 9, 10
Pg. 11
08/09/00
02/01/01
12/07/01
09/30/04
11/16/06
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
Pg. 10
Pg. 9,10
Pg.3
AddPJ28toIndustrialtemperature.
Added"restrictedhazardoussubstancedevice"toorderinginformation.
Addedindustrialtemppowerlimitsfor20nspart.Changedpowerlimitsfor25nspartforcommercial
andindustrial. Changedpowerlimitsforcommercialandindustrialfor35nspart.
Added 20ns part to ordering information. Refer to PCN SR-0602-01
AddedLgenerationdiesteptodatasheetorderinginformation.
Obsoleted24-pin600mil,15nsforCommercialand35nsforIndustrial&Commercial.
AddedTapeandReeltoOrderinginformationandupdateddescriptionofRestrictedhazardous
substancedevicetoGreen.
Pg.10
02/20/07
04/27/11
Pg. 9, 10
Pg. 1-3,5,6,9
10/30/13
12/06/16
Pg. 1
Pg. 2
IntheDescription:RemovedreferencetoIDT's fabricationandremoved"thelatestrevisionof".
Removedhalfmoonfromthepinconfigurationdiagramforallpackagestoreflectpin1orientation
and added dot at pin 1
UpdatedthepackagecodesintheDIP/SOJpinconfiguration
UpdatedthepackagecodesintheOrderingInformation
Pg. 9
Updated the BLANK designator from "Tube and Tray" to "Tube" in Ordering Information
AddedstandardfootnotestoOrderingInformationwithinstructionsfororderingIndustrial tempand
Greenparts
Pg. 1 & 9
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
sramhelp@idt.com
408-284-4532
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
10
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