IDT7187L85DBG [IDT]
Standard SRAM, 64KX1, 85ns, CMOS, CDIP22, 0.300 INCH, CERAMIC, DIP-22;
| 型号： | IDT7187L85DBG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 64KX1, 85ns, CMOS, CDIP22, 0.300 INCH, CERAMIC, DIP-22 CD 静态存储器 内存集成电路 |
| 文件： | 总8页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7187S
IDT7187L
CMOS Static RAM
64K (64K x 1-Bit)
Description
Features
◆
TheIDT7187isa65,536-bithigh-speedstaticRAMorganizedas64K
x1.ItisfabricatedusingIDT’shigh-performance,high-reliabilityCMOS
technology.Accesstimesasfastas25nsareavailable.
Both the standard (S) and low-power (L) versions of the IDT7187
provide two standby modes—ISB and ISB1. ISB provides low-power
operation;ISB1 provides ultra-low-poweroperation. The low-power(L)
version also provides the capability for data retention using battery
backup. When using a 2V battery, the circuit typically consumes only
30µW.
Ease of system design is achieved by the IDT7187 with full
asynchronous operation,alongwithmatchingaccess andcycletimes.
Thedeviceispackagedinanindustrystandard22-pin,300milceramic
DIP.
High speed (equal access and cycle time)
– Military: 25/35/45/55/70/85ns (max.)
Low power consumption
Battery backup operation—2V data retention
(L version only)
JEDEC standard high-density 22-pin ceramic
DIP packaging
Produced with advanced CMOS high-performance
technology
◆
◆
◆
◆
◆
Separate data input and output
Input and output directly TTL-compatible
Military product compliant to MIL-STD-883, Class B
◆
◆
Militarygradeproductismanufacturedincompliancewiththelatest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demandingthe highestlevelofperformance
and reliability.
Functional Block Diagram
A
A
A
CC
V
GND
65,536-BIT
MEMORY ARRAY
ROW
SELECT
A
A
A
A
CS
DATAOUT
IN
DATA
COLUMN I/O
WE
2986 drw 01
A
A
A
A
A
A
A
FEBRUARY 2001
1
©2000IntegratedDeviceTechnology,Inc.
DSC-2986/09
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
AbsoluteMaximumRatings(1)
PinConfiguration
Symbol
Rating
Value
-0.5 to +7.0
-55 to +125
-65 to +135
-65 to +150
1.0
Unit
V
A0
CC
V
15
A
14
A
13
A
12
A
11
A
10
A
1
22
V
TERM Terminal Voltage with Respect to GND
A
1
2
21
20
T
A
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
oC
oC
oC
W
A2
3
TBIAS
A
A
A5
3
4
19
18
17
16
T
STG
4
5
D22-1
6
P
T
A
A
6
7
7
IOUT
DC Output Current
50
mA
15
14
13
12
8
9
8
A
A
2986 tbl 03
9
NOTE:
OUT
DATA
,
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operationofthe device atthese oranyotherconditions above those indicatedinthe
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
WE
GND
10
11
DATAIN
CS
2986 drw 02
DIP
Capacitance (TA = +25°C, f = 1.0MHz)
Top View
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
IN = 0V
OUT = 0V
Max.
8
Unit
CIN
V
pF
COUT
V
8
pF
2986 tbl 04
Pin Descriptions
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Name
Description
A
0
- A15
Address Inputs
Chip Select
Write Enable
Power
CS
RecommendedDCOperations
Conditions
WE
V
CC
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ.
Max. Unit
DATAIN
DATAOUT
GND
Data Input
Data Output
Ground
VCC
4.5
5.0
5.5
0
V
V
V
0
0
____
VIH
Input High Voltage
Input Low Voltage
2.2
6.0
0.8
2986 tbl 01
-0.5(1)
V
____
VIL
2986 tbl 05
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
Truth Table(1)
CS
H
L
WE
X
Mode
Output
Power
RecommendedOperating
Standby
High-Z
Standby
Active
Temperature and Supply Voltage
Read
Write
H
DOUT
Grade
Temperature
GND
Vcc
L
L
High-Z
Active
Military
-55OC to +125OC
0V
5V ± 10%
2986 tbl 02
NOTE:
2986 tbl 06
1. H = VIH, L = VIL, X = don't care.
2
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
IDT7187S
Max.
IDT7187L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
CC = Max., VIN = GND to VCC
CC = Max., CS = VIH, VOUT = GND to VCC
OL = 10mA, VCC = Min.
OL = 8mA, VCC = Min.
OH = -4mA, VCC = Min.
Min.
Min.
Max.
5
Unit
µA
µA
V
____
____
|
V
10
10
____
____
____
____
____
____
|
V
5
VOL
I
0.5
0.5
I
0.4
0.4
____
____
VOH
Output High Voltage
I
2.4
2.4
V
2986 tbl 07
DC Electrical Characteristics(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7187S25
7187L25
7187S35
7187L35
7187S45
7187L45
7187S55
7187L55
7187S70
7187L70
7187S85
7187L85
Symbol
Parameter
Power
Unit
ICC1
Operating Power
mA
S
105
105
85
105
105
85
105
85
105
85
Supply Current
CS = VIL, Outputs Open
CC = Max., f =
0(2)
L
85
85
V
I
CC2
Dynamic Operating Current
S
L
130
110
120
100
120
95
120
90
120
90
120
90
mA
mA
CS = VIL, Outputs Open
(2)
V
CC = Max., f = fMAX
I
SB
Standby Power Supply
Current (TTL Level)
S
L
S
L
55
50
20
1.5
50
40
20
1.5
50
35
50
30
20
1.5
50
28
20
1.5
50
28
20
1.5
CS > VIH, Outputs Open
(2)
V
CC = Max., f = fMAX
ISB1
Full Standby Power
mA
20
Supply Current (CMOS Level)
CS > VHC, VCC = Max., VIN < VLC
or VIN > VHC, f = 0(2)
1.5
2986 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
6.42
3
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
DataRetentionCharacteristics
(L Version Only) (VHC = VCC - 0.2V, VLC = 0.2V)
Typ.(1)
Max.
VCC @
V
CC
@
Symbol
Parameter
CC for Data Retention
Test Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
V
____
____
____
____
____
VDR
V
2.0
____
I
CCDR
Data Retention Current
10
15
600
900
µA
ns
(3)
CDR
____
____
____
____
t
Chip Deselect to Data Retention Tim
Operation Recovery Time
Input Leakage Current
0
CS > VHC
V
IN > VHC or <
(3)
(2)
____
____
____
____
____
____
t
R
t
RC
ns
VLC
(3)
____
2
2
µA
IILII
2986 tbl 09
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed, but not tested.
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
VCC
4.5V
4.5V
VDR ≥ 2V
tR
tCDR
CS
VIH
VIH
VDR
2986 drw 04
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
1.5V
See Figures 1 and 2
2986 tbl 10
5V
5V
480Ω
480Ω
DATAOUT
DATAOUT
255Ω
255Ω
30pF*
5pF*
,
,
2986 drw 05
2986 drw 06
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tHZ, tLZ, tWZ and tOW)
*Includes scope and jig capacitances
4
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
AC Electrical Characteristics (VCC = 5.0V ± 10%)
7187S25
7187L25
7187S35/45
7187L35/45
7187S55
7187L55
7187S70
7187L70
7187S85
7187L85
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
Read Cycle
____
____
____
____
____
t
RC
AA
ACS
OH
Read Cycle Time
25
35/45
55
70
85
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
t
Address Access Time
25
35/45
55
70
85
____
____
____
____
____
t
Chip Select Access Time
25
35/45
55
70
85
____
____
____
____
____
t
Output Hold from Address Change
Output Select to Output in Low-Z
Chip Deselect to Output in High-Z
Chip Select to Power Up Time
Chip Deselect to Power Down Time
5
5
5
5
5
(1)
LZ
____
____
____
____
____
t
5
5
5
5
5
(1)
(1)
(1)
____
____
____
____
____
tHZ
12
17/20
30
30
40
____
____
____
____
____
tPU
0
0
0
0
0
____
____
____
____
____
tPD
20
30/35
35
35
40
ns
2986 tbl 11
NOTE:
1. This parameter guaranteed but not tested.
Timing Waveform of Read Cycle No. 1(1,2)
(5)
RC
t
ADDRESS
AA
t
OH
t
OUT
DATA
PREVIOUS DATA VALID
DATA VALID
2986 drw 07
Timing Waveform of Read Cycle No. 2(1,3)
(5)
RC
t
CS
(4)
ACS
tHZ
t
(4)
LZ
t
HIGH
IMPEDANCE
DATA VALID
OUT
DATA
PU
t
PD
t
CC
V
CC
I
SUPPLY
CURRENT
SB
I
2986 drw 08
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.42
5
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
AC Electrical Characteristics (VCC = 5.0V ± 10%)
7187S25
7187L25
7187S35/45
7187L35/45
7187S55
7187L55
7187S70
7187L70
7187S85
7187L85
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
CW
AW
AS
WP
WR
DW
DH
Write Cycle Time
25
20
20
0
35/45
25/40
25/40
0
55
50
50
0
70
55
55
0
85
65
65
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
t
t
t
Write Pulse Width
20
0
20/25
0
35
0
40
0
45
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Data Hold Time
15
15/25
25
30
35
t
5
5
5
5
5
(1)
WZ
____
____
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write
12
15/30
30
30
40
(1)
OW
____
____
____
____
____
t
0
0
0
0
0
ns
2986 tbl 12
NOTE:
1. This parameter guaranteed but not tested.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3,4)
WC
t
ADDRESS
AW
t
CS
WR
WP
t
t
AS
t
WE
(5)
WZ
t
(5)
OW
t
OUT
DATA
DW
t
DH
t
VALID DATA
IN
DATA
2986 drw 09
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
6
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4)
WC
t
ADDRESS
AW
t
CS
(3)
t
AS
tCW
tWR
WE
DW
DH
t
t
VALID DATA
IN
DATA
NOTES:
2986 drw 10
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
OrderingInformation
IDT7187
X
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
,
D
300 mil Ceramic DIP (D22-1)
25
35
45
55
70
85
Speed in nanoseconds
S
L
Standard Power
Low Power
2986 drw 11
6.42
7
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
Datasheet Document History
11/xx/99
Updatedtonewformat
Pp. 1, 2, 8
Pp. 3, 4
Pg. 8
Revisedpackageofferings
Removedcommercialtemperaturedata
AddedDatasheetDocumentHistory
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
08/09/00
02/01/01
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8
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