IDT7187S20DB
更新时间：2024-09-18 18:28:32
品牌：IDT
描述：Standard SRAM, 64KX1, 20ns, CMOS, CDIP22, 0.300 INCH, CERAMIC, DIP-22
概述
规格参数
数据手册IDT7187S20DB 概述
Standard SRAM, 64KX1, 20ns, CMOS, CDIP22, 0.300 INCH, CERAMIC, DIP-22 SRAM
IDT7187S20DB 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | DIP | 包装说明： | 0.300 INCH, CERAMIC, DIP-22 |
| 针数： | 22 | Reach Compliance Code： | not_compliant |
| ECCN代码： | 3A001.A.2.C | HTS代码： | 8542.32.00.41 |
| 风险等级： | 5.89 | Is Samacsys： | N |
| 最长访问时间： | 20 ns | I/O 类型： | SEPARATE |
| JESD-30 代码： | R-GDIP-T22 | JESD-609代码： | e0 |
| 长度： | 27.051 mm | 内存密度： | 65536 bit |
| 内存集成电路类型： | STANDARD SRAM | 内存宽度： | 1 |
| 功能数量： | 1 | 端口数量： | 1 |
| 端子数量： | 22 | 字数： | 65536 words |
| 字数代码： | 64000 | 工作模式： | ASYNCHRONOUS |
| 最高工作温度： | 125 °C | 最低工作温度： | -55 °C |
| 组织： | 64KX1 | 输出特性： | 3-STATE |
| 可输出： | NO | 封装主体材料： | CERAMIC, GLASS-SEALED |
| 封装代码： | DIP | 封装等效代码： | DIP22,.3 |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 并行/串行： | PARALLEL | 电源： | 5 V |
| 认证状态： | Not Qualified | 筛选级别： | 38535Q/M;38534H;883B |
| 座面最大高度： | 5.08 mm | 最大待机电流： | 0.02 A |
| 最小待机电流： | 4.5 V | 子类别： | SRAMs |
| 最大压摆率： | 0.14 mA | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | NO | 技术： | CMOS |
| 温度等级： | MILITARY | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | THROUGH-HOLE | 端子节距： | 2.54 mm |
| 端子位置： | DUAL | 宽度： | 7.62 mm |
| Base Number Matches： | 1 |
IDT7187S20DB 数据手册
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PDF下载IDT7187S
IDT7187L
CMOS STATIC RAM
64K (64K x 1-BIT)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High speed (equal access and cycle time)
— Military: 20/25/35/45/55/70/85ns (max.)
• Low power consumption
• Battery backup operation—2V data retention (L version
only)
The IDT7187 is a 65,536-bit high-speed static RAM
organized as 64K x 1. It is fabricated using IDT’s high-
performance,high-reliabilityCMOStechnology.Accesstimes
as fast as 15ns are available.
Both the standard (S) and low-power (L) versions of the
• JEDEC standard high-density 22-pin ceramic DIP, 22-pin IDT7187 provide two standby modes—ISB and ISB1. ISB
leadless chip carrier
• Produced with advanced CMOS high-performance
technology
• Separate data input and output
• Input and output directly TTL-compatible
• Military product compliant to MIL-STD-883, Class B
provides low-power operation; ISB1 provides ultra-low-power
operation. The low-power (L) version also provides the capa-
bility for data retention using battery backup. When using a 2V
battery, the circuit typically consumes only 30µW.
Ease of system design is achieved by the IDT7187 with full
asynchronous operation, along with matching access and
cycle times. The device is packaged in an industry standard
22-pin, 300 mil ceramic DIP, or 22-pin leadless chip carriers.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
A
A
V
CC
GND
65,536-BIT
MEMORY ARRAY
ROW
SELECT
A
A
A
A
CS
DATAOUT
DATAIN
COLUMN I/O
WE
2986 drw 01
A
A
A
A
A
A
A
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE
MARCH 1996
1996 Integrated Device Technology, Inc.
2986/5
6.2
1
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
PIN CONFIGURATIONS
INDEX
1
22
VCC
A15
A14
A13
A12
A11
A10
A9
A0
A1
A2
A3
22 21
2
2
21
20
1
20
19
18
17
16
15
14
A14
A13
A12
A11
A10
A9
A2
3
4
5
6
7
8
9
3
A3
A4
A5
A6
A7
4
19
18
17
16
15
14
13
12
5
A4
L22-1
6
A5
D22-1
7
A6
A7
DATAOUT
8
A8
DATAOUT
9
10 11 12 13
A8
DATAIN
CS
10
WE
GND
2986 drw 03
11
2986 drw 02
22-PIN LCC
TOP VIEW
DIP
TOP VIEW
TRUTH TABLE(1)
PIN DESCRIPTIONS
Name
A0–A15
CS
Description
Address Inputs
Chip Select
Write Enable
Power
Mode
Standby
Read
Output
Power
Standby
Active
CS
WE
X
H
High-Z
DOUT
L
H
WE
Write
NOTE:
1. H = VIH, L = VIL, X = don't care.
L
L
High-Z
Active
2986 tbl 02
VCC
DATAIN
DATAOUT
GND
Data Input
Data Output
Ground
2986 tbl 01
6.2
2
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, F = 1.0MHZ)
Symbol
Parameter(1)
Conditions Max. Unit
Symbol
Rating
Com’l.
Mil.
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
8
8
pF
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
with Respect
to GND
V
COUT
VOUT = 0V
pF
NOTE:
2986 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
TA
Operating
Temperature
0 to +70
–55 to +125
°C
°C
°C
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135
–55 to +125 –65 to +150
RECOMMENDED DC OPERATING
CONDITIONS
Storage
Temperature
Symbol
Parameter
Min. Typ. Max. Unit
PT
Power Dissipation
1.0
50
1.0
50
W
VCC
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
4.5
0
5.0
0
5.5
0
V
V
V
IOUT
DC Output
Current
mA
GND
VIH
NOTE:
2986 tbl 03
2.2
–0.5(1)
—
—
6.0
0.8
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VIL
V
NOTE:
2986 tbl 05
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
–55°C to +125°C
0°C to +70°C
GND
VCC
Military
0V
5V ± 10%
5V ± 10%
Commercial
0V
2986 tbl 06
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%)
IDT7187S
IDT7187L
Symbol
Parameter
Test Condition
VCC = Max.,
VIN = GND to VCC
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current
MIL.
COM’L.
—
—
10
5
—
—
5
2
µA
|ILO|
VOL
VOH
Output Leakage Current
Output Low Voltage
Output High Voltage
VCC = Max., CS = VIH,
VOUT = GND to VCC
MIL.
COM’L.
—
—
10
5
—
—
5
2
µA
IOL = 10mA, VCC = Min.
IOL = 8mA, VCC = Min.
0.5
0.4
—
—
0.5
0.4
V
—
IOH = –4mA, VCC = Min.
2.4
—
2.4
—
V
2986 tbl 07
6.2
3
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7187S20
7187L20
7187S25
7187L25
7187S35
7187L35
7187S45
7187L45
7187S55/70 7187S85
7187L55/70 7187L85
Symbol
Parameter
Power Com’l. Mil.(3) Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil.
Com’l. Mil.
Unit
ICC1
Operating Power
Supply Current
S
L
—
—
105
85
—
—
105
85
—
—
105
85
—
—
105
85
—
—
105
85
—
—
105
mA
CS = VIL, Outputs Open
85
VCC = Max., f = 0(2)
ICC2
ISB
Dynamic Operating
Current
CS = VIL, Outputs Open
S
L
—
—
140
120
—
—
130
110
—
—
120
100
—
—
120
95
—
—
120
90
—
—
120
90
mA
mA
mA
(2)
VCC = Max., f = fMAX
Standby Power Supply
Current (TTL Level)
CS ≥ VIH, VCC = Max.,
S
L
—
—
65
60
—
—
55
50
—
—
50
40
—
—
50
35
—
—
50
—
—
50
28
30/28
(2)
Outputs Open, f = fMAX
ISB1
Full Standby Power
Supply Current (CMOS
Level) CS ≥ VHC,
S
L
—
—
20
—
—
20
—
—
20
—
—
20
—
—
20
—
—
20
1.5
1.5
1.5
1.5
1.5
1.5
VCC=Max., VIN ≥ VHC or
VIN ≤ VLC, f = 0(2)
NOTES:
2986 tbl 06
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VHC = VCC - 0.2V, VLC = 0.2V
Typ. (1)
VCC @
Max.
VCC @
Symbol
VDR
Parameter
Test Condition
Min.
2.0v
3.0V
2.0V
3.0V
Unit
V
VCC for Data Retention
Data Retention Current
—
2.0
—
—
—
—
ICCDR
MIL.
COM’L.
—
—
10
10
15
15
600
150
900
225
µA
(3)
tCDR
Chip Deselect to Data
Retention Time
CS ≥ VHC
VIN ≥ VHC or ≤ VLC
0
—
—
—
—
ns
(3)
tR
|ILI|(3)
(2)
Operation Recovery Time
Input Leakage Current
tRC
—
—
—
—
—
2
—
2
ns
µA
—
NOTES:
1. TA = +25°C.
2986 tbl 09
2. tRC = Read Cycle Time.
3. This parameter is guaranteed, but not tested.
LOW VCC DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VCC
4.5V
4.5V
VDR ≥2V
tR
tCDR
VIH
CS
VIH
VDR
2986 drw 04
6.2
4
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
1.5V
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
See Figures 1 and 2
2986 tbl 10
5V
5V
480
Ω
480Ω
DATAOUT
DATAOUT
255Ω
255
Ω
30pF*
5pF*
2986 drw 05
2986 drw 06
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tHZ, tLZ, tWZ and tOW)
*Includes scope and jig capacitances
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
7187S20
7187L20
7187S25 7187S35/45
7187L25 7187L35/45
7187S55
(1)
7187S70
7187L70
7187S85
7187L85
7187L55
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
Read Cycle Time
15/20
—
—
5
—
15/20
15/20
—
25
—
—
5
—
25
25
—
—
12
—
20
35/45
—
—
5
—
35/45
35/45
—
55
—
—
5
—
55
55
—
—
30
—
35
70
—
—
5
—
70
70
—
—
30
—
35
85
—
—
5
—
85
85
—
—
40
—
40
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACS
Chip Select Access Time
tOH
Output Hold from Address Change
Output Selection to Output in Low-Z
Chip Deselect to Output in High-Z
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
(2)
tLZ
5
—
5
5
—
5
5
5
(2)
(2)
(2)
tHZ
tPU
tPD
—
0
6
—
0
—
0
17/20
—
—
0
—
0
—
0
—
—
15/20
—
—
30/35
—
—
—
ns
NOTES:
2986 tbl 11
1. –55°C to +125°C temperature range only.
2. This parameter guaranteed but not tested.
6.2
5
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
(1,2)
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
tRC
ADDRESS
tAA
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
2986 drw 07
(1,3)
TIMING WAVEFORM OF READ CYCLE NO. 2
(5)
tRC
CS
(4)
tACS
tHZ
(4)
tLZ
HIGH
DATA VALID
DATAOUT
IMPEDANCE
tPU
tPD
VCC
SUPPLY
CURRENT
ICC
ISB
2986 drw 08
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
7187S20
7187L20
7187S25 7187S35/45
7187L25 7187L35/45
7187S55
7187L55
7187S70
7187L70
7187S85
7187L85
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC
tCW
tAW
tAS
Write Cycle Time
12/15
12/15
12/15
0
—
—
—
—
—
—
—
—
6/8
—
25
20
20
0
—
—
—
—
—
—
—
—
12
—
35/45
25/40
25/40
0
—
—
55
50
50
0
—
—
—
—
—
—
—
—
30
—
70
55
55
0
—
—
—
—
—
—
—
—
30
—
85
65
65
0
—
—
—
—
—
—
—
—
40
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
—
—
tWP
tWR
tDW
tDH
Write Pulse Width
12/15
0
20
0
20/25
0
—
35
0
40
0
45
0
Write Recovery Time
—
Data Valid to End-of-Write
Data Hold Time
8/10
0
15
5
15/25
5
—
25
5
30
5
35
5
—
(2)
tWZ
tOW
Write Enable to Output in High-Z
Output Active from End-of-Write
—
—
0
—
15/30
—
—
0
—
0
—
0
(2)
0
0
ns
NOTES:
2986 tbl 12
1. –55°C to +125°C temperature range only.
2. This parameter guaranteed but not tested.
6.2
6
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
(1,2,3,4)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
CONTROLLED TIMING)
WE
t
WC
ADDRESS
t
AW
CS
tWP
t
WR
t
AS
WE
(5)
t
WZ
(5)
tOW
DATAOUT
t
DW
tDH
DATAIN
VALID DATA
2986 drw 09
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
(1,2,4)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CONTROLLED TIMING)
CS
tWC
ADDRESS
tAW
CS
(3)
tAS
tCW
tWR
WE
tDW
tDH
DATAIN
VALID DATA
2986 drw 10
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
6.2
7
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
ORDERING INFORMATION
IDT
7187
X
X
XX
XXX
Device
Type
Power Speed
Package
Process/
Temperature
Range
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
B
300 mil Ceramic DIP (D22-1)
Leadless Chip Carrier (L22-1)
D
L22
20
25
35
45
55
70
85
Speed in nanoseconds
S
L
Standard Power
Low Power
2986 drw 11
6.2
8
IDT7187S20DB 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| IDT7187S20EB | IDT | Standard SRAM, 64KX1, 20ns, CMOS, CDFP24, 0.300 INCH, CERPACK-24 | 获取价格 |
|
| IDT7187S20F | ETC | x1 SRAM | 获取价格 |
|
| IDT7187S20FB | IDT | Standard SRAM, 64KX1, 20ns, CMOS, CDFP24, FP-24 | 获取价格 |
|
| IDT7187S20L22B | ETC | x1 SRAM | 获取价格 |
|
| IDT7187S20L28B | ETC | x1 SRAM | 获取价格 |
|
| IDT7187S20L28B8 | IDT | Standard SRAM, 64KX1, 20ns, CMOS, CQCC28, LCC-28 | 获取价格 |
|
| IDT7187S20L28BG8 | IDT | Standard SRAM, 64KX1, 20ns, CMOS, CQCC28, LCC-28 | 获取价格 |
|
| IDT7187S20P | IDT | Standard SRAM, 64KX1, 20ns, CMOS, PDIP22, 0.300 INCH, PLASTIC, DIP-22 | 获取价格 |
|
| IDT7187S20SO | ETC | x1 SRAM | 获取价格 |
|
| IDT7187S20SO8 | IDT | Standard SRAM, 64KX1, 20ns, CMOS, PDSO24, 0.300 INCH, SOIC-24 | 获取价格 |
|
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