IDT7188L55DBG [IDT]
Standard SRAM, 16KX4, 55ns, CMOS, CDIP22, 0.300 INCH, CERAMIC, DIP-22;
| 型号： | IDT7188L55DBG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 16KX4, 55ns, CMOS, CDIP22, 0.300 INCH, CERAMIC, DIP-22 存储 静态存储器 |
| 文件： | 总8页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Static RAM
64K (16K x 4-Bit)
IDT7188S
IDT7188L
Features
◆
innovativecircuitdesigntechniques,providesacosteffectiveapproach
formemoryintensiveapplications.
High-speed (equal access and cycle times)
– Military:25/35/45/55/70/85ns(max.)
Low power consumption
Battery backup operation — 2V data retention
◆
Access times as fast as 25ns are available. The IDT7188 offers a
reduced power standby mode, ISB1, which is activated when CS goes
HIGH. This capability significantly decreases power while enhancing
systemreliability.Thelow-powerversion(L)versionalsooffersabattery
backupdataretentioncapabilitywherethecircuittypicallyconsumesonly
30µWoperatingfroma2Vbattery.
AllinputsandoutputsareTTL-compatibleandoperatefromasingle
5V supply. The IDT7188 is packaged in a 22-pin, 300 mil ceramic DIP
providingexcellentboard-levelpackingdensities.
◆
(L version only)
Available in high-density industry standard 22-pin, 300 mil
◆
ceramic DIP
Produced with advanced CMOS technology
Inputs/outputs TTL-compatible
Military product compliant to MIL-STD-883, Class B
◆
◆
◆
Description
The IDT7188 is a 65,536-bit high-speed static RAM organized as
16K x 4. It is fabricated using IDT’s high-performance, high-reliability
technology—CMOS. This state-of-the-arttechnology, combinedwith
Militarygradeproductismanufacturedincompliancewiththelatest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demandingthe highestlevelofperformance
andreliability.
FunctionalBlockDiagram
A0
VCC
GND
65,536-BIT
MEMORY ARRAY
DECODER
A13
I/O0
COLUMN I/O
I/O1
INPUT
DATA
CONTROL
I/O2
I/O3
,
CS
WE
2989 drw 01
FEBRUARY 2001
1
DSC-2989/09
©2000IntegratedDeviceTechnology,Inc.
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
PinConfiguration
AbsoluteMaximumRatings(1)
Symbol
Rating
Value
Unit
V
1
22
CC
13
12
V
A
A
0
1
2
3
4
A
A
A
A
A
VTERM Terminal Voltage with Respect to GND -0.5 to +7.0
2
21
20
TA
TBIAS
TSTG
PT
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-65 to +135
-65 to +150
1.0
oC
oC
oC
W
3
4
19
18
17
16
A11
10
D22-1
5
A
A
6
A5
9
7
IOUT
DC Output Current
50
mA
3
2
1
0
I/O
I/O
I/O
I/O
6
7
8
A
A
A
15
14
13
12
8
2989 tbl 03
NOTE:
9
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
10
11
CS
GND
WE
,
2989 drw 02
DIP
Top View
Capacitance
(TA = +25°C, f = 1.0MHz, VCC = 0V)
Symbol
CIN
Parameter(1 )
Input Capacitance
I/O Capacitance
Conditions
VIN = 0V
Max.
6
Unit
pF
PinDescriptions
CI/O
VOUT = 0V
6
pF
Name
A0 - A13
CS
Description
2989 tbl 04
Address Inputs
Chip Select
Write Enable
Data Input/Output
Power
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
WE
I/O0 - I/O3
VCC
RecommendedDCOperating
Conditions
GND
Ground
Symbol
Parameter
Min.
Typ.
Max. Unit
2989 tbl 01
VCC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND Ground
0
0
Truth Table(1)
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
6.0
0.8
CS
H
L
WE
X
Mode
I/O
Power
-0.5(1)
V
____
Standby
High-Z
DOUT
DIN
Standby
Active
2989 tbl 05
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns,once per cycle.
Read
Write
H
L
L
Active
2989 tbl 02
NOTE:
RecommendedOperating
TemperatureandSupplyVoltage
1. H = VIH, L = VIL, X = don't care.
Grade
Temperature
GND
Vcc
Military
-55OC to +125OC
0V
5V± 10%
2989 tbl 06
2
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
IDT7188S
Min.
IDT7188L
Symbol
|ILI|
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = Max., VIN = GND to VCC
VCC = Max., CS = VIH, VOUT = GND to VCC
IOL = 10mA, VCC = Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
____
____
____
____
____
____
____
____
|ILO|
10
5
VOL
0.5
0.5
IOL = 8mA, VCC = Min.
0.4
0.4
____
____
VOH
Output High Voltage
IOH = -4mA, VCC = Min.
2.4
2.4
V
2989 tbl 07
DCElectricalCharacteristics(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7188S25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Symbol
Parameter
Operating Power
Power
7188L25
Unit
I
mA
CC1
S
105
105
80
105
80
105
80
105
80
105
80
Supply Current
= V , Outputs Open
CS
IL
(2 )
L
80
VCC = Max., f = 0
I
Dynamic Operating Current
mA
mA
CC2
S
L
155
120
140
115
140
110
140
110
140
110
140
105
CS = VIL, Outputs Open
(2 )
VCC = Max., f = fMAX
I
Standby Power Supply
Current (TTL Level)
SB
S
L
S
L
60
40
20
1.5
50
40
20
1.5
50
35
20
1.5
50
35
20
1.5
50
35
20
1.5
50
35
20
1.5
CS > VIH, Outputs Open
(2 )
VCC = Max., f = fMAX
I
Full Standby Power
mA
SB1
Supply Current (CMOS Level)
CS > VHC, VCC = Max., VIN > VHC
(2 )
or VIN < VLC, f = 0
2989 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
6.42
3
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
DataRetentionCharacteristics
(L Version Only) (VHC = VCC - 0.2V)
Typ.(1)
Max.
VCC @
VCC @
Test
Condition
Symbol
Parameter
VCC for Data Retention
Min.
2.0V
3.0V
2.0V
3.0V
Unit
____
____
____
____
____
VDR
CCDR
2.0
V
µA
ns
____
I
Data Retention Current
10
15
600
900
____
____
____
____
(3)
CS > VHC
VIN > VHC or
< VLC
Chip Deselect to Data Retention Time
0
tCDR
____
____
____
____
____
____
(3)
(2)
Operation Recovery Time
Input Leakage Current
ns
tR
tRC
(3)
____
I I
2
2
µA
ILI
2989 tbl 09
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
CC
V
4.5V
4.5V
DR
V
≥ 2V
CDR
R
t
t
IH
IH
,
CS
V
V
DR
V
2989 drw 03
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
1.5V
See Figures 1 and 2
2989 tbl 10
5V
5V
480
Ω
480Ω
DATAOUT
255
OUT
DATA
Ω
30pF*
255Ω
5pF*
,
,
2989 drw 04
2989 drw 05
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tHZ, tLZ, tWZ, tOHZ and tOW)
*Includes scope and jig capacitances
4
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics (VCC = 5.0V ± 10%)
7188S25
7188L25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Symbol
Parameter
Unit
Read Cycle
____
____
____
____
tRC
tAA
tACS
tOH
Read Cycle Time
25
35
—
45
—
55
70
85
ns
ns
ns
ns
ns
____
____
____
____
____
____
Address Access Time
25
35
45
55
70
85
____
____
____
____
____
____
Chip Select Access Time
25
35
45
55
70
85
____
____
____
____
____
____
Output Hold from Address Change
Output Select to Output in Low-Z
5
5
5
5
5
5
____
____
____
____
____
____
(1)
5
5
5
5
5
5
tLZ
(1)
____
____
____
____
____
____
Chip Deselect to Output in High-Z
Chip Select to Power Up Time
Chip Deselect to Power Down Time
10
14
14
20
25
30
ns
ns
tHZ
____
____
____
____
____
____
(1)
0
0
0
0
0
0
tPU
(1)
____
____
____
____
____
____
25
35
45
55
70
85
ns
tPD
2989 tbl 11
NOTE:
1. This parameter is guaranteed by device characterization but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2)
(5)
tRC
ADDRESS
tAA
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
,
2989 drw 06
Timing Waveform of Read Cycle No. 2(1,3)
(5)
tRC
CS
tACS
(4)
tHZ
(4)
tLZ
DATAOUT
DATA VALID
HIGH IMPEDANCE
,
tPU
tPD
ICC
VCC SUPPLY
CURRENT
ISB
2989 drw 07
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state voltage.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.42
5
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics (VCC = 5.0V ± 10%)
7188S25
7188L25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Symbol
Parameter
Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tCW
tAW
tAS
Write Cycle Time
20
20
20
0
30
25
25
0
40
35
35
0
50
50
50
0
60
60
60
0
75
75
75
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
tWP
tWR
tDW
tDH
Write Pulse Width
20
0
25
0
35
0
50
0
60
0
75
0
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
13
15
20
25
30
35
0
0
0
0
0
0
____
____
____
____
____
____
(1)
Write Enable to Output in High-Z
7
10
15
25
30
40
tWZ
____
____
____
____
____
____
(1)
Output Active from End-of-Write
5
5
5
5
5
5
ns
tOW
2989 tbl 12
NOTE:
1. This parameter is guaranteed by device characterization.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3)
tWC
ADDRESS
tAW
1
2
CS , CS
tWP
tWR
tAS
WE
(6)
WZ
t
(6)
tOW
(4)
(4)
DATAOUT
tDW
tDH
,
DATA VALID
DATAIN
2989 drw 08
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
6
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,5)
tWC
ADDRESS
tAW
CS
tAS
tCW
tWR
WE
,
tDW
tDH
DATAIN
DATA VALID
2989 drw 09
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
OrderingInformation
IDT 7188
X
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
,
B
D
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
300 mil Ceramic DIP (D22-1)
25
35
45
55
70
85
Speed in nanoseconds
S
L
Standard Power
Low Power
2989 drw 10
6.42
7
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
DatasheetDocumentHistory
11/xx/99
Updatedtonewformat
Pg. 2, 3, 4
Pg. 8
Removedcommercialtemperaturedata
AddedDatasheetDocumentHistory
Notrecommendedfornewdesigns
08/09/00
02/01/01
Removed"Notrecommendedfornewdesigns"
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8
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