IDT7198L55DB [IDT]
CMOS STATIC RAMs 64K (16K x 4-BIT) Added Chip Select and Output Controls; CMOS静态RAM 64K （ 16K ×4位）增加了芯片选择和输出控制
| 型号： | IDT7198L55DB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS STATIC RAMs 64K (16K x 4-BIT) Added Chip Select and Output Controls |
| 文件： | 总8页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE
INFORMATION
IDT71T016
LOW POWER 2V CMOS SRAM
1 MEG (64K x 16-BIT)
Integrated Device Technology, Inc.
FEATURES:
• 64K x 16 Organization
DESCRIPTION:
The IDT71T016 is a 1,048,576-bit very low-power Static
RAM organized as 64K x 16. It is fabricated using IDT’s high-
reliabilityCMOStechnology. Thisstate-of-the-arttechnology,
combined with innovative circuit design techniques, provides
a cost-effective solution for low-power memory needs. It uses
a 6-transistor memory cell.
Operation is from a single extended-range 2.5V supply.
This extended supply range makes the device ideally suited
for unregulated battery-powered applications. Fully static
asynchronous circuitry is used, requiring no clocks or refresh
for operation.
• Wide Operating Voltage Range: 1.8 to 2.7V
• Speed Grades: 150ns, 200ns
• Low Operating Power: 20mA (max)
• Low Standby Power: 5µA (max)
• Low-Voltage Data Retention: 1.5V (min)
• Available in a 44-pin TSOP package
The IDT71T016 is packaged in a JEDEC standard 44-pin
TSOP Type II.
FUNCTIONAL BLOCK DIAGRAM
Output
Enable
OE
Buffer
Address
Buffers
Row / Column
Decoders
A0 - A15
I/O 15
High
Byte
I/O
Buffer
8
8
Chip
Enable
Buffer
CS
I/O 8
Sense
Amps
and
Write
Drivers
16
64K x 16
Memory
Array
Write
Enable
Buffer
WE
I/O 7
I/O 0
Low
Byte
I/O
8
8
Buffer
BHE
BLE
Byte
Enable
Buffers
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3777 drw 01
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
MAY 1997
1997 Integrated Device Technology, Inc.
DSC-3777/1
1
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A4
A3
1
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2
A6
A2
3
A7
A1
4
OE
A0
5
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
CS
6
I/O 0
I/O 1
I/O 2
I/O 3
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-2
VDD
V
V
SS
DD
VSS
I/O 4
I/O 5
I/O 6
I/O 7
WE
I/O 11
I/O 10
I/O 9
I/O 8
NC
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 1dV
Max. Unit
A15
A14
A13
A12
NC
A8
A9
6
7
pF
A10
A11
NC
CI/O
VOUT = 1dV
pF
NOTE:
3777 tbl 06
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
3777 drw 02
TSOP
TOP VIEW
PIN DESCRIPTIONS
A0 – A15
CS
Address Inputs
Chip Select
Input
Input
Input
Input
Input
Input
I/O
WE
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
Power
OE
BHE
BLE
I/O0 - I/O15
VDD
Pwr
VSS
Ground
Gnd
3777 tbl 01
TRUTH TABLE(1)
I/O0-I/O7
High-Z
I/O8-I/O15
Function
Deselected - Standby
Low Byte Read
High Byte Read
Word Read
CS
H
L
OE
X
L
WE
X
BLE
X
BHE
X
H
L
High-Z
High-Z
H
H
H
L
L
DATAOUT
High-Z
L
L
H
L
DATAOUT
DATAOUT
DATAIN
High-Z
L
L
L
DATAOUT
DATAIN
DATAIN
High-Z
L
X
X
X
H
X
L
L
Word Write
L
L
L
H
L
Low Byte Write
High Byte Write
Outputs Disabled
L
L
H
X
DATAIN
High-Z
L
H
X
X
H
High-Z
L
H
High-Z
High-Z
Outputs Disabled
NOTE:
3777 tbl 02
1.H = VIH, L = VIL, X = Don't care.
2
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
Symbol
Rating
Com’l. and Ind'l.
Unit
TEMPERATURE AND SUPPLY VOLTAGE
(2)
VTERM
Terminal Voltage with
Respect to VSS
–0.5 to +3.6
V
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
VSS
VDD
0V
1.8V to 2.7V
(3)
VTERM
Terminal Voltage with
Respect to VSS
–0.5 to VDD + 0.5
V
0V
1.8V to 2.7V
3777 tbl 04
TBIAS
TSTG
PT
Temperature Under Bias
Storage Temperature
Power Dissipation
–55 to +125
–55 to +125
1.0
°C
°C
RECOMMENDED DC OPERATING
CONDITIONS
W
IOUT
DC Output Current
20
mA
Symbol
Parameter
Supply Voltage
Ground
Min.
1.8
0
Max.
2.7
0
Unit
V
NOTES:
3777 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VDD
VSS
V
VIH
Input High Voltage
Input Low Voltage
VDD x 0.7 VDD + 0.3(1)
–0.3(2)
VDD x 0.3
V
VIL
V
2. VDD terminals only.
3. Input, Output,and I/O terminals; 3.6V maximum.
NOTE:
3777 tbl 05
1. VIH (max.) = VDD + 1.5V for pulse width less than 5ns, once per cycle.
1. VIL (min.) = –1.5V for pulse width less than 5ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VDD = 1.8V to 2.7V, Commercial and Industrial Temperature Ranges
Symbol
|ILI|
Parameter
Test Conditions
Min.
Max.
1
Unit
µA
µA
V
Input Leakage Current
Output Leakage Current
Output High Voltage
VDD = Max., VIN = VSS to VDD
VDD = Max., CS = VIH, VOUT = VSS to VDD
—
—
|ILO|
1
VOH
VDD = 1.8 to 2.7V
VDD = 2.3V
IOH = –0.3mA
IOH = –2.0mA
IOL = 0.3mA
IOL = 2mA
VDD - 0.2
1.7
—
—
VOL
Output Low Voltage
VDD = 1.8 to 2.7V
VDD = 2.3V
—
0.2
0.4
V
—
3777 tbl 07
DC ELECTRICAL CHARACTERISTICS(1, 2)
VDD = 1.8 to 2.7V, VLC = 0.2V, VHC = VDD–0.2V, Commercial and Industrial Temperature Ranges
Symbol
Parameter
Test Conditions
Typ.(5)
Max.
Unit
ICC2
Dynamic Operating Current CS = VLC, Outputs Open,
-70 ns
—
20
17
8
mA
(3)
VDD = 2.7V, f = fMAX
-100 ns
—
ICC
Static Operating Current
Standby Supply Current
CS = VLC, Outputs Open,
WE = VHC, VDD = 2.7V, f = 0(4)
—
mA
ISB1
CS = VHC, Outputs Open,
VDD = 2.7V
-40 to 85°C
0 to 70°C
40°C
—
—
—
—
10
5
µA
2
25°C
1
NOTES:
1. All values are maximum guaranteed values.
3771 tbl 08
2. Input low and high voltage levels are 0.2V and VDD-0.2V respectively for all tests.
3. fMAX = 1/tRC (all address inputs are cycling at fMAX).
4. f = 0 means no address input lines are changing .
5. Typical conditions are VDD = 2.0V and specified temperature.
3
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(VLC = 0.2V, VHC = VDD - 0.2V)
Symbol
VDR
Parameter
Test Condition
Min.
1.5
—
Typ. (1)
—
Max.
—
Unit
V
VCC for Data Retention
Data Retention Current
—
ICCDR
<1
5
µA
ns
(3)
tCDR
Chip Deselect to Data
Retention Time
CS ≥ VHC
0
—
—
(3)
tR
(2)
Operation Recovery Time
tRC
—
—
ns
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3777 tbl 09
3. This parameter is guaranteed by device characterization, but is not production tested.
LOW VDD DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VDD
1.8V
1.8V
VDR ≥ 1.5V
tCDR
tR
VIH
VIH
CS
VDR
3777 drw 05
AC TEST LOAD
AC TEST CONDITIONS
Input Pulse Levels
VDD
GND to VDD
Input Rise/Fall Times
3ns
3070Ω
Input Timing Reference Levels
Output Reference Levels
AC Test Load
VDD x 0.5
VDD x 0.5
See Figure 1
DATAOUT
50pF*
3150Ω
3777 tbl 09
3777 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
4
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 1.8 to 2.7V, All Temperature Ranges)
71T016L150
71T016L200
Symbol
Read Cycle
tRC
Parameter
Min.
Max.
Min.
Max. Units
Read Cycle Time
150
—
—
20
—
—
20
—
15
—
20
—
—
150
150
—
200
—
—
20
—
—
20
—
15
—
20
—
—
200
200
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tACS
Chip Select Access Time
(1)
tCLZ
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
(1)
tCHZ
30
75
—
40
tOE
100
—
(1)
tOLZ
(1)
tOHZ
30
—
40
tOH
tBE
—
75
—
100
—
(1)
tBLZ
(1)
tBHZ
30
40
Write Cycle
tWC
Write Cycle Time
150
120
120
120
0
—
—
—
—
—
—
—
—
—
—
40
200
160
160
160
0
—
—
—
—
—
—
—
—
—
—
50
ns
ns
tAW
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
tCW
ns
tBW
ns
tAS
ns
tWR
Address Hold from End of Write
Write Pulse Width
0
0
ns
tWP
100
60
0
140
80
0
ns
tDW
Data Valid to End of Write
Data Hold Time
ns
tDH
ns
(1)
tOW
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
5
5
ns
(1)
tWHZ
—
—
ns
NOTE:
3777 tbl 10
1. This parameter is guaranteed by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2,3)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
3777 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
5
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1)
tRC
ADDRESS
tAA
tOH
OE
(3)
tOE
tOHZ
(3)
tOLZ
CS
(2)
tACS
(3)
(3)
tCHZ
tCLZ
BHE, BLE
(2)
tBE
(3)
(3)
tBHZ
tBLZ
DATAOUT
DATAOUT VALID
3777 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
CONTROLLED TIMING)(1,2,3,5)
WE
tWC
ADDRESS
tAW
CS
(3)
(6)
(6)
tCW
tCHZ
tBHZ
tBW
BHE, BLE
tWR
tWP
WE
(6)
tAS
tWHZ
(6)
tOW
tDH
PREVIOUS DATA VALID (4)
DATA VALID
DATAOUT
DATAIN
tDW
DATAIN VALID
3777 drw 08
NOTES:
1. WE or (BHE and BLE) or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
3. OEis continuously HIGH. If during a WE controlled write cycle OEis LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW or BHEand BLELOW transition occurs simultaneously with or after the WELOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
6
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CONTROLLED TIMING)(1,2,5)
CS
tWC
ADDRESS
t
AW
CS
(3)
tAS
t
CW
tBW
BHE
,
BLE
WE
tWP
tWR
DATAOUT
DATAIN
t
DW
tDH
DATAIN VALID
3777 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (
,
CONTROLLED TIMING)(1,2,5)
BHE BLE
tWC
ADDRESS
CS
tAW
(3)
t
CW
t
AS
tBW
BHE, BLE
t
WP
tWR
WE
DATAOUT
tDW
tDH
DATAIN
DATAIN VALID
3777 drw 10
NOTES:
1. WE or (BHE and BLE) or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
3. OEis continuously HIGH. If during a WE controlled write cycle OEis LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW or BHEand BLELOW transition occurs simultaneously with or after the WELOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7
IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
L
X
71T016
XXX
XX
IDT
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PH
400-mil TSOP Type II (SO44-2)
Speed in nanoseconds
150
200
3777 drw 11
8
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