IDT71B74S10TP [IDT]
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM; BiCMOS工艺静态RAM 64K （ 8K ×8位） CACHE - TAG RAM
| 型号： | IDT71B74S10TP |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM |
| 文件： | 总9页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71B74
BiCMOS STATIC RAM
64K (8K x 8-BIT)
CACHE-TAG RAM
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed address to MATCH comparison time
— Commercial: 8/10/12/15/20ns (max.)
• High-speed address access time
— Commercial: 8/10/12/15/20ns (max.)
• High-speed chip select access time
— Commercial: 6/7/8/10ns (max.)
• Power-ON Reset Capability
• Low power consumption
— 830mW (typ.) for 12ns parts
— 880mW (typ.) for 10ns parts
— 920mW (typ.) for 8ns parts
The IDT71B74 is a high-speed cache address comparator
subsystem consisting of a 65,536-bit static RAM organized as
8K x 8 and an 8-bit comparator. A single IDT71B74 can map
8Kcachewordsintoa2megabyteaddressspacebyusingthe
21 bits of address organized with the 13 LSBs for the cache
address bits and the 8 higher bits for cache data bits. Two
IDT71B74s can be combined to provide 29 bits of address
comparison, etc. The IDT71B74 also provides a single RAM
clearcontrol,whichclearsallwordsintheinternalRAMtozero
when activated. This allows the tag bits for all locations to be
cleared at power-on or system-reset, a requirement for cache
comparator systems. The IDT71B74 can also be used as a
resettable 8K x 8 high-speed static RAM.
• Produced with advanced BiCMOS high-performance
technology
• Input and output directly TTL-compatible
• Standard 28-pin plastic DIP and 28-pin SOJ (300 mil)
The IDT71B74 is fabricated using IDT’s high-performance,
high-reliabilityBiCMOStechnology. Addressaccesstimesas
fast as 8ns, chip select times of 6ns and address-to-match
times of 8ns are available.
The MATCHpinofseveral IDT71B74scanbewired-ORed
together to provide enabling or acknowledging signals to the
data cache or processor, thus eliminating logic delays and
increasing system throughput.
FUNCTIONAL BLOCK DIAGRAM
VCC
A0
ADDRESS
DECODER
65,536-BIT
MEMORY ARRAY
GND
A12
RESET
8
I/O0 - 7
I/O CONTROL
WE
OE
CS
EQUAL
CONTROL
LOGIC
3013 drw 01
MATCH (OPEN DRAIN)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 1996
1996 Integrated Device Technology, Inc.
DSC-3013/4
14.1
1
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
V
WE
MATCH
A
A
CC
28
27
26
25
24
RESET
2
A
12
3
A
A
A
A
A
7
6
5
4
3
4
8
5
9
P28-2
SO28-5
6
23
22
A11
7
OE
A10
CS
I/O
I/O
I/O
I/O
I/O
8
A2
21
20
9
A
A
I/O
I/O
I/O
1
0
0
1
2
10
11
12
13
14
19
18
17
16
15
7
6
5
4
3
GND
3013 drw 02
DIP/SOJ
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
TRUTH TABLE(1, 2)
MATCH I/O
Function
Symbol
Rating
Com’l.
Unit
WE CS OE RESET
(2)
X
X
H
H
H
X
H
L
L
L
L
X
X
H
H
L
L
HIGH
HIGH
LOW
HIGH
—
Hi-Z
DIN
DIN
Reset all bits to LOW
Deselect chip
No MATCH
MATCH
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
V
H
H
H
H
H
TA
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
0 to +70
–55 to +125
–55 to +125
1.0
°C
°C
°C
W
TBIAS
TSTG
PT
HIGH DOUT
HIGH DIN
Read
L
X
Write
IOUT
DC Output Current
50
mA
NOTES:
3013 tbl 01
1. H = VIH, L = VIL, X = DON'T CARE
NOTES:
3013 tbl 03
2. HIGH = High-Z (pulled up by an external resistor), and LOW = VOL.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTIONS
2. VTERM must not exceed VCC + 0.5V.
Pin Names
Description
A0–12
Address
I/O0-7
CS
Data Input/Output
Chip Select
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ Package)
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
VIN = 3dV
Max. Unit
RESET
MATCH
WE
Memory Reset
Data/Memory Match (Open Drain)
Write Enable
Symbol
CIN
6
7
pF
pF
COUT
VOUT = 3dV
OE
Output Enable
Ground
NOTE:
3013 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
GND
VCC
Power
3013 tbl 02
14.1
2
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Parameter
Min. Typ. Max. Unit
Grade
Ambient Temperature
GND
VCC
VCC
Supply Voltage
4.5
0
5.0
0
5.5
0
6.0(4)
6.0
0.8
V
V
V
V
V
Commercial
0°C to +70°C
0V
5V ± 10%
GND
VIH
Supply Voltage
3013 tbl 06
Input HIGH Voltage(1)
RESET Input Voltage
Input LOW Voltage
2.2
—
—
—
VIHR
VIL
2.5(2)
–0.5(3)
NOTES:
1. All inputs except RESET.
3013 tbl 05
2. When using bipolar devices to drive the RESETinput, a pullup resistor of
1kΩ–10kΩ is usually required to assure this voltage.
3. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
4. VTERM must not exceed VCC + 0.5V.
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
Symbol
Parameter
Dynamic Operating Current
Outputs Open, VCC = Max., f = fMAX
71B74S8
71B74S10 71B74S12 71B74S15 71B74S20 Unit
ICC
WE = VLC
WE = VHC
230
210
210
200
200
170
190
160
180
150
mA
mA
(2)
NOTES:
3013 tbl 07
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only input addresses are cycling at fMAX.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE (VCC = 5.0V ± 10%)
IDT71B74S
Symbol
Parameter
Test Condition
Min.
Max.
Unit
|ILI|
Input Leakage Current
Output Leakage Current
VCC = Max., VIN = GND to VCC
—
—
5
5
µA
µA
|ILO|
VCC = Max., CS = VIH,
VOUT = GND to VCC
VOL
VOH
Output LOW Voltage
Output HIGH Voltage
IOL = 22mA MATCH
—
—
—
—
0.5
0.4
0.5
0.4
V
IOL = 18mA MATCH
IOL = 10mA, VCC = Min. (Except MATCH)
IOL = 8mA, VCC = Min. (Except MATCH)
IOH = –4mA, VCC = Min. (Except MATCH)
2.4
—
V
3013 tbl 08
AC TEST CONDITIONS
Input Pulse Levels
1.5V
GND to 3.0V
3ns
Input Rise/Fall Times
50Ω
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
DATAOUT
1.5V
3013 drw 03
See Figures 1, 2, and 3
3013 tbl 09
Figure 1. AC Test Load
14.1
3
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
7
5V
6
480Ω
∆TADM
(Typical, ns)
5
4
3
2
1
DATAOUT
255Ω
5pF*
3013 drw 05
*Includes scope and jig.
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
3013 drw 04
Figure 1A. Lumped Capacitive Load
Typical Derating Curve
7
6
5
4
3
2
1
∆TAA
(Typical, ns)
5V
RL
MATCH
R
L
= 200
Ω
Ω
(COM’L.)
(MIL.)
= 270
3013 drw 06
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
Figure 3. AC Test Load for MATCH
3013 drw 07
Figure 3A. Lumped Capacitive Load
Typical Derating Curve
32
D0-D31
A0-A31
DATA
DATA
ADDR
32
ADDR
LOGIC 1
13
8
7
8
89
89
8
A17-A24
A25-A31
80486
32-BIT
MICROPROCESSOR
MAIN
MEMORY
IDT71B74
CACHE-
TAG
IDT71B74
CACHE-
TAG
IDT71256 256 256 256
5V
CACHE-
DATA
RAM
A4-A16
RAM
RAM
(2)
RL
CLEAR
RDY
MATCH
MATCH
CACHE READ/WRITE
MEMORY READ/WRITE
CONTROL LOGIC
MAIN MEMORY READ/WRITE
3013 drw 08
NOTES:
1. For more information refer to IDT Application Notes AN-07 and AN-78 and Technical Notes TN-11 and TN-13.
2. RL = 200Ω.
Figure 4. Example of Cache Memory System Block Diagram
14.1
4
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8
71B74S10
71B74S12
71B74S15
71B74S20
Symbol
Read Cycle
tRC
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle Time
8
—
—
2
—
8
10
—
—
2
—
10
7
12
—
—
2
—
12
8
15
—
—
3
—
15
8
20
—
—
3
—
20
10
—
9
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tACS
Chip Select Access Time
6
(1)
tCLZ
Chip Select to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
—
5
—
6
—
6
—
8
tOE
—
2
—
2
—
2
—
2
—
2
(1)
tOLZ
—
4
—
5
—
5
—
7
—
8
(1)
tCHZ
—
—
3
—
—
3
—
—
3
—
—
3
—
—
3
(1)
tOHZ
4
4
5
5
8
tOH
—
—
—
—
—
ns
NOTE:
3013 tbl 10
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
tOH
OE
tOE
(5)
(5)
tOHZ
(5)
tOLZ
CS
(3)
tACS
(5)
tCLZ
tCHZ
DATAOUT
DATAOUT VALID
3013 drw 09
TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4)
t
RC
ADDRESS
DATAOUT
t
AA
t
OH
t
OH
DATAOUT VALID
NOTES:
3013 drw 10
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is continuously active, OE is LOW.
5. Transition is measured ±200mV from steady state.
14.1
5
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8
71B74S10
71B74S12
71B74S15
71B74S20
Symbol
Write Cycle
tWC
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle Time
8
7
—
—
—
—
—
—
5
10
8
—
—
—
—
—
—
5
12
9
—
—
—
—
—
—
5
15
10
10
0
—
—
—
—
—
—
5
20
15
15
0
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Select to End of Write
Address Valid to End of Write
Address Set-up Time
tAW
7
8
9
tAS
0
0
0
tWP
Write Pulse Width
7
8
9
10
0
15
0
tWR
Write Recovery Time (CS, WE)
Write Enable to Output in High-Z
Data Valid to End of Write
Data Hold from Write Time
Output Active from End of Write
0
0
0
(1)
tWHZ
—
5
—
5
—
6
—
8
—
10
0
tDW
tDH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
(1)
tOW
2
2
2
2
2
ns
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
3013 tbl 11
(1, 6)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
Controlled Timing,
HIGH During Write)
OE
WE
tWC
ADDRESS
OE
CS
(3)
tAW
tWR
tAS
WE
(2)
tWP
(8,9)
(9)
tWHZ
tOW
DATAOUT
tDW
t DH
(4,9)
tOHZ
DATA VALID
DATAIN
3013 drw 11
NOTES:
1. WE, CS must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE and a LOW CS.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. OE is continuously HIGH, OE ≥ VIH. If during the WE controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and the data to be placed on the bus for the required tDW. If OEis HIGH during the WE controlled write cycle, this requirement does not
apply and the minimum write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW timing.
7. DATAOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. tWHZ is not included if OEremains HIGH during the write cycle. If OEis LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW.
9. Transition is measured ±200mV from steady state.
14.1
6
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
(1, 6)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 ( Controlled Timing)
CS
tWC
ADDRESS
OE
(3)
(2)
tWR
t CW
(5)
CS
t AW
t AS
WE
(9)
(8,9)
tOW
tWHZ
(7)
DATAOUT
t DW
t DH
DATA VALID
DATAIN
3013 drw 12
NOTES:
1. WE, CS must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE and a LOW CS.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. OE is continuously HIGH, OE ≥ VIH. If during the WE controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and the data to be placed on the bus for the required tDW. If OEis HIGH during the WE controlled write cycle, this requirement does not
apply and the minimum write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW timing.
7. DATAOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. tWHZ is not included if OEremains HIGH during the write cycle. If OEis LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW.
9. Transition is measured ±200mV from steady state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8
71B74S10
71B74S12
71B74S15
71B74S20
Symbol
Match Cycle
tADM
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Address to MATCH Valid
—
—
—
—
—
—
—
2
8
7
—
—
—
—
—
—
—
2
10
7
—
—
—
—
—
—
—
2
12
8
—
—
—
—
—
—
—
2
15
10
8
—
—
—
—
—
—
—
2
20
10
8
ns
ns
ns
ns
ns
ns
ns
ns
tCSM
Chip Select to MATCH Valid
Chip Select to MATCH HIGH
Data Input to MATCH Valid
OE LOW to MATCH HIGH
WE LOW to MATCH HIGH
RESET LOW to MATCH HIGH
MATCH Valid Hold From Address
MATCH Valid Hold From Data
(1)
tCSMHI
7
8
8
tDAM
7
8
10
10
10
10
—
—
12
10
10
12
—
—
12
10
10
15
—
—
(1)
tOEMHI
7
8
(1)
tWEMHI
7
8
(1)
tRSMHI
8
10
—
—
tMHA
tMHD
—
—
2
2
2
2
2
ns
NOTE:
3013 tbl 12
1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
14.1
7
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
MATCH TIMING(1)
ADDRESS
tMHA
tADM
tCSM
CS
(2)
tCSMHI
OE
WE
(2)
tOEMHI
(2)
tWEMHI
RESET
(2)
tRSMHI
VALID MATCH
DATA
DATA
VALID READ DATA
tDAM
tMHD
MATCH
MATCH VALID
MATCH
NO MATCH
3013 drw 13
NOTES:
1. It is not recommended to float data and address input pins while the MATCH pin is active.
2. Transition is measured at ±200mV from steady state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8
71B74S10
71B74S12
71B74S15
71B74S20
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Reset Cycle
(1)
tRSPW
tWERS
tRSRC
Reset Pulse Width
30
5
—
—
—
—
35
5
—
—
—
—
35
5
—
—
—
—
40
5
—
—
—
—
45
5
—
—
—
—
ns
ns
WE HIGH to Reset HIGH
Reset HIGH to WE LOW
Power On Reset
25
100
25
100
25
100
30
120
30
120
ns
(2)
tPORS
ns
NOTES:
3013 tbl 13
1. Recommended duty cycle = 10% maximum.
2. This parameter is guaranteed with the AC Load (Figure 1) by device characterization, but is not production tested.
RESET TIMING
t
RSPW
RESET
WE
t
RSRC
t
WERS
3013 drw 14
14.1
8
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
POWER ON RESET TIMING
tPORS
VCC
RESET
WE
tRSRC
tWERS
3013 drw 15
5V
IDT71B74
RESET
IDT71B74
RESET
1KΩ – 10KΩ
CMOS GATE
BIPOLAR GATE
3013 drw 16
3013 drw 17
Driving the
pin with CMOS logic.
Driving the
pin with bipolar logic.
RESET
RESET
Figure 5.
ORDERING INFORMATION
IDT
71B74
S
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
TP
Y
Plastic DIP (300 mil) (P28–2)
SOJ (Small Outline IC, J-bend) (SO28–5)
8
10
12
15
20
Commercial Only, SOJ Only
Commercial Only
Commercial Only
Commercial Only
Commercial Only
Speed in ns
3013 drw 18
14.1
9
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