IDT71P73204S300BQ [IDT]
Standard SRAM, 2MX8, 0.45ns, CMOS, PBGA165;
| 型号： | IDT71P73204S300BQ |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 2MX8, 0.45ns, CMOS, PBGA165 静态存储器 |
| 文件： | 总24页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance
Information
IDT71P73204
IDT71P73104
IDT71P73804
IDT71P73604
18Mb Pipelined
DDR™II SRAM
Burst of 4
Features
Description
TM
◆
◆
◆
◆
◆
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
Common Read and Write Data Port
Dual Echo Clock Output
4-Word Burst on all SRAM accesses
Multiplexed Address Bus
The IDT DDRII Burst of four SRAMs are high-speed synchronous
memories with a double-data-rate (DDR), bidirectional data port. This
scheme allows maximization on the bandwidth on the data bus by pass-
ing two data items per clock cycle. The address bus operates at single
data rate speeds,allowing the user to fan out addresses and ease system
design while maintaining maximum performance on data transfers.
The DDRII has scalable output impedance on its data output bus and
echo clocks, allowing the user to tune the bus for low noise and high
performance.
-
One Read or One Write request per two clock
cycles.
DDR (Double Data Rate) Data Bus
Four word bursts data per two clock cycles
◆
-
◆
◆
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
All interfaces of the DDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8 sys-
tems if necessary. The device has a VDDQanda separate Vref, allowing
the user to designate the interface operational voltage, independent of
the device core voltage of 1.8V VDD. The output impedance control
allows the user to adjust the drive strength to adapt to a wide range of
loads and transmission lines.
◆
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
-
Output Impedance adjustable from 35 ohms to 70
ohms
◆
◆
◆
1.8V Core Voltage (VDD)
JTAG Interface
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
Clocking
The DDRII SRAM has two sets of input clocks, namely the K, K clocks
and the C, C clocks. In addition, the QDRII has an output “echo” clock,
CQ, CQ.
The K and K clocks are the primary device input clocks. The K
clock is used to clock in the control signals (LD, R/W andBWx or
NWx), the address, and the first and third words of the data burst
during a write operation. The K clock is used to clock in the control
Functional Block Diagram
DATA
REG
(Note1)
WRITE DRIVER
(Note2)
SA
SA
ADD
REG
(Note2)
0
1
SA
(Note4)
(Note4)
(Note1)
18M
MEMORY
ARRAY
DQ
LD
RW
BWx
CTRL
LOGIC
(Note3)
K
CLK
GEN
CQ
K
CQ
C
SELECT OUTPUT CONTROL
C
6431 drw 16
Notes
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x8 and x9, 18 address signal lines for x18, and 17 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
MAY 2004
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
DSC-6431/00
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
four word burst, with their BW/NW enables.
signals (BWx orNWx), and the second and fourth words of the data
burst during a write operation. The K and K clocks are also used
internally by the SRAM. In the event that the user disables the C and
C clocks, the K andK clocks will also be used to clock the data out of
the output register and generate the echo clocks.
DDRII devices internally store four words of the burst as a single,
wide word and will retain their order in the burst. The x8 and x9
devices do not have the ability to address to the single word level or
reverse the burst order; however the byte and nibble write signals
can be used to prevent writing any byte or individual nibbles, or
combined to prevent writing one word of the burst. The x18 and x36
DDRll devices have the ability to address to the individual word level
using the SA0and SA1 address bits, but the burst will continue in a
linear sequence and wrap back on itself. The address will not
increment to the next higher burst address location, but instead will
return to it’s own lower words within the burst location. When reading
x18 and x36 DDRll devices, the read burst will begin at the desig-
nated address, but if the burst is started at any other position than the
first word of the burst, the burst will wrap back on itself and read the
first locations before completing.
The C and C clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the DDRII will be closely aligned to the C and C input,
through the use of an internal DLL. When C is presented to the DDRII
SRAM, the DLL will have already internally clocked the data to arrive at
the device output simultaneously with the arrival of the C clock. The C
and second data item of the burst will also correspond. The third and
fourth data words will follow on the next clock cycle of the C and C,
respectively.
Single Clock Mode
The DDRII SRAM may be operated with a single clock pair. C andC
may be disabled by tying both signals high, forcing the outputs and echo
clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the DDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the SRAM.
With the DLL off, there will be a propagation delay from the time the clock
enters the device until the data appears at the output.
Output Enables
The DDRII SRAM automatically enables and disables the DQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the DQ outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge ofCQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
to it’s lowest value, the ZQ pin may be tied to VDDQ.
The echo clock is very closely aligned with the data, guaranteeing that
the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and C
clocks.
Write operations are initiated by holding the Read/Write control input
(R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the four
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BW orNW) inputs. On the follow-
ing rising edge of K, the second word of the data write burst will be
accepted at the device input withthedesignated(BW or NW) inputs. The
subsequent K and K rising edges will receive the last two words of the
6.242
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
Data I/O s ignals . Data inputs are s ample d on the ris ing e dge of K and
K during valid write ope ratio ns . Data
outp uts are drive n during a valid re ad ope ration. The outputs are aligne d with the ris ing e d ge of both C and
during normal op e ration. Whe n ope rating in a s ingle clo ck mod e (C and tie d high), the outp uts are aligne d
with the ris ing e d ge of both K and Whe n a Re ad ope ration is not initiate d or LD is high (de s e le cte d) d uring
the ris ing e dge of K, DQ[X:O] are automatically drive n to high impe dance afte r any pre vious re ad op e ration in
progre s s comple te s .
2M x 8 -- DQ[7:0]
C
C
K.
Inp ut/Outp ut
Synchronous
DQ[X:0]
2M x 9 -- DQ[8:0]
1M x 18 -- DQ[17:0]
512K x 36 -- DQ[35:0]
Byte Write S e le ct 0, 1, 2, and 3 are active LOW. S ample d o n the ris ing e dge of the K and again on the ris ing
e dge of
K clocks d uring write op e rations . Us e d to s e le ct which byte is writte n into the de vice during the
curre nt po rtion of the write ope ration s . Byte s not writte n re main unalte re d. All the byte write s are s ample d on
the s ame e dge as the d ata. De s e le cting a Byte Write Se le ct will caus e the corre s pond ing b yte of data to be
ig nore d and not writte n in to the de vice .
0
BW BW
,
1
Inp ut
Synchronous
BW , BW
2
3
2M x 9 -- BW
1M x 18 -- BW
512K x 36 -- BW
0
controls DQ[8:0]
controls DQ[8:0] and BW
controls DQ[8:0], BW
0
1
controls DQ[17:9]
0
1
controls DQ[17:9], BW controls DQ[26:18] and BW controls DQ[35:27]
2
3
Nibble Write Se le ct 0 and 1 are active LOW. Available o nly on x8 bit parts ins te ad of Byte Write Se le cts .
Sample d on the ris ing e dge of the K and clocks during write op e rations . Us e d to s e le ct which nibble is
writte n into the de vice during the curre nt portion of the write ope rations . Nib ble s not writte n re main unalte re d.
All the nib ble write s are s ample d on the s ame e dge as the data. De s e le cting a Nib ble Write Se le ct will caus e
the corre s ponding nib ble of data to be ignore d and not writte n in to the de vice .
K
Inp ut
Synchronous
0,
NW NW
1
Inp ut
Synchronous
SA
Add re s s Inputs . Addre s s e s are s amp le d on the ris ing e dge of K cloc k during active re ad or write o pe rations .
Inp ut
Synchronous
Burs t count addre s s bits on x18 and x36 DDRll d e vice s . The s e bits allo w re ve rs ing the burs t orde r in re ad or
write o pe rations , or addre s s ing to the individua l word of a burs t.
0 1
SA , SA
Load Control Log ic . Sample d on the ris ing e dge of K. If LD is low, a four word burst re ad or write ope ration
Inp ut
Synchronous
will initiate de s ignate d by the R/
W input. If LD is high during the ris ing e dg e of K, ope rations in prog re s s will
LD
comple te , but ne w ope rations will not be initiate d .
Re ad or Write Control Log ic. If LD is low during the ris ing e dge of K, the R/
W
ind icate s whe the r a ne w
is low, a write
input will be ignore d.
Inp ut
Synchronous
ope ration s hould be a re ad or write . If R/
W is high, a re ad op e ration will be initiate d, if R/W
R/
W
ope ration will be initiate d. If the LD input is high during the ris ing e dge of K, the R/
W
Pos itive Output Clock Inp ut. C is us e d in conjunction with
and can b e us e d to ge the r to de s ke w the flight time s of various de vice s on the b oard back to the contro lle r.
Se e application e xample for furthe r de tails .
C to clock o ut the Re ad data fro m the de vice . C
C
C
Inp ut Clo c k
Inp ut Clo c k
Ne g ative Output Clock Input.
C is us e d in conjunction with C to clock out the Re ad data fro m the de vice . C
and can b e us e d to ge the r to de s ke w the flight time s of various de vice s on the b oard back to the contro lle r.
C
C
Se e application e xample for furthe r de tails .
Pos itive Input Clock Input. The ris ing e d ge of K is us e d to capture s ynchro no us inputs to the de vice and to
drive out data throug h DQ[X:0] whe n in s ingle clo ck mode . All acce s s e s are initiate d on the ris ing e dge o f K.
K
Input Clock
Inp ut Clo c k
Ne g ativ e In p ut Clo ck Inp ut.
K is us e d to capture s ynchrono us inputs be ing pre s e nte d to the de vice and to
K
drive out data throug h DQ[X:0] whe n in s ingle clock mode .
Synchronous Echo clock outp uts . The ris ing e dge s of the s e outputs are tightly matche d to the s ynchronous
data outputs and can b e us e d as a data valid indication. The s e s ignals are fre e running and do not stop whe n
the output data is thre e s tate d.
CQ, CQ
Output Clock
Output Impe dance Matching Input. This inp ut is us e d to tune the d e vice outp uts to the s ys te m data bus
impe dance . DQ[X:0] o utput impe d ance is s e t to 0.2 x RQ, whe re RQ is a re s is tor conne cte d be twe e n ZQ and
ground. Alte rnate ly, this pin can be conne cte d d ire ctly to VDDQ, which e nable s the minimum impe dance mode .
This pin cannot b e conne c te d dire ctly to GND o r le ft unconne cte d.
ZQ
Input
6431 tbl 02a
6.42
3
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Definitions continued
Symbol Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with
the DLL turned off will be different from those listed in this data sheet. There will be an
increased propagation delay from the incidence of C and C to DQ, or K and K to DQ as
configured. The propagation delay is not a tested parameter, but will be similar to the
propagation delay of other SRAM devices in this speed grade.
Input
Doff
TDO
TCK
TDI
Output
Input
Input
Input
TDO pin for JTAG
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to V when the pin is unconnected.
DD
TMS
NC
TMS pin for JTAG. An internal resistor will pull TMS to V when the pin is unconnected.
DD
No Connect No connects inside the package. Can be tied to any voltage level
Input
Reference Voltage input. Static input used to set the reference level for HSTL inputs and
VREF
Reference Outputs as well as AC measurement points.
Power
Supply
Power supply inputs to the core of the device. Should be connected to a 1.8V power
supply.
VDD
VSS
Ground
Ground for the device. Should be connected to ground of the system.
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply
for HSTL or scaled to the desired output voltage.
VDDQ
6431 tbl 02b
6.442
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Configuration 2M x 8
1
2
3
SA
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
SA
4
5
6
7
8
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
VSS/
R/W
SA
NC
VSS/
CQ
NC
NC
NC
NC
NC
NC
NW1
NC
K
L/D
A
B
C
D
E
F
SA (2)
SA (1)
NW0
NC
NC
K
SA
NC
NC
VSS
SA
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
NC
NC
G
H
J
VREF
NC
VREF
DQ1
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
DQ0
NC
NC
NC
TDI
NC
K
L
DQ6
NC
NC
NC
M
N
P
R
NC
VSS
VSS
NC
NC
SA
SA
SA
SA
NC
TCK
SA
SA
SA
SA
TMS
C
6431 tbl 12
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Configuration 2M x 9
1
2
3
SA
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
SA
4
5
6
K
7
8
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
VSS/
R/W
SA
NC
NC
VSS/
CQ
NC
NC
NC
NC
NC
NC
LD
A
B
C
D
E
F
SA (2)
SA (1)
NC
NC
NC
K
SA
NC
NC
BW
SA
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
NC
NC
G
H
J
VREF
NC
VREF
DQ1
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
DQ0
NC
NC
NC
K
L
DQ6
NC
NC
NC
M
N
P
R
NC
VSS
VSS
NC
NC
SA
SA
SA
NC
DQ
8
TCK
SA
SA
SA
TMS
TDI
C
6431 tbl 12a
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.642
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Configuration 1M x 18
1
CQ
NC
2
3
4
5
6
K
7
8
9
10
11
VSS/
SA
R/W
NC
SA
Vss/
CQ
BW1
NC
LD
SA
A
B
C
D
E
F
SA (2)
SA (1)
DQ
NC
NC
SA
VSS
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
DQ
8
9
BW0
NC
NC
NC
NC
NC
NC
NC
NC
SA
VSS
VSS
SA
SA
VSS
VSS
DQ
7
NC
NC
0
1
DQ
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
NC
10
DQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ
6
11
DQ
NC
V
DD
V
SS
NC
DQ
5
12
NC
VREF
NC
DQ
VDD
VDD
VDD
VDD
VSS
VSS
VSS
NC
NC
ZQ
NC
13
G
H
J
VDDQ
NC
VREF
Doff
NC
NC
NC
NC
NC
NC
TDO
DQ
4
NC
DQ
V
SS
NC
NC
DQ
3
14
K
L
DQ
NC
V
SS
V
SS
DQ
2
15
NC
NC
VSS
SA
SA
SA
VSS
SA
C
DQ
NC
NC
1
M
N
P
R
NC
NC
DQ
VSS
VSS
NC
NC
16
DQ
SA
SA
SA
DQ
0
17
TCK
SA
SA
SA
SA
TMS
TDI
C
6431 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to VSS.on the 1M x 18 DDRII Burst of 4 (71P73804) devices.
2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 4 (71P73804) devices.
6.42
7
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Pin Configuration 512K x 36
1
2
3
4
5
6
7
8
9
10
11
CQ
VSS/
SA (3)
NC/
SA(1)
R/W
SA
SA
NC
NC
NC
NC
NC
NC
VSS/
SA (2)
CQ
NC
NC
NC
NC
NC
NC
BW2
BW3
SA
K
BW1
BW0
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
LD
A
B
C
D
E
F
DQ27
NC
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
K
SA
NC
DQ17
NC
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
DQ29
NC
VSS
VSS
VSS
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ15
NC
DQ30
DQ31
NC
G
H
J
V
REF
V
V
DD
V
V
REF
DDQ
DDQ
NC
NC
NC
NC
NC
NC
SA
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
VDD
VDD
VSS
VSS
SA
SA
SA
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
DQ33
NC
DQ11
NC
M
N
P
R
DQ35
NC
VSS
VSS
SA
SA
SA
DQ9
TMS
TCK
SA
SA
SA
C
6431 tbl 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A3 is reserved for the 36Mb expansion address
2. A10 is reserved for the 72Mb expansion address.
3. A2 is reserved for the 144Mb expansion address.
6.842
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Write Descriptions(1,2)
Signal
BW0
L
BW1
X
BW2
X
BW3
X
NW0
X
NW1
X
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
Write Nibble 0
Write Nibble 1
X
L
X
X
X
X
X
X
L
X
X
X
X
X
X
L
X
X
X
X
X
X
L
X
X
X
X
X
X
L
6431 tbl 09
NOTES:
1) All byte write (BWx) and nibble write (NWx) signals are sampled on the
rising edge of K and again on K. The data that is present on the data bus in the
designated byte/nibble will be latched into the input if the corresponding BWx or
NWx is held low. The rising edge of K will sample the first and third bytes/
nibbles of the four word burst and the rising edge of K will sample the second
and fourth bytes/nibbles of the four word burst.
2) The availability of the BWx or NWx on designated devices is described in
the pin description table.
3) The DDRII Burst of four SRAM has data forwarding. A read request that is
initiated on the cycle following a write request to the same address will produce
the newly written data in response to the read request.
Linear Burst Sequence Table (1,2)
a
SA [1:0]
b
d
c
00
01
10
11
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
NOTES:
6431 tbl 22
1. SA [1:0] is the address presented on pins SA1 and SA0 giving the burst sequence a,b,c,d.
2. SA0 and SA1 are only available on the x18 and x36-bit devices.
6.42
9
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Application Example
SRAM #1
SRAM #4
Ω
R=250
Ω
R=250
ZQ
DQ
ZQ
DQ
K
t
V
1
BW0 BW
LD R/W
SA
C
K
SA
C
K
C K
C
LD R/W
BW1
BW0
R
V
t
D ata Bus
Address
R
t
V
R
t
V
LD
R
R
R
R /
BWx NWx
/
W
M EM O RY
CO NTRO LLER
R eturn CLK
S ource C LK
t
V
R eturn CLK
S ource CLK
t
V
Vt
REF
=V
Ω
R =50
6431 drw 20
61.402
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Absolute Maximum Ratings(1)(2)
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Symbol
Rating
Value
Unit
Symbol
Parameter
Conditions
Max.
Unit
VTERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
V
CIN
Input Capacitance
5
6
7
pF
VDD = 1.8V
VDDQ = 1.5V
CCLK
CO
Clock Input Capacitance
Output Capacitance
pF
VTERM
VTERM
VTERM
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD+0.3
–0.5 to VDD+0.3
–0.5 to VDDQ+0.3
V
V
V
pF
Voltage on Input terminals with
respect to GND
6431 tbl 06
NOTE:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
Voltage on Input, Output and I/O
terminals with respect to GND
TBIAS
TSTG
IOUT
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
+ 20
°C
°C
Continuous Current into Outputs
mA
6431 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDDQ must not exceed VDD during normal operation.
Recommended DC Operating and
Temperature Conditions
DD
DDQ
SS
REF
DDQ
o
A
(1)
6431 tbl 04
NOTE:
1. During production testing, the case temperature equals the ambient
temperature.
6.42
11
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
= Max V = V to V
DDQ
Min
Max
Unit
Note
µA
Input Leakage Current
Output Leakage Current
I
IL
V
DD
-10
-10
+10
+10
IN
SS
Output Disabled
µA
I
OL
333MH
-
-
-
-
-
-
-
-
-
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Z
300MH
Z
V
= Max,
= 0mA (outputs open),
DD
Operating Current
(x36,x18,x9,x8): DDR
IDD
I
250MH
mA
1
OUT
Z
Cycle Time > t
Min
KHKH
200MHz
167MHz
333MH
Z
300MH
Z
Device Deselected (in
state),
NOP
I
= 0mA (outputs open),
OUT
Standby Current: NOP
I
250MH
mA
2
SB1
Z
f=Max,
All Inputs <0.2V or > VDD -0.2V
200MHz
167MHz
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
RQ = 250Ω, I = -15mA
V
/2-0.12
V
/2+0.12
/2+0.12
V
V
V
V
3,7
4,7
5
OH
DDQ
DDQ
V
OH1
RQ = 250Ω, I = 15mA
V
DDQ
/2-0.12
V
DDQ
OL
V
OL1
I
= -0.1mA
= 0.1mA
V
-0.2
DDQ
V
OH
DDQ
0.2
V
OH2
I
OL
V
SS
6
V
OL2
6431 tbl 10c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
61.422
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTES
1,2
Input High Voltage, DC
Input Low Voltage, DC
Input High Voltage, AC
Input Low Voltage, AC
V
)
V
+0.1
V
+0.3
V
IH (DC
REF
DDQ
V
IL (DC)
-0.3
+0.2
V
-0.1
-0.2
V
1,3
REF
V
IH (AC)
V
-
V
4,5
4,5
REF
V
IL (AC)
-
V
V
REF
6431 tbl 10d
NOTES:
1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))
3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))
4. This conditon is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Undershoot Timing
Overshoot Timing
20% tKHKH (MIN)
VIH
VDD +0.5
VDD +0.25
VSS
DD
V
VSS-0.25V
V -0.5V
SS
VIL
6431 drw 22
6431 drw 21
20% tKHKH (MIN)
AC Test Conditions
AC Test Load
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
Symbol
Value
1.7-1.9
1.4-1.9
1.25/0.25
Unit
DD
V
V
V
V
V
ns
DDQ
V
V
DDQ/2
IH IL
V /V
R EF
V
OUTPUT
DDQ
Input Reference Level
VREF
TR/TF
V
/2
Ω
=50
Z0
Input Rise/Fall Time
0.3/0.3
Device
Under
Test
Ω
R = 50
L
DDQ
Output Timing Reference Level
V
/2
V
Ω
Q
= 250
R
ZQ
DD Q
V
/2
6431 tbl 11a
NOTE:
1. Parameters are tested with RQ=250Ω
6431 drw 04
1.25V
0.75V
0.25V
6431 drw 06
6.42
13
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, TA =0 to 70°C )(3,8)
333MHz
300MHz
250MHz
200MHz
167MHz
Min.
Max
Min.
Max
Min.
Max
Min.
Max
Min.
Max
Symbol
Param eter
Unit
Notes
Clock Parameters
t
KHKH
KC var
KHKL
Average clock cycle time (K
,
K
,C,C)
,C,
3.00
-
3.47
3.30
-
5.25
4.00
-
6.30
5.00
-
7.88
6.00
-
8.40
ns
ns
t
Cycle to Cycle Period Jitte r (K,
K
C)
0.20
0.20
0.20
0.20
0.20
1,5
9
K
C
)
t
Clock High Time (K, ,C,
Clock LOW Time (K, ,C,
Clock to clock (K ,C
Clock to clock K,
Clock to data clock (K
1.20
1.20
1.35
1.35
0.00
1024
30
-
1.32
1.32
1.49
1.49
0.00
1024
30
-
1.60
1.60
1.80
1.80
0.00
1024
30
-
2.00
2.00
2.20
2.20
0.00
1024
30
-
2.40
2.40
2.70
2.70
0.00
1024
30
-
ns
t
KLKH
KH
HKH
KHCH
KC lock
KC re s et
K
C
)
-
-
-
-
-
ns
9
t
K
H
→
K
→
C
)
-
-
-
-
-
ns
10
10
tK
(K
→
C
→
C)
-
-
-
-
-
ns
t
→
C,
K
→
C)
1.30
1.45
1.80
2.30
2.80
ns
t
DLL lock time (K, C)
K static to DLL re set
-
-
-
-
-
-
-
-
-
-
cycle s
ns
2
t
Output Parameters
t
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
Set-Up Times
AV KH
IV KH
DVKH
Hold Times
KHAX
KHIX
KHDX
C,
C,
C,
C,
C
C
C
C
HIGH to o utp ut valid
HIGH to o utput hold
-
0.45
-
0.45
-
0.45
-
-0.45
-
0.45
-
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
t
-0.45
-
-
0.45
-
-0.45
-
-
0.45
-
-0.45
-
-
0.45
-
-
0.45
-
-0.50
-
-
0.50
-
t
HIGH to e cho clock valid
HIGH to e cho clock hold
t
-0.45
-
-0.45
-
-0.45
-
-0.45
-
-0.50
-
t
CQ,CQ HIGH to o utput valid
CQ,CQ HIGH to o utput hold
C HIGH to output High-Z
C HIGH to output Low-Z
0.25
-
0.27
-
0.30
-
0.35
-
0.40
-
t
-0.25
-
-0.27
-
-0.30
-
-0.35
-
-0.40
-
t
0.45
-
0.45
-
0.45
-
0.45
-
0.50
-
3,4,5
3,4,5
t
-0.45
-0.45
-0.45
-0.45
-0.50
t
Address valid to K,
Control inputs valid to K, rising e dge
D ate -in valid to K, rising e dge
K
rising e dge
0.40
0.40
0.30
-
-
-
0.40
0.40
0.30
-
-
-
0.50
0.50
0.35
-
-
-
0.6
0.6
-
-
-
0.7
0.7
-
-
-
ns
ns
ns
6
7
K
t
t
K
0.40
0.50
t
K,
K,
K,
K
K
rising e dge to addre ss hold
rising edge to control inputs hold
0.40
0.40
0.30
-
-
-
0.40
0.40
0.30
-
-
-
0.50
0.50
0.35
-
-
-
0.6
0.6
-
-
-
0.7
0.7
-
-
-
ns
ns
ns
6
7
t
t
K
rising edge to data-in hold
0.40
0.50
6431 tbl 11
NOTES:
1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65 (EIA/JESD65) pg.10
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. Control signals are R, W,BW0,BW1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36)
8. During production testing, the case temperature equals TA.
9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of hte cycle time (tKHKH).
10. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
61.442
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles
W rite A 3
(b u rst of 4 )
10
R ea d A 4
(b u rs t o f 4 )
N O P
R e ad A 0
(b urs t o f 4 )
W rite A 2
(b urs t o f 4 )
8
R ea d A 1
(bu rst o f 4)
4
N O P
N O P
(N o te 1 )
7
11
13
9
12
1
3
6
2
5
K
tKH KL
K
tK L KH
K
Note
2
LD
Note
1
W
A3
A 2
A 1
A4
A 0
SA
tK HD X
Q 02
Q 03
Q13
Q x 3
Q 01
Q00
Q0
Q1
D 33
Q12
D 2 0
D 3 0
D 3 2
Q40
D 2 3
D 3 1
D 22
DQ
D 2 1
tKHCH
tCHQV
tCQHQV
tCQHQX
tCHQ V
tCHQX1
tKHCH
tCHQX
tCHQX
tCHQZ
C
tKHKH
tKHKH
tKLKH
tKHKL
C
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
6431 drw 09
NOTE:
1. If R/W is low on the second rising edge of K after a Read request, the device automatically performs a NOP (No Operation.)
2. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent bus
contention.
6.42
15
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry
when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the
SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that
resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable
the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI
are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0
Instruction
EXTEST
TDO Output
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Boundary Scan Register
Identification register
Boundary Scan Register
Do Not Use
IDCODE
2
1
5
4
5
5
SAMPLE-Z
RESERVED
SRAM
CO RE
SAMPLE/PRELOAD Boundary Scan register
RESERVED
RESERVED
BYPASS
Do Not Use
Do Not Use
TDI
BYPASS Reg.
TDO
Bypass Register
3
Identification Reg.
6431 tbl 13
Instruction Reg
Control Signal
TAP Controller
.
NOTES:
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
s
TMS
TCK
3. Bypass register is initialized to Vss when BYPASS instruction is invoked.
The Bypass Register also holds serially loaded TDI when existing the Shift DR
states.
6431 drw 18
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
1
0
1
1
1
Select IR
0
Run Test Idle
Select DR
0
0
1
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
0
1
Exit 1 DR
0
Exit 1 IR
0
Pause DR
1
Pause IR
1
0
0
0
Exit 2 DR
1
Exit 2 IR
1
0
1
Update DR
0
Update IR
1
6431 drw 17
61.462
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Scan Register Definition
Part
Instrustion Register
Bypass Register
ID Register
32 bits
Boundry Scan
107 bits
512Kx36
1Mx18
3 bits
3 bits
3 bits
1 bit
1 bit
1 bit
32 bits
107 bits
2Mx8/x9
32 bits
107 bits
6431 tbl 14
Identification Register Definitions
INSTRUCTION FIELD
Revision Number (31:29)
Device ID (28:12)
ALL DEVICES
DESCRIPTION
Revision Number
PART NUMBER
000
0 0000 0010 0101 0000 512Kx36
0 0000 0010 0101 0001 1Mx18
0 0000 0010 0101 0010 2Mx9
0 0000 0010 0100 0011 2Mx8
DDRII BURST OF 4
71P73604S
71P73804S
71P73104S
71P73204S
IDT JEDEC ID CODE (11:1)
000 0011 0011
1
Allows unique identification of SRAM
vendor.
ID Register Presence
Indicator (0)
Indicates the presence of an ID register.
6431 tbl 15
6.42
17
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Boundary Scan Exit Order (2M x 8-Bit, 2M x 9-Bit)
ORDER
1
PIN ID
6R
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
9E
ORDER
73
PIN ID
3E
2C
1D
2E
1E
2F
2
6P
74
3
6N
10C
11D
9C
75
4
7P
76
5
7N
77
6
7R
9D
78
7
8R
11B
11C
9B
79
3F
8
8P
80
2G
3G
1F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
Internal
9A
82
83
1G
1J
84
85
2J
10M
11N
9M
9N
8B
86
3K
3J
7C
87
6C
88
3L
2L
1K
2K
1M
1L
3N
3M
2N
3P
8A
89
7A
11L
11M
9L
90
7B
91
6B
92
6A
10L
11K
10K
9J
93
5B
94
5A
95
4A
96
5C
9K
97
4B
10J
11J
98
2M
1N
2P
3A
99
2A
11H
10G
9G
100
101
102
103
104
105
106
107
1A
1P
2B
3R
4R
4P
3B
11F
11G
9F
1C
1B
5P
3D
10F
11E
10E
5N
5R
3C
2D
6431 tbl 18a
6431 tbl 17a
6431 tbl 16a
61.482
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Boundary Scan Exit Order (1M x 18-Bit)
ORDER
1
PIN ID
6R
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
9E
ORDER
73
PIN ID
2C
3E
2D
2E
1E
2F
2
6P
74
3
6N
75
10C
11D
9C
4
7P
76
5
7N
77
78
6
7R
9D
79
3F
7
8R
11B
11C
9B
80
1G
1F
8
8P
81
9
9R
82
3G
2G
1J
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
Internal
9A
83
84
85
2J
86
3K
3J
10M
11N
9M
9N
8B
87
7C
88
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
6C
89
8A
90
11L
11M
9L
7A
91
7B
92
6B
93
10L
11K
10K
9J
6A
94
5B
95
5A
96
4A
97
9K
5C
98
10J
11J
4B
99
2N
2P
3A
100
101
102
103
104
105
106
107
11H
10G
9G
1H
1P
1A
3R
4R
4P
2B
11F
11G
9F
3B
1C
5P
1B
5N
5R
10F
11E
10E
3D
6431 tbl 18
3C
1D
6431 tbl 16
6431 tbl 17
6.42
19
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Boundary Scan Exit Order (512K x 36-Bit)
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
10E
11C
9D
ORDER
73
PIN ID
3C
3E
1E
2E
2D
3F
ORDER
PIN ID
1
6R
74
2
6P
75
3
6N
76
4
7P
77
9C
5
7N
78
11D
11B
10B
9B
6
7R
79
1F
7
8R
80
1G
2F
8
8P
81
9
9R
82
3G
2J
10C
11A
Internal
9A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
9P
83
84
1J
10N
10P
11M
9N
85
2G
3K
1K
2K
3J
86
8B
87
7C
88
6C
9M
11N
11L
10L
9L
89
8A
90
3L
1L
1M
2L
3N
2M
1N
3M
3P
7A
91
7B
92
6B
93
6A
10M
11K
9K
94
5B
95
5A
96
4A
9J
97
5C
10K
11J
9G
98
4B
99
1P
3A
100
101
102
103
104
105
106
107
2P
1H
11H
10G
10J
11F
10F
9F
2N
3R
4R
4P
1A
3B
1B
1C
5P
2B
5N
5R
3D
11G
11E
9E
2C
6431 tbl 18b
1D
6431 tbl 17b
6431 tbl 16b
62.402
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
JTAG DC Operating Conditions
Paramete r
Symbol
Min
1.4
1.7
1.3
-0.3
Ty p
Max
1.9
Unit
V
Note
Output Powe r Supply
V
DDQ
DD
IH
IL
OH
OL
-
1.8
-
Powe r Supply Voltage
Input High Le ve l
V
1.9
V
V
VDD+0.3
0.5
V
Input Low Le ve l
V
-
V
1
Output High Voltage (IOH =-1mA)
V
V
DDQ - 0.2
-
V
DDQ
V
1
Output Low Voltage (IOL = 1mA)
V
V
SS
-
0.2
V
NOTE:
6431 tbl 1 9
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter
Symbol
VIH/VIL
TR/TF
Min
Unit
V
Note
1
Input High/Low Level
1.3/0.5
1.0/1.0
VDDQ/2
Input Rise/Fall Time
ns
Input and Output Timing Reference Level
V
6431 tbl20
NOTE:
1. See AC test load on page 12.
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
CHCH
t
TCK Cycle Time
-
-
CHCL
t
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
CLCH
t
-
MVCH
t
-
CHMX
t
5
-
DVCH
t
TDI Input Setup Time
5
-
CHDX
t
TDI Input Hold Time
5
-
SVCH
t
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
-
CHSX
t
5
-
CLQV
t
0
10
6431 tbl.21
JTAG Timing Diagram
TCK
tC H CH
tCH CL
tC HM X
tC LCH
tMV C H
TMS
tD V CH
tC HD X
TDI/
SRA M
Inputs
tSV CH
tC H SX
S RAM
Outp uts
tC LQ V
TDO
6431 drw 19
6.42
21
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
62.422
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Advance Information
Commercial Temperature Range
Ordering Information
IDT
71P73XXX
S
XXX
BQ
Device
Type
Power Speed
Package
BQ
165 Fine Pitch Ball Grid Array (fBGA)
Clock Frequency in MegaHertz
333
300
250
200
167
IDT71P73204 2M x 8 DDR II SRAM Burst of 4
IDT71P73104 2M x 9 DDR II SRAM Burst of 4
IDT71P73804 1M x 18 DDR II SRAM Burst of 4
IDT71P73604 512K x 36 DDR II SRAM Burst of 4
6431 drw 15
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
sramhelp@idt.com
800-544-7726
www.idt.com
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
6.42
23
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18 x -Bit) 71P73604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Revision History
REVISION
DATE
PAGES
DESCRIPTION
Initial Advance Information Data Sheet Release
0
05/31/04
1-23
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