IDT71T024 [IDT]
LOW POWER 2V CMOS SRAM 1 MEG (128K x 8-BIT); 低功耗2V CMOS SRAM 1 MEG （ 128K ×8位）
| 型号： | IDT71T024 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LOW POWER 2V CMOS SRAM 1 MEG (128K x 8-BIT) |
| 文件： | 总8页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE
INFORMATION
IDT71T024
LOW POWER 2V CMOS SRAM
1 MEG (128K x 8-BIT)
Integrated Device Technology, Inc.
FEATURES:
• 128K x 8 Organization
DESCRIPTION:
The IDT71T024 is a 1,048,576-bit very low-power Static
RAM organized as 128K x 8. It is fabricated using IDT’s high-
reliabilityCMOStechnology. Thisstate-of-the-arttechnology,
combined with innovative circuit design techniques, provides
a cost-effective solution for low-power memory needs. It uses
a 6-transistor memory cell.
Operation is from a single extended-range 2.5V supply.
This extended supply range makes the device ideally suited
for unregulated battery-powered applications. Fully static
asynchronous circuitry is used, requiring no clocks or refresh
for operation.
• Wide Operating Voltage Range: 1.8V to 2.7V
• Speed Grades: 150ns, 200ns
• Low Operating Power: 11mA (max)
• Low Standby Power: 5µA (max)
• Low-Voltage Data Retention: 1.5V (min)
• Available in 32-pin, 13.4mm x 8mm Type I TSOP pack-
age
The IDT71T024 is packaged in a JEDEC standard 32-pin
TSOP Type I.
FUNCTIONAL BLOCK DIAGRAM
A0
•
•
•
•
1,048,576-BIT
MEMORY ARRAY
ADDRESS
DECODER
•
•
A16
8
8
I/O0 – I/O7
I/O CONTROL
8
WE
CONTROL
LOGIC
OE
CS1
CS2
3779 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
MAY 1997
1997 Integrated Device Technology, Inc.
DSC-3779/1
1
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A13
WE
CS2
A15
VDD
NC
A16
A14
A12
A7
TSOP (I)
9
10
11
12
13
14
15
16
A6
A5
A4
A1
A2
A3
3779 drw 02
TSOP
TOP VIEW
TRUTH TABLE(1)
PIN DESCRIPTIONS
CS2
I/O0-I/O7
Function
Deselected - Standby
Deselected - Standby
Read
CS1
H
OE
X
WE
X
A0 – A16
CS1
Address Inputs
Chip Select
Input
Input
Input
Input
Input
I/O
X
High-Z
High-Z
X
L
X
X
CS2
Chip Select
L
H
L
H
DATAOUT
DATAIN
High-Z
WE
Write Enable
Output Enable
OE
L
H
X
L
Write
I/O0 - I/O7
VDD
Data Input/Output
Power
L
H
H
H
Outputs Disabled
NOTE:
3779 tbl 02
Pwr
1.H = VIH, L = VIL, X = Don't care.
VSS
Ground
Gnd
3779 tbl 01
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 1dV
Max. Unit
6
7
pF
CI/O
VOUT = 1dV
pF
NOTE:
3779 tbl 06
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
2
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
Symbol
Rating
Com’l. and Ind'l.
Unit
TEMPERATURE AND SUPPLY VOLTAGE
(2)
VTERM
Terminal Voltage with
Respect to VSS
–0.5 to +3.6
V
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
VSS
VDD
0V
1.8V to 2.7V
(3)
VTERM
Terminal Voltage with
Respect to VSS
–0.5 to VDD+0.5V
V
0V
1.8V to 2.7V
3779 tbl 04
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
Power Dissipation
–55 to +125
–55 to +125
1.0
°C
°C
PT
W
RECOMMENDED DC OPERATING
CONDITIONS
IOUT
DC Output Current
20
mA
NOTES:
3779 tbl 03
Symbol
Parameter
Supply Voltage
Ground
Min.
1.8
0
Max.
Unit
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VDD
2.7
VSS
0
V
VIH
Input High Voltage
Input Low Voltage
VDD x 0.7 VDD + 0.3(1)
–0.3(2)
VDD x 0.3
V
VIL
V
2. VDD terminals only.
3. Input, Output,and I/O terminals; 3.6V maximum.
NOTE:
3779 tbl 05
1. VIH (max.) = VDD + 1.5V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –1.5V for pulse width less than 5ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VDD = 1.8V to 2.7V, Commercial and Industrial Temperature Ranges
Symbol
|ILI|
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Test Conditions
Min.
—
Max.
1
Unit
µA
µA
V
VDD = Max., VIN = VSS to VDD
|ILO|
VDD = Max., CS = VIH, VOUT = VSS to VDD
—
1
VOH
VDD = 1.8 to 2.7V
VDD = 2.3 to 2.7V
VDD = 1.8 to 2.7V
VDD = 2.3 to 2.7V
IOH = –0.3mA
IOH = –2mA
IOL = 0.3mA
IOL = 2mA
VDD - 0.2
1.7
—
—
VOL
Output Low Voltage
—
0.2
0.4
V
—
3779 tbl 07
DC ELECTRICAL CHARACTERISTICS(1, 2)
VDD = 1.8 to 2.7V, VLC = 0.2V, VHC = VDD–0.2V, Commercial and Industrial Temperature Ranges
Symbol
Parameter
Test Conditions
Typ.(5)
Max.
Unit
ICC2
Dynamic Operating Current CS1 = VLC, CS2 = VHC, Outputs Open,
-70 ns
—
11
9
mA
(3)
VDD = 2.7V, f = fMAX
-100 ns
—
ICC
Static Operating Current
Standby Supply Current
CS1 = VLC, CS2 = VHC, Outputs Open,
WE = VHC, VDD = 2.7V, f = 0(4)
—
4
mA
ISB1
CS1 and CS2 = VHC, or CS2 = VLC,
Outputs Open, VDD = 2.7V
-40 to 85°C
0 to 70°C
40°C
—
—
—
—
10
5
µA
2
25°C
1
NOTES:
1. All values are maximum guaranteed values.
3778 tbl 08
2. Input low and high voltage levels are 0.2V and VDD-0.2V respectively for all tests.
3. fMAX = 1/tRC (all address inputs are cycling at fMAX).
4. f = 0 means no address input lines are changing .
5. Typical conditions are VDD = 2.0V and specified temperature.
3
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(VLC = 0.2V, VHC = VDD - 0.2V)
Symbol
VDR
Parameter
Test Condition
Min.
1.5
—
Typ. (1)
—
Max.
—
Unit
V
VCC for Data Retention
Data Retention Current
—
ICCDR
1) CS1 ≥ VHC and CS2 ≥ VHC
<1
5
µA
ns
(3)
tCDR
Chip Deselect to Data
Retention Time
or
0
—
—
2) CS2 ≤ VLC
(3)
tR
(2)
Operation Recovery Time
tRC
—
—
ns
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3779 tbl 09
3. This parameter is guaranteed by device characterization, but is not production tested.
LOW VDD DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VDD
1.8V
1.8V
VDR ≥ 1.5V
tCDR
tR
VIH
CS
VIH
VDR
3779 drw 05
AC TEST LOAD
AC TEST CONDITIONS
Input Pulse Levels
VDD
GND to VDD
3ns
Input Rise/Fall Times
3070Ω
Input Timing Reference Levels
Output Reference Levels
AC Test Load
VDD x 0.5
VDD x 0.5
See Figure 1
DATAOUT
50pF*
3150Ω
3779 tbl 10
3779 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
4
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 1.8 to 2.7V, All Temperature Ranges)
71T024L150
71T024L200
Symbol
Read Cycle
tRC
Parameter
Min.
Max.
Min.
Max. Units
Read Cycle Time
150
—
—
150
150
—
200
—
—
200
200
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tACS
Chip Select Access Time
—
—
(1)
tCLZ
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
20
—
20
—
(1)
tCHZ
30
75
—
40
tOE
—
—
100
—
(1)
tOLZ
20
—
20
—
(1)
tOHZ
30
—
40
tOH
15
15
—
Write Cycle
tWC
Write Cycle Time
150
120
120
0
—
—
—
—
—
—
—
—
—
40
200
160
160
0
—
—
—
—
—
—
—
—
—
50
ns
ns
tAW
Address Valid to End of Write
Chip Select Low to End of Write
Address Set-up Time
tCW
ns
tAS
ns
tWR
Address Hold from End of Write
Write Pulse Width
0
0
ns
tWP
100
60
0
140
80
0
ns
tDW
Data Valid to End of Write
Data Hold Time
ns
tDH
ns
(1)
tOW
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
5
5
ns
(1)
tWHZ
—
—
ns
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
3779 tbl 11
5
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t
RC
ADDRESS
tAA
OE
OE
t
(5)
tOLZ
CS1
CS2
(3)
t ACS
(5)
(5)
tOHZ
t CHZ
t CLZ
(5)
HIGH IMPEDANCE
DATA OUT
DATAOUT VALID
3779 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
PREVIOUS DATAOUT VALID
DATAOUT VALID
DATAOUT
3779 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected; CS1 is LOW and CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
CONTROLLED TIMING)(1, 2, 5)
WE
tWC
ADDRESS
tAW
tCW
CS1
CS2
(3)
tWR
(7)
tAS
tWP
WE
(6)
tCHZ
(6)
(6)
tWHZ
tOW
HIGH IMPEDANCE
tDW
(4)
(4)
DATAOUT
DATAIN
tDH
DATAIN VALID
3779 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
AND CS2 CONTROLLED TIMING)(1,2,5)
CS1
tWC
ADDRESS
tAW
CS1
CS2
WE
(3)
tWR
tAS
tCW
tDH
tDW
DATAIN
DATAIN VALID
3779 drw 10
NOTES:
1. WE or CS1 must be HIGH, or CS2 must be LOW during all address transitions.
2. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.
3. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If theCS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WELOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. OEis continuously HIGH. If during a WE controlled write cycle OEis LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
7
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
L
X
71T024
XXX
XX
IDT
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PZ
8mm x 13.4mm TSOP Type I
Speed in nanoseconds
150
200
3779 drw 11
8
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