IDT71T66802S133BG [IDT]
ZBT SRAM, 512KX18, 4.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119;
| 型号： | IDT71T66802S133BG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 512KX18, 4.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 静态存储器 |
| 文件： | 总23页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K x 36, 512K x 18
Preliminary
IDT71T66602
IDT71T66802
Smart ZBTTM 2.5VSynchronousSRAMs
2.5V I/O, Burst Counter
PipelinedOutputs
Features
Description
◆
The IDT71T66602/66802 are 2.5V high-speed 9,437,184-bit
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead
bus cycles when turning the bus around between reads and writes, or
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - from 66MHz to
133MHz
TM
◆
ZBTTM Feature - No dead cycles between write and read
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero
Bus Turnaround.
cycles
Smart ZBTTM Feature - Eases system timing requirements
◆
Address and control signals are applied to the SRAM during one
clockcycle,andtwocycles latertheassociateddatacycleoccurs,beit
read or write.
and reduces the likelihood of bus contention
With Smart ZBTTM the output turn-on (tCLZ) is adaptable to
◆
The IDT71T66602/66802 offer the user a Smart functionality which
simplifiessystemtimingrequirementswhenturningthebusaroundbetween
writesandreads.Traditionally,SRAMsaredesignedwithfastturn-ontimes
(tCLZ)inordertomeettherequirementsofhigh-speedapplications.Thisfast
turn-on may lead to bus contention at slower speeds, i.e. 133 MHz and
slower,sincethesedesignsoftenuselessaggressiveASICs/controllerswith
looseturn-offparameters(tCHZ).Thusatslowerspeeds,moremarginon
theRAM’stCLZ maybeneededtocompensatefortheslowturn-offofthe
ASIC/controller.TheIDT71T66602/66802havetheabilitytoprovidethis
extramarginbyallowingtCLZ toadapttotheuser’ssystem.
the user's system and is a function of the cycle time
◆
Backward compatible with IDT’s existing ZBT offerings
User selectable Smart ZBTTM or Original ZBTTM mode pin (MS)
◆
◆
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-lead plastic thin quad
◆
◆
◆
◆
WiththeSmartZBTTM feature,theoutputturn-ontime(tCLZ)adapts
to the user’s system and is solely a function of cycle time (tCYC). Thus
withSmartZBTTM,tCLZisindependentofprocess,voltage,andtempera-
turevariations.Withthisdeterministicoutputturn-onfeature,theguess
work of when the SRAM begins to drive the bus is removed, therefore
easingsystemtimingrequirements.TheSmartfeatureallowstheturn-on
◆
◆
◆
◆
◆
flatpack (TQFP) and 119-lead ball grid array (BGA).
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE2, CE2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW1, BW2, BW3, BW4
CLK
ADV/LD
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
LBO
TMS
N/A
TDI
N/A
TCK
Test Clock
N/A
TDO
Te st Data Output
Sleep Mode
N/A
ZZ
Asynchronous
Synchronous
Static
I/ O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input/Output
Core Power, I/O Power
Ground
Supply
Supply
SS
V
Static
5300 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
Smart ZBT and Smart Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is also supported by Micron Technology, Inc.
DECEMBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC-5300/00
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Description(cont.)
time of the ZBTTM SRAM output drivers (tCLZ) to adapt to match the databuswilltri-statetwocyclesafterthechipisdeselectedorawriteisinitiated.
requirementsofthesystem.
TheIDT71T66602/66802haveanon-chipburstcounter.Intheburst
TheIDT71T66602/66802containdataI/O,addressandcontrolsignal mode,theIDT71T66602/66802canprovidefourcyclesofdataforasingle
registers.Outputenableistheonlyasynchronoussignalandcanbeused address presented to the SRAM. The order of the burst sequence is
todisabletheoutputsatanygiventime.
defined by the LBO input pin. The LBO pin selects between linear and
A Clock Enable CEN pin allows operation of the IDT71T66602/66802 interleaved burst sequence. The ADV/LD signal is used to load a new
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter
(CEN)ishighandtheinternaldeviceregisterswillholdtheirpreviousvalues. (ADV/LD = HIGH).
There are three chip enable pins (CE1, CE2, CE2) that allow the
The IDT71T66602/66802 SRAMs utilize IDT’s latest high-perfor-
user to deselect the device when desired. If any one of these three is not mance 2.5V CMOS process, and are packaged in a JEDEC Standard
assertedwhenADV/LD islow, nonewmemoryoperationcanbeinitiated. 14mmx20mm100-leadthinplasticquadflatpack(TQFP)aswellasa119-
However,anypendingdatatransfers(readsorwrites)willbecompleted.The lead ball grid array (BGA).
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A
0
-A18
Addre ss Inputs
I
N/A
Synchronous Addre ss inputs. The addre ss re giste r is trigge re d by a combination of the rising e dge of CLK,
ADV/LD low, CEN low, and true chip e nable s.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a sync hronous input that is use d to load the inte rnal re giste rs with ne w addre ss and control whe n it is
sample d lo w at the rising e dge of clock with the chip se le c te d. Whe n ADV/LD is low with the chip de se le cte d,
any burst in progre ss is te rminate d. Whe n ADV/LD is sample d high the n the inte rnal burst counte r is advance d
for any burst that was in progre ss. The e xte rna l addre sse s are ignore d whe n ADV/LD is sample d high.
R/
W
Re ad / Write
Clock Enable
I
I
N/A
R/W signal is a synchronous input that ide ntifie s whe the r the curre nt load cycle initiate d is a Re ad or Write acce ss
to the me mory array. The data bus activity for the curre nt cycle take s place two clock cycle s late r.
LOW
Synchronous Clock Enable Input. Whe n CEN is sample d high, all othe r synchronous inputs, including clock are
ignore d and outputs re main unchange d. The e ffe ct of CEN sample d high on the de vice outputs is as if the low
to high clock transition did not occur. For normal ope ration, CEN must be sample d low at rising e dge of clock.
CEN
Individ ual Byte
Write Enable s
I
I
LOW
LOW
Synchronous byte write e nable s. Each 9-bit byte has its own active low byte write e nable . On load write cycle s
BW
1
-
BW
4
(whe n R/
write signal must also be valid on e ach cycle of a burst write . Byte Write signals are ignore d whe n R/
high. The appropriate byte (s) of data are writte n into the de vice two cycle s late r. BW can all be tie d low if
always doing write to the e ntire 36-bit word.
W
and ADV/LD are sample d low) the appropriate byte write signal (BW
1
-
BW
4
) must be valid. The byte
W
is sample d
1
-
BW
4
Chip Enable s
S ynchronous active low chip e nable . CE
sample d high or CE sample d low) and ADV/LD low at the rising e dge of clock, initiate s a de se le ct cycle .
The ZBTTM has a two cycle de se le ct, i.e ., the data bus will tri-state two clo ck cycle s afte r de se le ct is initiate d.
1
and CE
2
are use d with CE
2
1
to e nable the IDT71T66602/66802 (CE or
CE
1
,
CE
2
CE
2
2
CE
2
Chip Enable
Clock
I
I
HIGH
N/A
Synchronous active high chip e nable . CE
but othe rwise ide ntical to CE and CE
2
is use d with CE
1
2 2
and CE to e nab le the chip . CE has inve rte d polarity
1
2
.
CLK
This is the clock input to the IDT71T66602/66802. Exce pt for OE, all timing re fe re nce s for the de vice are made
with re spe ct to the rising e dge of CLK.
I/O
I/OP 1-I/OP 4
0
-I/O31
Data Inp ut/Outp ut
Line ar Burst Orde r
Output Enable
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input pa th and data output path are re g iste re d and trigge re d
by the rising e dge of CLK.
LOW
LOW
Burst orde r se le ction input. Whe n LBO is high the Inte rle ave d burst se que nce is se le cte d. Whe n LBO is low the
Line ar burst se que nce is se le cte d. LBO is a static input and it must not change during de vice ope ration.
LBO
I
Asynchronous output e nable . OE must be low to re ad data from IDT71T66602/66802. Whe n OE is high the I/O
pins are in a high-impe dance state .OE doe s not ne e d to be active ly controlle d for re ad and write cycle s. In normal
ope ration, OE can be tie d low.
OE
TMS
TDI
Te st Mode Se le ct
Te st Data Input
Te st Clo c k
I
I
I
N/A
N/A
N/A
Give s input command for TAP controlle r; sample d o n rising e dge of TCK.
Se rial input of re giste rs place d be twe e n TDI and TDO. Sample d o n rising e dge of TCK.
TCK
Clock input of TAP controlle r. Each TAP e ve nt is clocke d. Te st inputs are capture d o n rising e dge of TCK,
while te st outputs are drive n from falling e dge of TCK.
TDO
ZZ
Te st Data Output
Sle e p Mode
O
I
N/A
Se rial output of re giste rs place d be twe e n TDI and TDO. This output is active de pe nding on the state of the TAP
controlle r.
HIGH
Asynchronous s le e p mode input. ZZ HIGH will gate the CLK inte rnally and powe r down the IDT71T66602/66802
to its lowe st powe r consumption le ve l. Data re te ntion is guarante e d in Sle e p Mode .
V
DD
DDQ
S S
Powe r Supply
Powe r Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
2.5V core powe r supply.
2.5V I/O Supply.
V
V
Ground.
5300 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.422
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
FunctionalBlockDiagram
LBO
256Kx36 BIT
MEMORY ARRAY
Address A [0:17]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
,
5300 drw 01a
Data I/O [0:31],
I/O P[1:4]
LBO
512Kx18 BIT
MEMORY ARRAY
Address
Address A [0:18]
D
D
Q
Q
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
,
,
5300 drw 01b
Data I/O [0:15],
I/O P[1:2]
6.42
3
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
RecommendedDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
VDD
VDDQ
VSS
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
2.375
2.375
0
Typ.
Max.
2.625
2.625
0
Unit
V
Grade
Temperature
VSS
VDD
VDDQ
2.5
Commercial
0°C to +70°C
0V
2.5V±5%
2.5V±5%
2.5
V
5300 tbl 05
0
V
____
VIH
Input High Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
1.7
VDD +0.3
VDDQ+0.3
0.7
V
____
____
VIH
1.7
V
VIL
-0.3(1)
V
5300 tbl 03
NOTE:
1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.
Pin Configuration 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
2
3
4
5
76
75
74
73
6
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
I/O22
I/O23
VDDQ
I/O9
I/O8
69
68
67
66
65
64
63
62
61
60
59
(4)
VSS
VSS
VDD
(1)
VDD
(1)
VDD
VDD
ZZ
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
58
57
56
55
54
53
VDDQ
I/O30
I/O31
I/OP4
,
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5300 drw 02a
Top View
TQFP
NOTES:
1. Pins 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU = Do not use
4. Pin 14 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL.
6.442
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Pin Configuration 512K x 18
AbsoluteMaximumRatings(1)
Symbol
Rating
Commercial
Unit
(2)
TERM
V
Terminal Voltage with
Respect to GND
-0.5 to +3.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
(3,6)
(4,6)
(5,6)
TERM
V
DD
1
Terminal Voltage with
Respect to GND
-0.5 to V
V
V
V
80
NC
NC
NC
VDDQ
VSS
NC
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
VDD
ZZ
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
2
79
78
77
3
4
TERM
V
DD
-0.5 to V +0.5
Terminal Voltage with
Respect to GND
5
76
75
74
73
6
7
NC
8
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
TERM
V
DDQ
Terminal Voltage with
Respect to GND
-0.5 to V +0.5
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
0 to +70
-55 to +125
-55 to +125
2.0
oC
oC
oC
W
69
68
67
66
A
T
(4)
VSS
BIAS
T
(1)
VDD
(1)
65
64
63
62
VDD
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
STG
T
T
P
61
60
59
OUT
I
DC Output Current
50
mA
58
57
56
55
5300 tbl 06
NOTES:
NC
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
VSS
VDDQ
NC
NC
NC
54
53
,
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5300 drw 02b
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
TQFP
NOTES:
1. Pins 16 and 66 do not have to be connected directly to VDD as long as the input
voltage is ≥VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU = Do not use
4. Pin 14 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL.
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP Package)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
5
7
pF
CI/O
pF
5300 tbl 07
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
5
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Pin Configuration 256K X 36 BGA(1,2,3)
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
NC(2)
ADV/LD
2
3
2
9
NC
NC
CE
NC
NC
2
CE
7
A
DD
V
12
15
A
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
13
15
I/O
V
V
V
NC
V
V
V
I/O
17
I/O
18
I/O
14
I/O
I/O
1
CE
DDQ
20
19
I/O
12
I/O
DDQ
10
V
V
OE
21
I/O
11
I/O
G
H
J
I/O
A17
I/O
2
BW3
BW
22
I/O
23
I/O
SS
V
SS
V
9
I/O
8
I/O
R/W
DDQ
V
DD
DD
V
DD
DDQ
V
DD(1)
DD(1)
V
V
V
V
V
24
I/O
26
I/O
SS
4
SS
6
I/O
7
I/O
K
L
CLK
NC
V
25
I/O
27
I/O
4
I/O
5
I/O
1
BW
BW
DDQ
28
SS
V
SS
SS
SS
3
DDQ
V
M
N
P
R
T
V
I/O
V
V
V
I/O
CEN
29
I/O
30
I/O
SS
1
2
I/O
1
I/O
V
V
A
A
31
I/O
P4
SS
0
0
I/O
P1
I/O
I/O
DNU
ZZ
(3)
5
DD
11
13
NC
A
V
SS(4)
V
A
LBO
10
A
14
A
NC
NC
TMS
A
NC
(3)
DDQ
V
DDQ
V
U
TDI
TCK
TDO
DNU
5300 drw 13a
Top View
Pin Configuration 512K X 18 BGA(1,2,3)
1
2
3
4
5
6
7
DDQ
6
4
8
16
A
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
NC(2)
3
2
9
NC
NC
CE2
A
NC
NC
NC
2
CE
ADV/LD
7
A
DD
V
13
17
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
V
V
V
V
9
I/O
6
I/O
NC
DDQ
1
CE
NC
5
I/O
DDQ
V
V
NC
OE
10
4
I/O
G
H
J
NC
I/O
NC
NC
A18
BW2
11
I/O
SS
V
SS
3
I/O
V
NC
R/W
DD(1)
DD(1)
SS
DDQ
V
DD
DD
V
DD
V
DDQ
V
V
V
V
V
12
SS
2
I/O
K
L
NC
I/O
NC
CLK
NC
V
NC
13
I/O
SS
1
I/O
V
NC
1
BW
DDQ
14
SS
SS
SS
SS
DDQ
V
M
N
P
R
T
V
I/O
NC
V
V
V
V
V
V
NC
CEN
15
SS
SS
1
0
I/O
I/O
NC
A
A
NC
P2
0
P1
I/O
I/O
NC
(3)
5
DD
V
SS(4)
12
11
NC
NC
DDQ
A
A
V
DNU
LBO
10
15
A
14
A
A
NC
A
ZZ
(3)
DDQ
V
5300 drw 13b
U
V
TMS
TDI
TCK
TDO
DNU
Top View
NOTES:
1. J3 and J5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A4 is reserved for future 16M.
3. DNU = Do not use.
4. R5 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL.
6.462
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
SynchronousTruthTable(1)
R/W
Chip(5)
Enable
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
(2 cycles later)
(7)
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
BURST WRITE
D
(7)
Q
(7)
Valid
LOAD WRITE /
BURST WRITE
D
(2)
(Advance burst counter)
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(2)
(Advance burst counter)
DESELECT or STOP(3)
NOOP
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
HiZ
HiZ
X
X
DESELECT / NOOP
X
(4)
SUSPEND
Previous Value
5300 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Osremainsunchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3)
OPERATION
R/W
H
L
BW1
X
BW2
X
BW3
BW4
READ
X
L
X
L
WRITE ALL BYTES
L
L
(2)
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1)
L
L
H
H
H
L
H
H
H
L
P2
WRITE BYTE 2 (I/O[8:15], I/O )
L
H
L
(2,3)
P3
WRITE BYTE 3 (I/O[16:23], I/O )
L
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)
NO WRITE
L
H
H
H
H
L
H
H
H
5300 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
7
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
Second Address
Third Address
1
0
1
1
0
0
1
0
0
1
Fourth Address(1)
1
0
0
1
0
5300 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5300 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A17)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O[0:31], I/O P[1:4]
,
5300 drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.482
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Device Operation - Showing Mixed Load, Burst,
DeselectandNOOPCycles(2)
CE(1)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWx
X
X
X
X
X
X
X
X
L
OE
X
X
L
0
A
n
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
X
X
Load read
Burst read
Load read
n+1
X
X
L
1
A
0
Q
n+2
0+1
Q
n+3
X
X
H
X
L
L
Deselect or STOP
NOOP
1
Q
n+4
L
2
A
n+5
X
X
L
Z
Z
Load read
Burst read
Deselect or STOP
Load write
n+6
X
X
X
H
L
2
Q
n+7
3
A
2+1
Q
n+8
L
n+9
X
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
4
A
3
D
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
L
Load write
3+1
D
X
X
X
X
L
H
X
L
X
X
L
Deselect or STOP
NOOP
4
D
5
A
Z
Z
Load write
6
A
H
L
L
X
L
Load read
Load write
7
A
5
D
L
6
Q
X
X
H
X
L
X
L
L
Burst write
8
A
7
D
X
X
L
X
X
L
Load read
Burst read
Load write
7+1
D
X
X
L
9
A
8
Q
5300 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
ReadOperation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
n
A0
X
X
H
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
L
X
X
X
X
X
L
Q0
Contents of Address A0 Read Out
5300 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
9
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Burst Read Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
X
L
0
A
n
H
X
X
X
X
H
X
X
H
L
H
H
H
H
L
X
X
Address and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
L
X
Clock Setup Valid, Advance Counter
0
Q
0
X
L
X
Address A Read Out, Inc. Count
0+1
Q
0+1
X
L
X
L
Address A Read Out, Inc. Count
0+2
Q
0+2
X
L
X
L
Address A Read Out, Inc. Count
1
A
0+3
Q
0+3
1
L
L
X
L
Address A Read Out, Load A
0
Q
0
X
X
H
H
L
X
L
X
L
Address A Read Out, Inc. Count
1
Q
1
X
L
X
L
Address A Read Out, Inc. Count
2
A
1+1
Q
1+1
2
L
L
X
L
Address A Read Out, Load A
5300 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
n
A0
X
X
L
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
L
X
X
X
L
X
X
D0
Write to Address A0
5300 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
X
X
X
X
X
X
X
X
0
A
n
n+1
L
X
X
X
X
L
L
H
H
H
H
L
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
X
X
X
X
X
L
L
0
D
0
n+2
X
L
L
Address A Write, Inc. Count
0+1
D
0+1
n+3
X
L
L
Address A Write, Inc. Count
0+2
D
0+2
n+4
X
L
L
Address A Write, Inc. Count
1
A
0+3
D
0+3
1
n+5
L
L
L
Address A Write, Load A
0
D
0
n+6
X
X
X
X
L
H
H
L
X
L
L
Address A Write, Inc. Count
1
D
1
n+7
X
L
L
Address A Write, Inc. Count
2
A
1+1
D
1+1
2
n+8
L
L
L
Address A Write, Load A
5300 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1402
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Read Operation with Clock Enable Used(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
L
0
A
n
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
X
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
A1
X
X
L
H
L
X
X
Clock Valid
0
Q
0
X
X
L
H
H
L
X
Clock Ignored. Data Q is on the bus.
0
Q
0
X
X
L
Clock Ignored. Data Q is on the bus.
2
A
0
Q
0
X
L
Address A Read out (bus trans.)
3
A
1
Q
1
L
L
X
L
Address A Read out (bus trans.)
A4
L
L
X
L
Q2
Address A2 Read out (bus trans.)
5300 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
X
X
X
X
X
0
A
n
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
L
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
A1
X
X
L
H
L
X
L
X
X
L
H
H
L
X
X
L
Clock Ignored.
X
Clock Ignored.
2
A
0
D
0
Write Data D
3
A
1
D
1
L
L
L
Write Data D
A4
L
L
L
D2
Write Data D2
5300 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Read Operation with Chip Enable Used(1)
(3)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
0
A
Z
Z
Address and Control meet setup.
Deselected or STOP.
X
H
L
1
A
0
Q
0
1
Address A Read out. Load A .
X
X
H
H
L
X
L
Z
Deselected or STOP.
1
1
Q
Z
Z
Address A Read out. Deselected.
2
A
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
2
Q
2
Address A Read out. Deselected.
5300 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
X
X
L
OE
X
X
X
X
X
X
X
X
X
X
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
L
?
Deselected.
0
A
L
Z
Z
Address and Control meet setup.
Deselected or STOP.
X
X
L
H
L
L
X
L
1
A
0
D
0
1
L
Address D Write in. Load A .
X
X
X
X
L
H
H
L
L
X
X
L
Z
Deselected or STOP.
1
D
1
L
Address D Write in. Deselected.
2
A
L
Z
Z
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
H
L
X
X
2
D
2
L
Address D Write in. Deselected.
5300 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1422
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
LI
|I |
DD
V
IN
DD
Input Leakage Current
= Max., V = 0V to V
5
µA
(1)
___
___
___
LBO Input Leakage Current
Output Leakage Current
Output Low Voltage
LI
DD
IN
DD
|I |
V
= Max., V = 0V to V
30
5
µA
µA
V
LO
|I |
OUT
V
DDQ
= 0V to V , Device Deselected
OL
V
OL
DD
I
= +6mA, V = Min.
0.4
___
OH
V
OH
I
DD
Output High Voltage
= -6mA, V = Min.
2.0
V
5300 tbl 21
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(1) (VDD=2.5V±5%)
Symbol
Parameter
Test Conditions
133MHz
100MHz
Unit
DD
I
Device Selected, Outputs Open,
Operating Power
Supply Current
300
250
mA
DD
ADV/LD = X, V = Max.,
(2)
MAX
IN
IH
IL
V > V or < V , f = f
SB1
I
Device Deselected, Outputs Open,
CMOS Standby Power
Supply Current
40
110
40
40
100
40
mA
mA
DD
IN
HD
LD
V
= Max., V > V or < V ,
(2,3)
f = 0
SB2
I
Device Deselected, Outputs Open,
Clock Running Power
Supply Current
DD
IN
HD
LD
V
= Max., V > V or < V ,
(2.3)
f = fMAX
SB3
I
Device Selected, Outputs Open,
Idle Power
Supply Current
mA
IH DD
CEN > V , V = Max.,
(2,3)
IN
HD
LD
MAX
V > V or < V , f = f
5300 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
VDDQ/2
AC Test Load
AC Test Conditions
Input Pulse Levels
50Ω
0 to 2.5V
I/O
Z0 = 50Ω
,
Input Rise/Fall Times
2ns
5300 drw 04
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
(VDDQ/2)
(VDDQ/2)
Figure 1. AC Test Load
6
5
4
3
See Figure 1
•
5300 tbl 23
∆tCD
(Typical, ns)
2
•
•
1
•
•
,
20 30 50
80 100
Capacitance (pF)
200
5300 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
13
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
AC Electrical Characteristics
(VDD = 2.5V±5%, TA = 0 to 70°C)
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
CYC
t
Clock Cycle Time
Clock Frequence
7.5
—
10
—
ns
MHz
ns
____
____
(1)
133
100
F
t
____
____
(2)
CH
Clock High Pulse Width
Clock Low Pulse Width
2.2
2.2
3.2
3.2
t
____
____
(2)
CL
ns
t
Output Parameters
____
____
(5)
(5)
CD
t
Clock High to Valid Data
ns
ns
ns
ns
ns
ns
ns
CYC
( t
CYC
/ 3 ) + 2.0
/ 3 ) + 2.0
( t
____
____
(5)
(5)
CDC
t
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
CYC
CYC
/ 3 ) - 0.2
( t
/ 3 ) - 0.2
( t
____
____
(3,4)
(5)
(5)
CLZ
t
CYC
( t
CYC
( t / 3 ) - 0.2
/ 3 ) - 0.2
(3,4)
1.5
3
1.5
3.3
CHZ
t
____
____
OE
t
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
4.2
5
____
____
(3,4)
(3,4)
0
0
OLZ
t
____
____
4.2
5
OHZ
t
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
SE
t
Clock Enable Setup Time
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
SA
t
Address Setup Time
SD
t
Data In Setup Time
SW
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
SADV
t
SC
t
SB
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HE
t
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
HA
t
Address Hold Time
HD
t
Data In Hold Time
HW
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
HADV
t
HC
t
HB
t
ns
5300 tbl 23a
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. Smart ZBT functionality only guaranteed at 66 MHz ≤ f ≤ 133MHz.
6.1442
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Timing Waveform of Read Cycle(1,2,3,4)
,
.
6.42
15
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Smart ZBTTM Timing
Clock
ASIC Write
tCHZ (max)
tCD
Smart ZBTTM Read
tCLZ (tCYC/3)
,
Additional Margin
provided by Smart ZBTTM
tCLZ (min)
Traditional ZBT™ Read
5300 drw 05a
tCD
6.1462
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Timing Waveform of Write Cycles(1,2,3,4,5)
,
.
6.42
17
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
,
6.1482
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Timing Waveform of CEN Operation(1,2,3,4)
,
6.42
19
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Timing Waveform of CS Operation(1,2,3,4)
,
6.2402
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
119-Lead Ball Grid Array (BGA) Package Diagram Outline
6.42
21
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
,
5300 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
IDT
XXXX
S
XX
XX
Device
Type
Power Speed
Package
PF
BG
100-Lead Plastic Thin Quad Flatpack (TQFP)
119-Lead Ball Grid Array (BGA)
133
100
Clock Frequency in Megahertz
IDT71T66602
IDT71T66802
256Kx36 Pipelined Smart ZBT SRAM
512Kx18 Pipelined Smart ZBT SRAM
5300 drw 12
6.2422
IDT71T66602, IDT71T66802, 256K x 36, 512K x 18, 2.5V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Range
Datasheet Document History
12/31/99
CreatedSmartZBTdatasheet
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6.42
23
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