IDT71T75602S200PFG8_技术文档

512K x 36, 1M x 18

IDT71T75602

IDT71T75802

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

PipelinedOutputs

Features

◆

Description

512K x 36, 1M x 18 memory configurations

◆

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit

(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead

bus cycles when turning the bus around between reads and writes, or

Supports high performance system speed - 225 MHz

(3.0 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

TM

writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero

Bus Turnaround.

cycles

◆

Internally synchronized output buffer enable eliminates the

Address and control signals are applied to the SRAM during one

clockcycle,andtwocycles latertheassociateddatacycleoccurs,beit

read or write.

need to control OE

◆

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

TheIDT71T75602/802containdataI/O,addressandcontrolsignal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

AClockEnable CEN pinallows operationofthe IDT71T75602/802

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

2.5V power supply (±5%)

2.5V I/O Supply (VDDQ)

Power down controlled by ZZ input

Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

PinDescriptionSummary

A⁰-A¹⁹

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE², CE2

OE

Output Enable

W

R/

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW4

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

LBO

TMS

N/A

TDI

N/A

TCK

Test Clock

N/A

TDO

Test Data Input

N/A

JTAG Reset (Optional)

Sleep Mode

Asynchronous

Synchronous

Static

TRST

ZZ

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

Static

5313 tbl 01

APRIL 2004

1

DSC-5313/08

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Description(cont.)

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-statetwocyclesafterthechipisdeselectedorawrite

isinitiated.

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter

(ADV/LD = HIGH).

TheIDT71T75602/802SRAMsutilizeIDT’slatesthigh-performance

2.5VCMOSprocess,andarepackagedinaJEDECStandard14mmx

20mm100pinthinplasticquadflatpack(TQFP)aswellasa119ballgrid

array (BGA).

The IDT71T75602/802 have an on-chip burst counter. In the burst

mode,theIDT71T75602/802canprovidefourcyclesofdataforasingle

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

Pin Definitions⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

A⁰-A¹⁹

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,

ADV/LD low, CEN low, and true chip enables.

ADV/LD

Advance / Load

I

N/A

ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is

sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected,

any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced

for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high.

R/W

Read / Write

Clock Enable

I

N/A

R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access

to the memory array. The data bus activity for the current cycle takes place two clock cycles later.

LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are

ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low

to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.

CEN

Individual Byte

Write Enables

I

LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles

(when R/W and ADV/LD are sampled low) the appropriate byte write signal (BW¹-BW⁴) must be valid. The byte

write signal must also be valid oneach cycle of a burstwrite. Byte Write signals are ignored when R/W is sampled

high. The appropriate byte(s) of data are written into the device two cycles later. BW¹-BW⁴can all be tied low if

always doing write to the entire 36-bit word.

BW¹-BW4

CE¹, CE2

CE1 CE2

and

2

CE1 CE2

are used with CE to enable the IDT71T75602/802 ( or

Chip Enables

LOW Synchronous active low chip enable.

sampled high or CE²sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The

ZBT^TMhas a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.

CE²

Chip Enable

Clock

I

HIGH Synchronous active high chip enable. CE²is used with CE¹and CE²to enable the chip. CE²has inverted polarity

but otherwise identical to CE¹and CE².

CLK

N/A

This is the clock input to the IDT71T75602/802. Except for OE, all timing references for the device are made with

respect to the rising edge of CLK.

I/O⁰-I/O³¹

I/O^P1-I/O^P4

Data Input/Output

Linear Burst Order

Output Enable

I/O

I

N/A

Synchronous data input/output(I/O)pins. Boththe data inputpathand data outputpath are registered and triggered

by the rising edge of CLK.

LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the

Linear burst sequence is selected. LBO is a static input and it must not change during device operation.

LBO

I

LOW Asynchronous output enable. OE must be low to read data from the 71T75602/802. When OE is high the I/O pins

OE

are in a high-impedance state. does not need to be actively controlled for read and write cycles. In normal

operation, OE can be tied low.

TMS

TDI

Test Mode Select

Test Data Input

I

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal

pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while

test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TCK

TDO

Test Clock

I

N/A

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP

controller.

Test Data Output

O

Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs

LOW automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left

JTAG Reset

(Optional)

I

TRST

floating. This pin has an internal pullup. Only available in BGA package.

Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its

lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown.

ZZ

Sleep Mode

HIGH

V^DD

V^DDQ

V^SS

Power Supply

Ground

N/A

2.5V core power supply.

2.5V I/O Supply.

Ground.

5313 tbl 02

NOTE:

1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.

6.422

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

FunctionalBlockDiagram

LBO

512Kx36 BIT

MEMORY ARRAY

Address A [0:18]

D

Q

Address

CE1, CE2, CE

2

R/W

Control

CEN

ADV/LD

DI

DO

BWx

D

Q

Control Logic

Clk

Mux

Sel

D

Output Register

Q

Clock

Gate

OE

,

5313 drw 01

TMS

TDI

TCK

Data I/O [0:31],

I/O P[1:4]

TDO

JTAG

TRST

(optional)

LBO

1Mx18 BIT

MEMORY ARRAY

Address

Address A [0:19]

CE CE

D

Q

1, CE2,

2

W

R/

CEN

ADV/LD

BW

D

Q

Control

DI

DO

x

D

Q

Control Logic

Clk

Mux

Sel

D

Output Register

Q

Clock

Gate

OE

,

5313 drw 01b

,

TMS

TDI

TCK

Data I/O [0:15],

I/O P[1:2]

TDO

JTAG

TRST

(optional)

6.42

3

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

RecommendedDCOperating

Conditions

RecommendedOperating

TemperatureandSupplyVoltage

Symbol

V^DD

V^DDQ

V^SS

Parameter

Core Supply Voltage

I/O Supply Voltage

Ground

Min.

2.375

0

Typ.

Max.

2.625

0

Unit

V

Ambient

Grade

VSS

VDD

VDDQ

Temperature⁽¹⁾

0° C to +70° C

-40° C to +85° C

2.5

Commercial

Industrial

OV 2.5V ± 5%

2.5V ± 5%

2.5

V

2.5V ± 5%

0

V

____

5313 tbl 05

V^IH

InputHigh Voltage - Inputs

Input High Voltage -I/O

Input Low Voltage

1.7

V^DD+0.3

V^DDQ+0.3

0.7

V

NOTE:

1. During production testing, the case temperature equals the ambient temperature.

____

V^IH

1.7

V

(1)

V^IL

-0.3

V

5313 tbl 03

NOTE:

1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.

Pin Configuration 512K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

I/OP3

I/O16

I/O17

I/OP2

I/O15

I/O14

2

79

78

77

3

4

V

DDQ

V

DDQ

5

V

SS

76

75

74

73

72

71

70

V

SS

6

I/O18

I/O19

I/O20

I/O21

I/O13

I/O12

I/O11

I/O10

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

SS

V

DDQ

V

DDQ

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

I/O22

I/O23

I/O

9

I/O

8

V

DD⁽¹⁾

V

SS

DD⁽¹⁾

DD

V

DD

DD⁽¹⁾

SS

V

ZZ

I/O

I/O24

I/O25

7

6

V

DDQ

V

DDQ

V

SS

V

SS

I/O26

I/O27

I/O28

I/O29

I/O

5

4

3

2

V

SS

V

SS

V

DDQ

V

DDQ

I/O30

I/O31

I/OP4

I/O

1

I/O

0

I/OP1

,

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5313 drw 02

Top View

100TQFP

NOTES:

1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.

2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without

interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin

42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected

“NC” and the JTAG circuit will remain disabled from power up.

3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.

6.442

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration 1Mx 18

AbsoluteMaximumRatings⁽¹⁾

Symbol

Rating

Commercial

Industrial

Unit

(2)

VTE RM

Terminal Voltage with

Respect to GND

V

-0.5 to +3.6

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

(3,6)

VTE RM

Terminal Voltage with

Respect to GND

V

1

80

NC

DDQ

V

SS

V

NC

8

I/O

9

I/O

SS

V

10

A

-0.5 to VDD

2

79

78

77

NC

3

(4,6)

4

VTE RM

DDQ

Terminal Voltage with

Respect to GND

V

-0.5 to VDD +0.5

5

76

75

74

73

SS

6

NC

P1

I/O

7

I/O

6

I/O

7

(5,6)

VTE RM

Terminal Voltage with

Respect to GND

8

-0.5 to VDDQ +0.5 -0.5 to VDDQ +0.5

9

72

71

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SS

V

Operating Ambient

Temperature

70

69

68

67

66

65

64

(7)

^oC

DDQ

V

DDQ

5

TA

0 to +70

-40 to +85

10

I/O

11

(1)

DD

I/O

V

4

I/O

SS

(1)

DD

V

TBIAS

TSTG

PT

Temperature Under Bias

Storage Temperature

Power Dissipation

-55 to +125

2.0

-55 to +125

2.0

^oC

W

V

DD

V

DD

(1)

DD

V

SS

V

ZZ

3

I/O

2

I/O

DDQ

V

63

62

12

I/O

13

I/O

61

60

59

58

57

56

55

DDQ

V

SS

V

IOUT

DC Output Current

50

mA

SS

V

5313 tbl 06

14

I/O

1

I/O

15

I/O

0

I/O

NC

NOTES:

P2

I/O

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

NC

SS

V

DDQ

V

NC

26

27

28

29

30

SS

V

54

53

,

DDQ

NC

52

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5313 drw 02a

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;

however, the voltage on any input or I/O pin cannot exceed VDDQ during power

supply ramp up.

Top View

100TQFP

1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as

the input voltage is ≥ VIH.

NOTES:

7. During production testing, the case temperature equals TA.

2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To

disable the TAP controller without interfering with normal operation, several

settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and

pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)

pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit

will remain disabled from power up.

3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin

TQFP package for the 36M ZBT device.

165fBGACapacitance

(TA = +25°C, f = 1.0MHz)

100-PinTQFPCapacitance

(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

V^IN= 3dV

V^OUT= 3dV

Max. Unit

Symbol

C^IN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

V^IN= 3dV

V^OUT= 3dV

Max. Unit

Symbol

C^IN

7

pF

5

7

pF

C^I/O

pF

C^I/O

pF

5313 tbl 07b

5313 tbl 07

119BGACapacitance

(TA = +25°C, f = 1.0MHz)

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

7

pF

CI/O

pF

5313 tbl 07a

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

5

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration 51₁2K X 36, 119₄BGA^(1,2)

2

3

5

6

7

Top View

DDQ

V

A

B

C

D

E

F

V

A

6

4

18

8

16

NC

CE₂

A

ADV/LD

A

NC

CE₂

3

9

DD

V

A

7

2

12

15

SS

V

SS

V

I/O

NC

I/O

16

P3

P2

15

SS

V

SS

V

I/O

CE

17

18

13

14

1

DDQ

V

SS

V

SS

V

DDQ

V

I/O

OE

19

12

G

H

J

I/O

A

I/O

10

BW₃

BW₂

20

21

17

11

SS

V

SS

V

I/O

R/W

I/O

8

22

23

9

(1)

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

SS

K

L

M

I/O

V

CLK

NC

V

I/O

7

24

26

6

I/O

5

BW₄

BW₁

25

27

4

DDQ

V

SS

V

SS

V

DDQ

V

I/O

CEN

I/O

3

28

SS

N

P

I/O

V

A

V

I/O

1

29

30

1

2

SS

V

SS

V

I/O

A

I/O

0

31

P4

0

P1

(1)

DD

V

R

T

U

NC

A

V

A

NC

LBO

5

13

(3)

NC

A

14

NC

ZZ

10

11

NC/TMS⁽²⁾

(2)

(2, 4)

NC/

TRST

NC/TCK NC/TDO

VDDQ

NC/TDI

VDDQ

5313 tbl 25

Pin Configuration 1M X 18, 119 BGA^(1,2)

1

2

3

4

5

6

7

Top View

A

B

C

D

E

F

V

A

V

DDQ

6

4

19

8

16

NC

CE₂

A

ADV/LD

A

NC

I/O₇

CE₂

3

9

NC

A

V

DD

A

7

2

13

17

I/O₈

NC

I/O₉

NC

V

SS

NC

CE₁

OE

V

SS

I/O_P1

NC

V

SS

V

SS

V

SS

V

SS

I/O₆

NC

V

DDQ

I/O₅

NC

G

H

J

NC

I/O

A

V

SS

BW₂

10

18

I/O

NC

V

SS

R/W

V

SS

I/O₄

11

(1)

V

DDQ

V

DD

V

DD

V

DD

V

DD

DDQ

I/O₃

NC

K

L

M

N

P

NC

I/O

V

CLK

NC

V

NC

I/O₂

NC

SS

12

I/O

13

NC

I/O

V

SS

BW

1

V

SS

V

SS

V

DDQ

I/O₁₅

NC

DDQ

NC

I/O₀

NC

ZZ

CEN

14

NC

I/O

V

SS

A

V

SS

I/O

1

V

SS

A

V

SS

NC

P2

0

(1)

R

T

U

NC

A

V

A

DD

LBO

5

12

(3)

NC

A

NC

A

10

15

14

11

(2)

(2, 4)

NC/TMS⁽²⁾

NC

/TRST

V

DDQ

NC/TDI

V

DDQ

NC/TCK NC/TDO

5313 tbl 25a

NOTES:

1. J3, R5, and J5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings

are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST) U2, U3,

U4 and U6 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.

3. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device).

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6.462

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

SynchronousTruthTable⁽¹⁾

Chip^{(5 )}

Enable

ADV/LD

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

CEN

BWx

R/W

(2 cycles later)

(7 )

L

H

X

Select

X

L

H

Valid

X

External

Internal

X

LOAD WRITE

LOAD READ

D

(7 )

Q

(7 )

Valid

LOAD WRITE /

BURST WRITE

D

(Advance burst counter)^{(2 )}

(7 )

L

X

H

X

Internal

LOAD READ /

BURST READ

Q

(Advance burst counter)^{(2 )}

L

H

X

Deselect

L

H

X

DESELECT or STOP^{(3 )}

NOOP

HiZ

X

DESELECT / NOOP

X

(4 )

SUSPEND

Previous Value

5313 tbl 08

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE¹, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will

tri-state two cycles after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the

I/Osremainsunchanged.

5. To select the chip requires CE¹= L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

Partial Truth Table for Writes⁽¹⁾

(3 )

BW1

X

BW2

X

BW3

BW4

OPERATION

R/W

H

L

READ

X

L

X

L

WRITE ALL BYTES

WRITE BYTE 1 (I/O[0:7], I/O^P1)

L

(2 )

L

H

L

H

L

(2 )

WRITE BYTE 2 (I/O[8:15], I/O^P2)

WRITE BYTE 3 (I/O[16:23], I/O^P3)^(2,3)

WRITE BYTE 4 (I/O[24:31], I/O^P4)^(2,3)

NO WRITE

L

H

L

H

L

H

L

H

5313 tbl 09

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for X18 configuration.

6.42

7

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

A0

0

A1

A0

First Address

0

1

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5313 tbl 10

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

1

A0

0

A1

1

A0

First Address

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5313 tbl 11

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

FunctionalTimingDiagram⁽¹⁾

CYCLE

n+29

n+30

n+31

n+32

n+33

n+34

n+35

n+36

n+37

CLOCK

(2)

ADDRESS

A29

C29

A30

C30

A31

C31

A32

C32

A33

C33

A34

C34

A35

C35

A36

C36

A37

C37

(A0 - A18)

(2)

CONTROL

(R/W, ADV/LD, BWx)

(2)

DATA

D/Q27

D/Q28

D/Q29

D/Q30

D/Q32

D/Q33

D/Q34

D/Q35

D/Q31

I/O[0:31], I/O P[1:4]

,

5313drw 03

NOTES:

1. This assumes CEN, CE1, CE2, CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

6.482

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Device Operation - Showing Mixed Load, Burst,

DeselectandNOOPCycles⁽²⁾

CE^{(1 )}

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

H

X

H

X

H

X

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

X

L

X

L

X

Load read

Burst read

Load read

n+1

X

L

n+2

A¹

X

Q⁰

n+3

H

X

L

Q⁰⁺¹Deselect or STOP

n+4

X

L

Q¹

Z

NOOP

n+5

A²

X

L

Load read

Burst read

Deselect or STOP

n+6

X

H

L

Z

n+7

X

Q²

n+8

A³

X

L

Q²⁺¹Load write

n+9

X

L

X

L

X

L

Z

Burst write

Load write

n+10

n+11

n+12

n+13

n+14

n+15

n+16

n+17

n+18

n+19

A⁴

X

L

D³

X

L

H

X

L

X

L

D³⁺¹Deselect or STOP

X

D⁴

Z

NOOP

A⁵

A⁶

A⁷

X

Load write

Load read

Load write

Burst write

Load read

H

L

X

L

Z

L

D⁵

Q⁶

D⁷

X

H

X

L

X

L

A⁸

X

L

X

L

X

L

D⁷⁺¹Burst read

A⁹

Q⁸

Load write

5313 tbl 12

NOTES:

1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

2. H = High; L = Low; X = Don’t Care; Z = High Impedance.

ReadOperation⁽¹⁾

CE^{(2 )}

L

CEN

BW

OE

x

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

H

X

L

X

L

X

L

X

Address and Control meet setup

Clock Setup Valid

n+1

n+2

X

Q⁰

Contents of Address A⁰Read Out

5313 tbl 13

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.42

9

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Burst Read Operation⁽¹⁾

CE^{(2 )}

L

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

H

X

H

X

H

L

H

L

X

L

X

Address and Control meet setup

Clock Setup Valid, Advance Counter

Address A⁰Read Out, Inc. Count

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

X

L

X

Q⁰

X

Q⁰⁺¹Address A⁰⁺¹Read Out, Inc. Count

X

Q⁰⁺²

Q⁰⁺³

Q⁰

Address A⁰⁺²Read Out, Inc. Count

Address A⁰⁺³Read Out, Load A¹

Address A⁰Read Out, Inc. Count

Address A¹Read Out, Inc. Count

A¹

X

H

L

X

L

X

Q¹

A²

Q¹⁺¹Address A¹⁺¹Read Out, Load A²

5313 tbl 14

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE¹= L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Write Operation⁽¹⁾

CE^{(2 )}

L

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

L

X

L

X

L

X

Address and Control meet setup

Clock Setup Valid

n+1

n+2

X

D⁰

Write to Address A⁰

5313 tbl 15

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Burst Write Operation⁽¹⁾

CE^{(2 )}

L

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

L

X

L

H

L

X

Address and Control meet setup

Clock Setup Valid, Inc. Count

Address A⁰Write, Inc. Count

Address A⁰⁺¹Write, Inc. Count

Address A⁰⁺²Write, Inc. Count

Address A⁰⁺³Write, Load A¹

Address A⁰Write, Inc. Count

Address A¹Write, Inc. Count

Address A¹⁺¹Write, Load A²

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

X

L

X

D⁰

X

D⁰⁺¹

D⁰⁺²

D⁰⁺³

D⁰

X

A¹

X

L

H

L

X

L

X

D¹

A²

D¹⁺¹

5313 tbl 16

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.1402

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Read Operation with Clock Enable Used⁽¹⁾

CE^{(2 )}

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

H

X

H

X

H

L

X

L

X

L

H

L

H

L

X

L

X

Address and Control meet setup

Clock n+1 Ignored

n+1

n+2

n+3

n+4

n+5

n+6

n+7

X

L

A¹

X

Clock Valid

X

L

Q⁰

Q¹

Q²

Clock Ignored. Data Q⁰is on the bus.

Address A⁰Read out (bus trans.)

Address A¹Read out (bus trans.)

Address A²Read out (bus trans.)

X

A²

A³

A⁴

L

5313 tbl 17

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Write Operation with Clock Enable Used⁽¹⁾

CE^{(2 )}

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

L

X

L

X

L

X

L

X

L

H

L

H

L

X

L

X

L

X

Address and Control meet setup.

Clock n+1 Ignored.

Clock Valid.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

X

L

A¹

X

L

X

Clock Ignored.

X

Clock Ignored.

A²

A³

A⁴

D⁰

D¹

D²

Write Data D⁰

L

Write Data D¹

L

Write Data D²

5313 tbl 18

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.42

11

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Read Operation with Chip Enable Used⁽¹⁾

CE^{(2 )}

H

L

(3 )

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

Comments

I/O

n

X

H

X

H

X

H

X

L

X

L

?

Deselected.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

Deselected.

A⁰

X

Z

Address and Control meet setup.

Deselected or STOP.

H

L

Z

A¹

X

Q⁰

Z

Address A⁰Read out. Load A¹.

Deselected or STOP.

H

L

X

L

X

Q¹

Z

Address A¹Read out. Deselected.

Address and control meet setup.

Deselected or STOP.

A²

X

L

H

Z

X

Q²

Address A²Read out. Deselected.

5313 tbl 19

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

Write Operation with Chip Enable Used⁽¹⁾

CE^{(2 )}

H

L

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

X

L

X

L

X

?

Deselected.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

Deselected.

A⁰

X

Z

Address and Control meet setup.

Deselected or STOP.

X

L

H

L

X

L

Z

A¹

X

D⁰

Z

Address D⁰Write in. Load A¹.

Deselected or STOP.

X

L

H

L

X

L

X

D¹

Z

Address D¹Write in. Deselected.

Address and control meet setup.

Deselected or STOP.

A²

X

H

X

Z

X

D²

Address D²Write in. Deselected.

5313 tbl 20

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.1422

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 2.5V±5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

V^DD= Max., V^IN= 0V to V^DD

5

µA

(1 )

___

LBO, JTAG and ZZ Input Leakage Current

Output Leakage Current

Output Low Voltage

|I^LI|

V^DD= Max., V^IN= 0V to V^DD

V^OUT= 0V to V^DDQ, Device Deselected

I^OL= +6mA, V^DD= Min.

30

5

µA

V

|I^LO|

V^OL

V^OH

0.4

___

Output High Voltage

I^OH= -6mA, V^DD= Min.

2.0

V

5313 tbl 21

NOTE:

1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD, and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾(VDD = 2.5V±5%)

225MHz

200MHz

166MHz

150MHz

133MHz

100MHz

Symbol

Parameter

Test Conditions

Unit

Com'l Only Com'l Only Com'l Ind Com'l Ind Com'l Ind Com'l Ind

Device Selected, Outputs Open,

Operating Power

Supply Current

DD

I

DD

ADV/LD = X, V = Max.,

315

40

90

60

40

275

40

80

60

40

245 265

215

40

60

40

235

60

80

60

195 215 175

195

60

65

80

60

mA

(2)

IN

IH

IL

MAX

V

> V or < V , f = f

Device Deselected, Outputs Open,

CMOS Standby Power

Supply Current

SB1

I

DD

IN

HD

LD

V

= Max., V > V or < V ,

40

70

60

40

60

90

80

60

40

50

60

40

60

70

80

60

40

45

60

40

mA

(2,3)

f = 0

Device Deselected, Outputs Open,

Clock Running Power

Supply Current

SB2

I

DD

IN

HD

LD

V

= Max., V > V or < V ,

(2.3)

MAX

f = f

Device Selected, Outputs Open,

Idle Power

Supply Current

SB3

I

IH DD

CEN > V , V = Max.,

(2,3)

IN

HD

LD

MAX

V

> V or < V , f = f

Device Selected, Outputs Open,

Full Sleep Mode

Supply Current

ZZ

I

IH DD

CEN < V , V = Max.,

mA

(2,3)

IN

HD

LD

MAX

HD

,ZZ > V

V

> V or < V , f = f

5313 tbl 22

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.

AC Test Load

AC Test Conditions

Input Pulse Levels

VDDQ/2

0 to 2.5V

2ns

50Ω

Input Rise/Fall Times

I/O

Z0 = 50Ω

,

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

(V /2)

DDQ

5313 drw 04

Figure 1. AC Test Load

6

5

4

3

(V /2)

DDQ

See Figure 1

•

5313 tbl 23

∆tCD

(Typical, ns)

2

•

1

•

,

20 30 50

80 100

Capacitance (pF)

200

5313 drw 05

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

13

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics (VDD = 2.5V +/-5%, Commercial and Industrial

Temperature Ranges)

225MHz

200MHz

166MHz

150MHz

133MHz

100MHz

Symbol

Parameter

Min. Max. Min. Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Unit

____

tCY C

(1)

Clock Cycle Time

4.4

5

6

6.7

7.5

10

ns

____

Clock Frequency

225

200

166

150

133

100

MHz

tF

____

(2)

Clock High Pulse Width

Clock Low Pulse Width

1.8

2.0

2.2

3.2

ns

t_CH

____

(2)

tCL

Output Parameters

____

tCD

Clock High to Valid Data

3.0

3.2

3.5

3.8

4.2

5

ns

____

tCDC

Clock High to Data Change

Clock High to Output Active

1.0

1.5

____

(3,4,5)

tCL Z

ns

(3,4,5)

Clock High to Data High-Z

1.0

3

1.0

3

1.0

3

1.5

3

1.5

3

1.5

3.3

ns

tCHZ

____

tOE

Output Enable Access Time

Output Enable Low to Data Active

3.0

3.2

3.5

3.8

4.2

5

____

(3,4)

tOLZ

0

____

(3,4)

tOHZ

Output Enab le High to Data High-Z

3.0

3.2

3.5

3.8

4.2

5

ns

Set Up Times

____

tSE

t_SA

Clock Enable Setup Time

1.4

1.5

1.7

2.0

ns

Address Setup Time

Data In Setup Time

____

tSD

1.4

1.5

1.7

2.0

ns

____

tSW

tSADV

tSC

Read/Write (R/W) Setup Time

1.4

1.5

1.7

2.0

ns

Advance/Load (ADV/LD) Setup Time

Chip Enable/Select Setup Time

Byte Write Enable (BWx) Setup Time

tSB

Hold Times

tHE

____

Clock Enable Hold Time

Address Hold Time

0.4

0.5

ns

tHA

tHD

Data In Hold Time

tHW

Read/Write (R/W) Hold Time

tHADV

tHC

Advance/Load (ADV/ ) Hold Time

LD

Chip Enable/Select Hold Time

tHB

Byte Write Enable (BWx) Hold Time

ns

5313 tbl 24

NOTES:

1. tF = 1/tCYC.

2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.

3. Transition is measured ±200mV from steady-state.

4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.

5. Toavoidbuscontention,theoutputbuffersaredesignedsuchthattCHZ (deviceturn-off)isfasterthantCLZ(deviceturn-on)atagiventemperatureandvoltage.Thespecsasshown

donotimplybuscontentionbecausetCLZisaMin.parameterthatisworsecaseattotallydifferenttestconditions(0deg.C,2.625V)thantCHZ,whichisaMax.parameter(worsecase

at 70 deg. C, 2.375V).

6.1442

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle^(1,2,3,4)

,

.

6.42

15

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycles^(1,2,3,4,5)

,

.

6.1462

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Read and Write Cycles^(1,2,3)

,

6.42

17

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of CEN Operation^(1,2,3,4)

,

6.1482

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of CS Operation^(1,2,3,4)

,

6.42

19

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

JTAG Interface Specification

t^JCYC

Commercial and Industrial Temperature Ranges

tJR

tJF

tJCL

tJCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

t^JDC

t^JS

t^JH

Device Outputs⁽²⁾/

TDO

tJRSR

t^JCD

3)

(

x

TRST

M5313 drw 01

tJRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

JTAG AC Electrical

Characteristics^(1,2,3,4)

Symbol

t^JCYC

t^JCH

t^JCL

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

40

Max.

Units

ns

ScanRegisterSizes

____

Register Name

Instruction (IR)

Bit Size

____

ns

4

1

40

ns

Bypass (BYR)

(1 )

____

t^JR

5

ns

JTAG Identification (JIDR)

Boundary Scan (BSR)

32

(1 )

____

t^JF

5

ns

Note (1)

____

t^JRST

t^JRSR

t^JCD

t^JDC

t^JS

50

ns

I5313 tbl 03

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

50

ns

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

____

20

ns

____

0

ns

____

25

ns

t^JH

JTAG Hold

ns

I5313 tbl 01

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.2402

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions

Instruction Field

Revision Number (31:28)

Value

Description

0x2

0x220, 0x222

0x33

Reserved for version number.

IDT Device ID (27:12)

Defines IDT part number 71T75602 and 71T75802, respectively.

Allows unique identification of device vendor as IDT.

Indicates the presence of an ID register.

IDT JEDEC ID (11:1)

ID Register Indicator Bit (Bit 0)

1

I5313 tbl 02

AvailableJTAGInstructions

Instruction

Description

OPCODE

Forces contents of the boundary scan cells onto the device outputs⁽¹⁾.

Places the boundary scan register (BSR) between TDI and TDO.

EXTEST

0000

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs⁽²⁾and outputs⁽¹⁾to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the boundary scan cells via the TDI.

SAMPLE/PRELOAD

0001

Loads the JTAG ID register (JIDR) with the vendor ID code and places

the register between TDI and TDO.

DEVICE_ID

HIGHZ

0010

0011

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

RESERVED

0100

0101

0110

0111

Several combinations are reserved. Do not use codes other than those

identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,

VALIDATE and BYPASS instructions.

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

CLAMP

1000

RESERVED

1001

1010

1011

1100

Same as above.

Automatically loaded into the instruction register whenever the TAP

controller passes through the CAPTURE-IR state. The lower two bits '01'

are mandated by the IEEE std. 1149.1 specification.

VALIDATE

1101

RESERVED

BYPASS

Same as above.

1110

1111

The BYPASS instruction is used to truncate the boundary scan register

as a single bit in length.

I5313 tbl 04

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

6.42

21

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

100-Pin Thin Quad Flatpack (TQFP)Package Diagram Outline

6.2422

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

119 Ball Grid Array (BGA) Package Diagram Outline

6.42

23

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of OE Operation⁽¹⁾

OE

t_OE

tOHZ

t_OLZ

DATAOUT

Valid

,

5313 drw 11

NOTE:

1. A read operation is assumed to be in progress.

OrderingInformation

IDT

XXXX

S

XX

X

Device

Type

Power Speed

Package

Blank Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

I

PF

BG

100-Pin Plastic Thin Quad Flatpack (TQFP)

119 Ball Grid Array (BGA)

225

200

166

150

133

100

Clock Frequency in Megahertz

IDT71T75602

IDT71T75802

512Kx36 Pipelined ZBT SRAM

1Mx18 Pipelined ZBT SRAM

5313 drw 12

6.2442

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Datasheet Document History

Rev

0

1

Date

04/20/00

05/25/00

Pages

Description

CreatedNewDatasheet

Added166MHzspeedgrade offering

Corrected error in ZZ Sleep Mode

Pg.1,14,15,25

Pg. 1,2,14

Pg. 23

AddBQ165PackageDiagramOutline

Pg. 24

Pg. 25

Pg. 1,2,24

Pg. 7

Pg. 23

Corrected119BGAPackageDiagramOutline.

Correctedtopmarkonorderinginformation

RemovedreferenceofBQ165Package

Removedpage ofthe 165BGA pinconfiguration

Removedpageofthe165BGApackagediagramoutline

Corrected 3.3V to 2.5V in Note 2

2

08/23/01

3

4

5

10/16/01

10/29/01

12/21/01

Pg. 6

Pg. 13

Pg. 4-6

Pg. 14

ImprovedDCElectricalcharacteristics-parametersimproved:Icc,ISB2,ISB3,IZZ.

AddedclarificationtoJTAGpins,allowforNC. Added36Maddress pinlocations.

Revised 166MHz tCDC(min), tCLZ(min) and tCHZ(min) to 1.0ns

06/07/02

Pg. 1-3,6,13,20,21 AddedcompleteJTAGfunctionality.

Pg. 2,13

Added notes for ZZ pin internal pulldown and ZZ leakage current.

Pg. 13,14,24

Added200MHzand225MHztoDCandACElectricalCharacteristics. Updatedsupplycurrentfor

Idd, ISB1, ISB3 and Izz.

6

7

8

11/19/02

05/23/03

04/01/04

Pg.1-24

Pg.13

ChangeddatasheetfromAdvancedInformationtofinalrelease.

UpdatedDCElectricalcharacteristicstemperatureandvoltagerangetable.

Pg.4,5,13,14,24 AddedI-temptothedatasheet.

Pg.5

Pg. 1

Pg. 4,5

Pg. 6

Pg. 23

Updated165BGACapacitancetable.

Updatedlogowithnewdesign.

Clarifiedambientandcaseoperatingtemperatures.

Updated pin I/O number order for the 119 BGA.

Updated119BGAPackageDiagramDrawing.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Rd

San Jose, CA 95138

for SALES:

for Tech Support:

sramhelp@idt.com

800-345-7015 or

408/284-4555

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc. Allbrandsorproductsarethetrademarksorregisteredtrademarksoftheirrespectiveowners.

ZBT^®andZeroBusTurnaroundaretrademarksofIntegratedDeviceTechnology,Inc.andthearchitectureissupportedbyMicronTechnologyandMotorolaInc.

6.42

25


型号：	IDT71T75602S200PFG8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	ZBT SRAM, 512KX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP-100 时钟静态存储器内存集成电路
文件：	总25页 (文件大小：639K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71T75602S200PFG8 [IDT]

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