IDT71V016 [IDT]
3.3V CMOS Static RAM 1 Meg (64K x 16-Bit); 3.3V CMOS静态RAM 1兆欧（ 64K ×16位）
| 型号： | IDT71V016 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) |
| 文件： | 总9页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71V016SA
Features
Description
◆
64K x 16 advanced high-speed CMOS Static RAM
TheIDT71V016isa1,048,576-bithigh-speedStaticRAMorganized
as64Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneeds.
◆
Equal access and cycle times
— Commercial:10/12/15/20ns
— Industrial:12/15/20ns
One Chip Select plus one Output Enable pin
◆
◆
Bidirectional data inputs and outputs directly
The IDT71V016 has an output enable pin which operates as fast
as 5ns, with address access times as fast as 10ns. All bidirectional
inputsandoutputsoftheIDT71V016areLVTTL-compatibleandoperation
isfromasingle3.3Vsupply.Fullystaticasynchronouscircuitryisused,
requiringnoclocks orrefreshforoperation.
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
◆
◆
◆
◆
Available in 44-pin Plastic SOJ, 44-pin TSOP, and
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
48-Ball Plastic FBGA packages
Functional Block Diagram
Output
Enable
Buffer
OE
Address
Buffers
Row / Column
Decoders
A0 – A15
I/O15
High
Byte
I/O
8
8
Chip
Enable
Buffer
CS
Buffer
I/O8
Sense
Amps
and
Write
Drivers
16
64K x 16
Memory
Array
Write
Enable
Buffer
WE
I/O7
I/O0
Low
Byte
I/O
8
8
Buffer
BHE
BLE
Byte
Enable
Buffers
3834 drw 01
JUNE 2002
1
©2000 IntegratedDeviceTechnology,Inc.
DSC-3834/06
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
1
2
3
4
5
6
A
B
C
D
E
A0
A1
A2
NC
BLE
OE
A
4
1
A
A
A
5
6
7
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
2
A2
3
I/O8
I/O9
VSS
A3
A5
A4
A6
I/O0
I/O2
VDD
VSS
I/O6
I/O7
BHE
I/O10
I/O11
I/O12
I/O13
NC
CS
A
1
4
OE
A0
5
BHE
BLE
I/O15
I/O14
I/O13
I/O12
I/O1
I/O3
I/O4
I/O5
CS
I/O
I/O
I/O
6
0
7
NC
NC
A14
A12
A9
A7
1
8
2
9
VDD
I/O14
I/O15
NC
NC
A15
A13
A10
I/O3
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
VDD
V
SS
DD
VSS
V
F
I/O
I/O
I/O
I/O
WE
4
I/O11
I/O10
5
G
H
WE
6
I/O
I/O
NC
9
7
8
A8
A11
NC
A15
A14
A13
A12
A
A
A
A
8
3834 tbl 02a
FBGA (BF48-1)
Top View
9
10
11
NC
NC
Pin Description
0
15
A – A
Address Inputs
Input
3834 drw 02
Chip Select
Input
Input
Input
Input
Input
I/O
CS
WE
OE
BHE
BLE
0
SOJ/TSOP
Top View
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
15
I/O – I/O
DD
V
Power
Gnd
SS
V
Ground
3834 tbl 01
Truth Table(1)
0
7
8
15
CS
H
L
L
L
L
L
L
L
L
OE
X
L
WE
X
H
H
H
L
BLE
BHE
X
H
L
I/O -I/O
I/O -I/O
High-Z
High-Z
Function
X
L
High-Z
Deselected – Standby
OUT
DATA
Low Byte Read
High Byte Read
Word Read
OUT
DATA
L
H
L
High-Z
OUT
OUT
DATA
L
L
DATA
IN
IN
X
X
X
H
X
L
L
DATA
DATA
Word Write
IN
L
L
H
L
DATA
High-Z
High-Z
High-Z
High-Z
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
IN
L
H
X
H
DATA
H
X
X
H
High-Z
High-Z
3834 tbl 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
6.42
2
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended Operating
Temperature and Supply Voltage
Symbol
Rating
Value
Unit
DD
V
Supply Voltage Relative to
SS
V
–0.5 to +4.6
V
SS
DD
V
Grade
Temperature
0°C to +70°C
-40°C to +85°C
V
Commercial
Industrial
0V
0V
See Below
DD
IN OUT
V , V
Terminal Voltage Relative
SS
to V
–0.5 to V +0.5
V
See Below
3834 tbl 04
oC
oC
W
BIAS
T
Temperature Under Bias
Storage Temperature
Power Dissipation
–55 to +125
–55 to +125
1.25
STG
T
Recommended DC Operating
Conditions
T
P
OUT
I
DC Output Current
50
mA
Symbol
Parameter
Supply Voltage
Min.
3.15
3.0
Typ.
3.3
Max.
3.6
Unit
V
3834 tbl 03
(1)
NOTE:
VDD
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
(2)
VDD
Supply Voltage
Ground
3.3
3.6
V
Vss
VIH
VIL
0
0
0
V
____
Input High Voltage
Input Low Voltage
2.0
VDD+0.3(3)
0.8
V
–0.3(4)
V
____
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
3834 tbl 05
NOTES:
1. For 71V016SA10 only.
2. For all speed grades except 71V016SA10.
3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
6
7
pF
CI/O
pF
3834 tbl 06
NOTE:
1. Thisparameterisguaranteedbydevicecharacterization,butnotproductiontested.
DCElectrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V016SA
Symbol
|ILI|
Parameter
Input Leakage Current
Test Condition
VDD = Max., VIN = VSS to VDD
VDD = Max., CS = VIH, VOUT = VSS to VDD
IOL = 8mA, VDD = Min.
Min.
Max.
Unit
µA
µA
V
___
___
___
5
5
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
VOL
0.4
___
VOH
IOH = –4mA, VDD = Min.
2.4
V
3834 tbl 07
DC Electrical Characteristics(1,2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71V016SA10
71V016SA12
71V016SA15
71V016SA20
Com'l Only
160
Com'l
150
Ind
160
--
Com'l
130
Ind
Com'l
120
Ind
120
--
Symbol
Parameter
Dynamic Operating Current
Unit
Max.
130
--
mA
CC
I
(3)
(3)
Typ.(4)
125
120
110
110
LC
DD
MAX
CS ≤ V , Outputs Open, V = Max., f = f
Dynamic Standby Power Supply Current
mA
SB
I
45
10
40
10
45
10
35
10
35
10
30
10
30
10
HC
DD
MAX
CS ≥ V , Outputs Open, V = Max., f = f
Full Standby Power Supply Current (static)
mA
SB1
I
(3)
HC
DD
CS ≥ V , Outputs Open, V = Max., f = 0
NOTES:
3834 tbl 08
1. Allvaluesaremaximumguaranteedvalues.
2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
4. Typical values are measured at 3.3V, 25°C and with equal read and write cycles.
6.42
3
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3834 tbl 09
AC Test Loads
3.3V
+1.5V
50
320
Ω
Ω
Ω
OUT
DATA
Z0 = 50Ω
I/O
5pF*
350
30pF
3834 drw 03
3834 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
6
•
∆
t
AA, ACS
t
5
4
3
(Typical, ns)
•
•
2
1
•
•
•
·
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
3834 drw 05
Figure 3. Output Capacitive Derating
6.42
4
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V016SA10(2)
71V016SA12
71V016SA15
71V016SA20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
RC
t
Read Cycle Time
10
12
15
20
ns
ns
ns
ns
____
____
____
____
AA
t
Address Access Time
10
12
15
20
____
____
____
____
ACS
t
Chip Select Access Time
Chip Select Low to Output in Low-Z
10
12
15
20
____
____
____
____
(1)
4
4
5
5
CLZ
t
____
____
____
____
(1)
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
CHZ
t
____
____
____
____
tOE
5
6
7
8
____
____
____
____
(1)
0
0
0
0
OLZ
t
____
____
____
____
(1)
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
ns
OHZ
t
tOH
4
—
4
—
4
—
4
—
____
BE
t
—
5
—
6
—
7
8
____
____
____
____
(1)
0
0
0
0
BLZ
t
____
____
____
____
(1)
Byte Enable High to Output in High-Z
5
6
6
8
ns
tBHZ
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
WC
t
Write Cycle Time
10
7
7
7
0
0
7
5
0
12
8
8
8
0
0
8
6
0
15
10
10
10
0
20
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AW
t
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
tCW
BW
t
AS
t
WR
t
Address Hold from End of Write
Write Pulse Width
0
0
WP
t
10
7
12
9
DW
t
Data Valid to End of Write
Data Hold Time
DH
t
0
0
____
____
____
____
(1)
Write Enable High to Output in Low-Z
3
3
3
3
OW
t
____
____
____
____
(1)
Write Enable Low to Output in High-Z
5
6
6
8
ns
tWHZ
NOTES:
3834 tbl 10
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 0°C to +70°C temperature range only.
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC
ADDRESS
tAA
tOH
tOH
PREVIOUS DATAOUT VALID
DATAOUT VALID
DATAOUT
NOTES:
3834 drw 06
1. WE is HIGH for Read Cycle.
2. Deviceiscontinuouslyselected,CSisLOW.
3. OE, BHE, and BLE are LOW.
6.42
5
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
tRC
ADDRESS
tAA
tOH
OE
(3)
tOHZ
tOE
(3)
tOLZ
CS
(2)
tACS
(3)
(3)
tCHZ
tCLZ
BLE
BHE,
(2)
(3)
tBE
tBHZ
(3)
tBLZ
DATAOUT
DATA OUTVALID
3834 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. AddressmustbevalidpriortoorcoincidentwiththelaterofCS,BHE,orBLE transitionLOW;otherwisetAA isthelimitingparameter.
3. Transitionismeasured±200mVfromsteadystate.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
tAW
CS
(2)
(5)
tCW
tCHZ
tBHZ
tBW
BHE , BLE
WE
(5)
tWR
tWP
tAS
(5)
tWHZ
(5)
tOW
tDH
(3)
DATAOUT
DATAIN
PREVIOUS DATA VALID
DATA VALID
tDW
DATAIN VALID
3834 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OEis continuouslyHIGH. IfduringaWE controlledwrite cycleOEis LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed
onthe bus forthe requiredtDW. IfOEis HIGHduringaWEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. IftheCSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.42
6
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
(2)
tAS
tCW
tBW
BHE, BLE
tWP
tWR
WE
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
3834 drw 09
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
(2)
tCW
tAS
tBW
BHE, BLE
tWP
tWR
WE
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
3834 drw 10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OEis continuouslyHIGH. IfduringaWE controlledwrite cycleOEis LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed
onthe bus forthe requiredtDW. IfOEis HIGHduringaWEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. IftheCSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.42
7
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
X
IDT 71V016
SA
XX
XXX
X
Device
Type
Power Speed Package
Process/
Temperature
Range
Tape & Reel
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
Y
400-mil SOJ (SO44-1)
PH
BF
400-mil TSOP Type II (SO44-2)
7.0 x 7.0 mm FBGA (BF48-1)
10**
12
15
Speed in nanoseconds
20
** Commercial temperature range only.
3834 drw 11
6.42
8
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
1/7/00
Updatedtonewformat
Pp. 1, 3, 5, 8
Pg. 2
Pg. 6
Pg. 7
Pg. 9
AddedIndustrialTemperaturerangeofferings
Numbered I/Os and address pins on FBGA Top View
RevisedfootnotesonWriteCycleNo.1diagram
Revised footnotes on Write Cycle No. 2 and No. 3 diagrams
AddedDatasheetDocumentHistory
08/30/00
Pg. 3
Tighten ICC and ISB.
Pg. 5
Tighten tCLZ, tCHZ, tOHZ, tBHZ and tWHZ
08/22/01
06/20/02
Pg. 8
Pg. 8
Removedfootnote "available in15ns and20ns only"
Addedtapeandreelfieldtoorderinginformation
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
for Tech Support:
800-345-7015 or 408-727-6116 sramhelp@idt.com
fax: 408-492-8674
www.idt.com
800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
9
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