IDT71V256SA10TP [IDT]
LOW POWER 3.3V CMOS FAST SRAM 256K (32K x 8-BIT); 低功耗3.3V CMOS快速SRAM 256K ( 32K ×8位)型号: | IDT71V256SA10TP |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | LOW POWER 3.3V CMOS FAST SRAM 256K (32K x 8-BIT) |
文件: | 总6页 (文件大小:72K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT71V256SA
LOW POWER
3.3V CMOS FAST SRAM
256K (32K x 8-BIT)
Integrated Device Technology, Inc.
FEATURES
• Ideal for high-performance processor secondary cache
DESCRIPTION
TheIDT71V256SAisa 262,144-bithigh-speedstaticRAM
• Commercial (0° to 70°C) and Industrial (-40° to 85°C) organized as 32K x 8. It is fabricated using IDT’s high-
temperature options
performance, high-reliability CMOS technology.
• Fast access times:
— Commercial: 10/12/15/20ns
— Industrial: 15ns
• Low standby current (maximum):
— 2mA full standby
• Small packages for space-efficient layouts:
— 28-pin 300 mil SOJ
The IDT71V256SA has outstanding low power character-
istics while at the same time maintaining very high perfor-
mance. Address access times of as fast as10 ns are ideal for
3.3V secondary cache in 3.3V desktop designs.
When power management logic puts the IDT71V256SA in
standby mode, its very low power characteristics contribute to
extended battery life. By taking CS HIGH, the SRAM will
automatically go to a low power standby mode and will remain
in standby as long as CS remains HIGH. Furthermore, under
— 28-pin 300 mil plastic DIP (Commercial only)
— 28-pin TSOP Type I
• Produced with advanced high-performance CMOS full standby mode (CS at CMOS level, f=0), power consump-
technology
• Inputs and outputs are LVTTL-compatible
• Single 3.3V(±0.3V) power supply
tion is guaranteed to always be less than 6.6mW and typically
will be much smaller.
The IDT71V256SA is packaged in 28-pin 300 mil SOJ, 28-
pin 300 mil plastic DIP, and 28-pin 300 mil TSOP Type I
packaging.
FUNCTIONAL BLOCK DIAGRAM
A0
VCC
GND
262,144 BIT
MEMORY ARRAY
ADDRESS
DECODER
A14
I/O0
I/O CONTROL
INPUT
DATA
CIRCUIT
I/O7
CS
OE
WE
CONTROL
CIRCUIT
3101 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
MAY 1997
1997 Integrated Device Technology, Inc.
DSC-3101/04
1
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Value
Unit
A
A
A
A
A
A
A
A
A
A
14
12
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
WE
CC
VCC
Supply Voltage
Relative to GND
–0.5 to +4.6
V
2
7
6
5
4
3
2
1
0
0
1
2
3
A
A
A
A
13
4
8
(2)
VTERM
Terminal Voltage
Relative to GND
–0.5 to VCC+0.5
V
5
9
6
11
SO28-5
P28-2
7
TBIAS
TSTG
PT
Temperature Under Bias
Storage Temperature
Power Dissipation
–55 to +125
–55 to +125
1.0
°C
°C
W
OE
8
A10
9
CS
10
11
12
13
14
I/O
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
6
5
4
3
IOUT
DC Output Current
50
mA
NOTES:
3101 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
GND
3101 drw 02
DIP/SOJ
TOP VIEW
2. Input, Output, and I/O terminals; 4.6V maximum.
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A
10
OE
CS
I/O
I/O
I/O
I/O
I/O
A
11
7
6
5
4
3
A
A
9
8
A
13
WE
V
CC
SO28-8
A
A
14
12
GND
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ package)
2
I/O
I/O
I/O
A
A
A
2
1
0
3
A
A
A
A
A
7
6
5
4
3
4
(1)
Symbol
Parameter
Conditions
VIN = 3dV
Max. Unit
5
0
1
2
6
CIN
Input Capacitance
Output Capacitance
6
7
pF
7
8
COUT
VOUT = 3dV
pF
3101 drw 11
NOTE:
3101 tbl 04
TSOP
TOP VIEW
1. This parameter is determined by device characterization, but is not
production tested.
PIN DESCRIPTIONS
Name
Description
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
A0–A14
I/O0–I/O7
CS
Addresses
Data Input/Output
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
GND
VCC
Chip Select
Write Enable
Output Enable
Ground
0V
3.3V ± 0.3V
WE
0V
3.3V ± 0.3V
OE
3101 tbl 05
GND
VCC
Power
3101 tbl 01
RECOMMENDED DC OPERATING
CONDITIONS
TRUTH TABLE(1)
I/O
Function
WE
X
CS
H
OE
X
Symbol
Parameter
Supply Voltage
Supply Voltage
Min. Typ. Max. Unit
High-Z
High-Z
High-Z
Standby (ISB)
Standby (ISB1)
Output Disable
Read
VCC
3.0
0
3.3
0
3.6
0
V
V
V
V
V
X
VHC
L
X
GND
VIH
H
H
L
Input High Voltage - Inputs 2.0
—
—
—
5.0
H
L
DOUT
DIN
VIH
Input High Voltage - I/O
Input Low Voltage
2.0
–0.3(1)
Vcc+0.3
0.8
L
L
X
Write
NOTE:
1. H = VIH, L = VIL, X = Don’t Care
3101 tbl 02
VIL
NOTE:
3101 tbl 06
1. VIL (min.) = –2.0V for pulse width less than 5ns, once per cycle.
2
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS(1, 2)
(VCC = 3.3V ± 0.3V, VLC = 0.2V, VHC = VCC - 0.2V)
Symbol
Parameter
71V256SA10(3) 71V256SA12(3) 71V256SA15 71V256SA20(3) Unit
ICC
Dynamic Operating Current CS ≤ VIL, Outputs
Open, VCC = Max., f = fMAX
100
20
2
90
20
2
85
20
2
85
20
2
mA
mA
mA
(2)
ISB
Standby Power Supply Current (TTL Level)
CS = VIH, VCC = Max., Outputs Open, f = fMAX
(2)
ISB1
Full Standby Power Supply Current (CMOS Level)
CS ≥ VHC, VCC = Max., Outputs Open, f = 0(2)
VIN ≤ VLC or VIN ≥ VHC
,
NOTES:
3101 tbl 07
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs cycling at fmax; f = 0 means that no inputs are cycling.
3. Commercial temperature range only.
DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V± 0.3V
IDT71V256SA
Symbol
|ILI|
Parameter
Test Condition
Min.
—
Typ.
—
Max.
2
Unit
Input Leakage Current
VCC = Max., VIN = GND to VCC
µA
|ILO|
Output Leakage Current VCC = Max., CS= VIH, VOUT = GND to VCC
—
—
2
µA
V
VOL
Output Low Voltage
Output High Voltage
IOL = 8mA, VCC = Min.
IOH = –4mA, VCC = Min.
—
—
0.4
—
VOH
2.4
—
V
3101 tbl 08
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
3ns
1.5V
1.5V
See Figures 1 and 2
3101 tbl 09
3.3V
3.3V
320
320Ω
Ω
DATAOUT
DATAOUT
350
Ω
350Ω
30pF*
5pF*
3101 drw 04
3101 drw 05
Figure 2. AC Test Load
Figure 1. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
*Includes scope and jig capacitances
3
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ± 0.3V)
(2)
(2)
(2)
71V256SA10
71V256SA12
71V256SA15
71V256SA20
Symbol
Parameter
Max.
Min.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
tAA
Read Cycle Time
Address Access Time
10
—
—
5
—
10
10
—
8
12
—
—
5
—
12
12
—
8
15
—
—
5
—
15
15
—
9
20
—
—
5
—
20
20
—
10
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
tACS
Chip Select Access Time
(1)
tCLZ
tCHZ
tOE
Chip Select to Output in Low-Z
Chip Select to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(1)
0
0
0
0
—
3
6
—
3
6
—
0
7
—
0
(1)
tOLZ
—
6
—
6
—
7
—
8
(1)
tOHZ
tOH
2
2
0
0
3
—
3
—
3
—
3
—
Write Cycle
tWC
tAW
tCW
Write Cycle Time
10
9
9
0
9
0
6
0
4
1
—
—
—
—
—
—
—
—
—
8
12
9
9
0
9
0
6
0
4
1
—
—
—
—
—
—
—
—
—
8
15
10
10
0
—
—
—
—
—
—
—
—
—
9
20
15
15
0
—
—
—
—
—
—
—
—
—
10
ns
ns
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
ns
tAS
ns
tWP
tWR
Write Pulse Width
10
0
15
0
ns
Write Recovery Time
ns
tDW
tDH
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End-of-Write
Write Enable to Output in High-Z
7
8
ns
0
0
ns
(1)
tOW
4
4
ns
(1)
tWHZ
1
1
ns
NOTE:
3101 tbl 10
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
2. Commercial temperature range only.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
tOH
OE
tOE
(2)
(2)
(2)
tOHZ
tCHZ
tOLZ
CS
tACS
(2)
tCLZ
DATAOUT
DATA VALID
3101 drw 06
NOTES:
1. WE is HIGH for Read cycle.
2. Transition is measured ±200mV from steady state.
4
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
PREVIOUS DATA VALID
DATA VALID
DATAOUT
3101 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
t
ACS
(5)
CLZ
(5)
CHZ
t
t
DATA VALID
DATAOUT
3101 drw 08
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
CONTROLLED TIMING)(1, 2, 3, 5, 7)
WE
t
WC
ADDRESS
OE
(6)
t
OHZ
t
AW
CS
(7)
t
WP
t
WR
t
AS
WE
(6)
(6)
t
WHZ
t
OW
DATAOUT
DATAIN
(4)
(4)
t
DW
t DH
DATA VALID
3101 drw 09
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified tWP.
5
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CONTROLLED TIMING)(1, 2, 3, 4)
CS
tWC
ADDRESS
tAW
CS
(5)
tAS
tCW
tWR
WE
tDW
t DH
DATA VALID
DATAIN
3101 drw 10
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified tWP.
ORDERING INFORMATION - COMMERCIAL
IDT71V256
SA
XX
X
X
Power Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
Y
TP
PZ
300 mil SOJ (SO28-5)
300 mil Plastic DIP (P28-2)
TSOP Type I (SO28-8)
10
12
15
20
Speed in nanoseconds
3101 drw 11
ORDERING INFORMATION - INDUSTRIAL
IDT71V256
SA
XX
X
X
Power Speed
Package
Process/
Temperature
Range
I
Industrial (-40°C to +85°C)
Y
PZ
300 mil SOJ (SO28-5)
TSOP Type I (SO28-8)
Speed in nanoseconds
15
3101 drw 12
6
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