IDT71V256SA15Y8 [IDT]
Cache SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.300 INCH, SOJ-28;
| 型号： | IDT71V256SA15Y8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Cache SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.300 INCH, SOJ-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Lower Power
IDT71V256SA
3.3V CMOS Fast SRAM
256K (32K x 8-Bit)
Features
Description
◆
Ideal for high-performance processor secondary cache
Commercial (0°C to +70°C) and Industrial (–40°C to +85°C)
temperature range options
TheIDT71V256SAisa 262,144-bithigh-speedstaticRAMorganized
as32Kx8.ItisfabricatedusingIDT’shigh-performance,high-reliability
CMOStechnology.
◆
◆
◆
◆
Fast access times:
TheIDT71V256SAhasoutstandinglowpowercharacteristicswhile
at the same time maintaining very high performance. Address access
times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V
desktopdesigns.
Whenpowermanagementlogicputs the IDT71V256SAinstandby
mode,itsverylowpowercharacteristicscontributetoextendedbatterylife.
BytakingCSHIGH,theSRAMwillautomaticallygotoalowpowerstandby
modeandwillremaininstandbyaslongasCSremainsHIGH.Further-
more,underfullstandbymode(CSatCMOSlevel,f=0),powerconsump-
tionisguaranteedtoalwaysbelessthan6.6mWandtypicallywillbemuch
smaller.
– CommercialandIndustrial:10/12/15/20ns
Low standby current (maximum):
– 2mAfullstandby
Small packages for space-efficient layouts:
– 28-pin 300 mil SOJ
– 28-pin TSOP Type I
Produced with advanced high-performance CMOS
technology
Inputs and outputs are LVTTL-compatible
Single 3.3V(±0.3V) power supply
◆
◆
◆
TheIDT71V256SAispackagedina28-pin300milSOJanda28-pin
300 mil TSOP Type I.
FunctionalBlockDiagram
A0
VCC
GND
262,144 BIT
MEMORY ARRAY
ADDRESS
DECODER
A14
I/O
0
I/O CONTROL
INPUT
DATA
CIRCUIT
I/O7
,
CS
OE
CONTROL
CIRCUIT
3101 drw 01
WE
JANUARY 2004
1
DSC-3101/08
©2004IntegratedDeviceTechnology,Inc.
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
TruthTable(1)
PinConfigurations
Function
Standby (ISB
I/O
WE
CS
OE
X
X
H
L
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
A
14
12
V
WE
CC
X
H
High-Z
High-Z
High-Z
)
2
3
A
A
7
6
5
4
3
2
1
0
A
A
A
A
13
X
VHC
Standby (ISB1
Output Disable
Read
)
4
8
5
A
A
A
A
A
A
9
H
L
L
L
6
11
SO28-5
7
OE
H
DOUT
8
A10
L
X
DIN
Write
9
CS
I/O
I/O
I/O
I/O
10
11
12
13
14
7
3101 tbl 02
I/O
I/O
I/O
GND
0
NOTE:
1. H = VIH, L = VIL, X = Don’t Care
6
1
5
2
4
I/O
3
,
AbsoluteMaximumRatings(1)
3101 drw 02
DIP/SOJ
Symbol
Rating
Com'l.
Unit
Top View
VCC
Supply Voltage
Relative to GND
-0.5 to +4.6
V
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A11
A10
CS
(2)
TERM
V
Terminal Voltage
Relative to GND
-0.5 to VCC+0.5
V
I/O
I/O
I/O
I/O
I/O
7
A9
6
5
4
3
A8
T
BIAS
STG
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
1.0
oC
oC
W
A13
WE
V
A
A
CC
14
12
SO28-8
T
GND
2
I/O
I/O
I/O
A
A
A
2
1
0
P
T
3
A
7
6
5
4
3
4
A
A
A
A
,
IOUT
DC Output Current
50
mA
5
0
1
2
6
3101 tbl 03
NOTES:
7
8
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
3101 drw 03
TSOP
Top View
2. Input, Output, and I/O terminals; 4.6V maximum.
PinDescriptions
Name
Description
Capacitance
A
0
- A14
Addresses
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max.
Unit
I/O
0
- I/O
7
CIN
V
6
pF
CS
COUT
V
7
pF
WE
OE
3101 tbl 04
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
GND
VCC
Power
3101 tbl 01
RecommendedOperating
TemperatureandSupplyVoltage
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND
Vcc
0V
3.3V ± 0.3V
3.3V ± 0.3V
0V
3101 tbl 05
2
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
RecommendedDCOperating
Conditions
Symbol
Parameter
Supply Voltage
GND Ground
Min. Typ.
Max.
3.6
0
Unit
V
V
CC
3.0
0
3.3
0
V
____
V
IH
IH
IL
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
5.0
V
____
____
V
2.0
V
CC +0.3
V
V
-0.3(1)
0.8
V
3101 tbl 06
NOTE:
1. VIL (min.) = –2.0V for pulse width less than 5ns, once per cycle.
DCElectricalCharacteristics(1)
(VCC = 3.3V ± 0.3V, VLC = 0.2V, VHC = VCC - 0.2V, Commercial and Industrial Temperture Ranges)
Symbol
Parameter
71V256SA10
71V256SA12
71V256SA15
71V256SA20
Unit
ICC
Dynamic Operating Current CS < VIL, Outputs
100
90
85
85
mA
(2)
Open, VCC = Max., f = fMAX
I
SB
Standby Power Supply Current (TTL Level)
20
2
20
2
20
2
20
2
mA
mA
(2)
CS = VIH, VCC = Max., Outputs Open, f = fMAX
ISB1
Full Standby Power Supply Current (CMOS Level)
CS > VHC, VCC = Max., Outputs Open, f = 0(2),
VIN < VLC or VIN > VHC
3101 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs cycling at fMAX; f = 0 means that no inputs are cycling.
DC Electrical Characteristics
(VCC = 3.3V± 0.3V)
IDT71V256SA
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
CC = Max., VIN = GND to VCC
CC = Max., CS = VIH, VOUT = GND to VCC
OL = 8mA, VCC = Min.
OH = -4mA, VCC = Min.
Min.
Typ.
Max.
2
Unit
µA
µA
V
___
___
|ILI|
V
___
___
___
___
___
|ILO
|
V
2
VOL
I
0.4
___
VOH
Output High Voltage
I
2.4
V
3101 tbl 08
6.42
3
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
1.5V
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
See Figures 1 and 2
3101 tbl 09
3.3V
3.3V
320Ω
320Ω
OUT
DATA
OUT
DATA
350Ω
30pF*
350Ω
5pF*
,
,
3101 drw 04
3101 drw 05
Figure 2. AC Test Load
Figure 1. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
*Includes scope and jig capacitances
AC Electrical Characteristics
(VCC = 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)
71V256SA10
71V256SA12
71V256SA15
71V256SA20
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
Read Cycle
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
10
12
15
20
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
10
12
15
20
____
____
____
____
t
10
12
15
20
____
____
____
____
(1)
CLZ
5
5
5
5
t
(1)
Chip Select to Output in High-Z
Output Enable to Output Valid
0
8
0
8
0
9
0
10
ns
ns
ns
ns
ns
t
CHZ
____
____
____
____
tOE
6
6
7
8
(1)
(1)
____
____
____
____
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
3
2
3
3
2
3
0
0
3
0
0
3
t
OLZ
6
6
7
8
t
OHZ
____
____
____
____
tOH
Wri te Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
AS
WP
WR
DW
DH
Write Cycle Time
10
9
9
0
9
0
6
0
4
12
9
9
0
9
0
6
0
4
15
10
10
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
t
t
t
Write Pulse Width
10
0
15
0
t
Write Recovery Time
t
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End-of-Write
7
8
t
0
0
____
____
____
____
(1)
OW
4
4
t
(1)
WHZ
Write Enable to Output in High-Z
1
8
1
8
1
9
1
10
ns
t
3101 tbl 10
NOTE:
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
4
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
RC
t
ADDRESS
AA
OH
t
t
OE
OE
t
(2)
(2)
OHZ
t
OLZ
t
CS
ACS
t
(2)
(2)
CHZ
t
CLZ
t
DATAOUT
DATA VALID
,
3101 drw 06
NOTES:
1. WE is HIGH for Read cycle.
2. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cycle No. 2(1,2,4)
RC
t
ADDRESS
AA
t
OH
t
OH
t
PREVIOUS DATA VALID
DATA VALID
DATAOUT
3101 drw 07
,
Timing Waveform of Read Cycle No. 3(1,3,4)
CS
ACS
t
(5)
CHZ
t
(5)
CLZ
t
DATA VALID
DATAOUT
,
3101 drw 08
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
5
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6)
WC
t
ADDRESS
(5)
OHZ
t
OE
tAW
CS
(6)
WP
t
tAS
t WR
WE
(5)
tWHZ
(5)
OW
t
(3)
(3)
DATAOUT
DW
DH
t
t
DATA VALID
DATAIN
3101 drw 09
,
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
spectified tWP.
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,4)
WC
t
ADDRESS
AW
t
CS
(5)
AS
CW
WR
t
t
t
WE
DW
DH
t
t
DATA VALID
DATAIN
3101 drw 10
,
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
spectified tWP.
6
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information — Commercial and Industrial
SA
XX
X
71V256
X
IDT
X
X
Device
Type
Power Speed
Package
Process/ Tape & Reel
Temperature
Range
8
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Blank
I
G
Restricted Hazardous
Substance Device
Y
PZ
300 mil SOJ (SO28-5)
TSOP Type I (SO28-8)
Speed in nanoseconds
* Available in SOJ package only.
3101 drw 11
6.42
7
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
1/7/00
Updatedtonewformat
ExpandedIndustrialTemperatureofferings
Removed28-pin300milplasticDIPpackageoffering
RemovedNoteNo.1fromWriteCycleNo.1diagram;renumberednotes andfootnotes
RevisedOrderingInformation
Pg. 1, 3, 4, 7
Pg. 1, 2, 7
Pg. 6
Pg. 7
Pg. 8
AddedDatasheetDocumentHistory
08/09/00
02/01/01
06/21/02
01/30/04
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
Addedtapeandreeloptiontotheorderinginformation
Added"restrictedhazardoussubstancedevice"toorderinformation.
Pg. 7
Pg. 7
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www.idt.com
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8
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