IDT71V2578S150PFI8 [IDT]
Cache SRAM, 256KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100;
| 型号： | IDT71V2578S150PFI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Cache SRAM, 256KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K X 36, 256K X 18
IDT71V2576
IDT71V2578
3.3VSynchronousSRAMs
2.5V I/O, Pipelined Outputs,
Burst Counter, Single Cycle Deselect
Features
Description
◆
128K x 36, 256K x 18 memory configurations
The IDT71V2576/78 are high-speed SRAMs organized as 128K x
36/256Kx18.TheIDT71V2576/78SRAMscontainwrite,data,address
andcontrolregisters. InternallogicallowstheSRAMtogenerateaself-
timedwritebaseduponadecisionwhichcanbeleftuntiltheendofthewrite
cycle.
◆
Supports high system speed:
CommercialandIndustrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO input selects interleaved or linear burst mode
◆
Theburstmodefeatureoffersthehighestlevelofperformancetothe
◆
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V2576/78canprovidefourcyclesofdata
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O
Packaged in a JEDEC Standard 100-pin plastic thin quad operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball datawillbeavailabletotheuseronthenextthreerisingclockedges. The
forasingleaddress presentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone
cycle before it is available on the next rising clock edge. If burst mode
◆
◆
◆
◆
grid array (fBGA)
orderofthesethreeaddressesaredefinedbytheinternalburstcounter
andthe LBO inputpin.
The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray
(BGA) and 165 fine pitch ball grid array (fBGA).
PinDescriptionSummary
0
17
A -A
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
0
1
CS , CS
Chip Selects
Output Enable
OE
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
GW
BWE
(1)
1,
2,
3,
4
BW BW BW BW
CLK
ADV
ADSC
ADSP
LBO
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ZZ
Asynchronous
Synchronous
N/A
0
31
P1
P4
I/O -I/O , I/O -I/O
Data Input / Output
Core Power, I/O Power
Ground
DD DDQ
V , V
Supply
Supply
SS
V
N/A
4876 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V2578.
OCTOBER 2000
1
©2000IntegratedDeviceTechnology,Inc.
DSC-4876/07
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
0
17
A -A
ADSC
ADSP
ADV
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
1
4
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW -BW . If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BWE
1
0-7
P1
2
8-15
P2
Individual Byte
Write Enables
I
I
I
LOW
LOW
N/A
Synchronous byte write enables. BW controls I/O , I/O , BW controls I/O , I/O , etc.
1
4
BW -BW
Any active byte write causes all outputs to be disabled.
0
1
Chip Enable
Synchronous chip enable. CE is used with CS and CS to enable the IDT71V2576/78. CE
CE
also gates ADSP.
CLK
Clock
This is the clock input. All timing references for the device are made with respect to this
input.
0
0
1
CS
Chip Select 0
Chip Select 1
I
I
I
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS is used with CE and CS to enable the chip.
1
0
Synchronous active LOW chip select. CS is used with CE and CS to enable the chip.
1
CS
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
GW
0
31
I/O -I/O
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
P1
I/O -I/O
P4
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
OE
DD
V
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
I
N/A
N/A
3.3V core power supply.
DDQ
V
2.5V I/O Supply.
SS
V
N/A
Ground.
NC
ZZ
No Connect
Sleep Mode
N/A
NC pins are not electrically connected to the device.
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V2576/78 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
4876 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
CLK
2
Burst
Logic
17/18
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
CLR
ADSP
2
CLK EN
A0,A1
A2 - A17
ADDRESS
REGISTER
A0 - A16/17
GW
36/18
36/18
17/18
Byte 1
Write Register
BWE
Byte 1
Write Driver
BW1
BW2
9
9
Byte 2
Write Register
Byte 2
Write Driver
Byte 3
Write Register
Byte 3
Write Driver
BW3
BW4
9
9
Byte 4
Write Register
Byte 4
Write Driver
OUTPUT
REGISTER
CE
CS0
CS1
Q
D
Enable
DATA INPUT
REGISTER
Register
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
,
36/18
I/O0 — I/O31
I/OP1 — I/OP4
4876 drw 01
6.42
3
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Commercial &
Symbol
Rating
Industrial
Unit
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
DD
V
DDQ
V
Grade
(2)
TERM
V
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
2.5V±5%
2.5V±5%
(3,6)
(4,6)
(5,6)
TERM
V
DD
Terminal Voltage with
Respect to GND
-0.5 to V
V
V
4876 tbl 04
NOTES:
1. TA is the "instant on" case temperature
TERM
V
DD
-0.5 to V +0.5
Terminal Voltage with
Respect to GND
RecommendedDCOperating
Conditions
TERM
V
DDQ
Terminal Voltage with
Respect to GND
-0.5 to V +0.5
V
Commercial
Operating Temperature
-0 to +70
-40 to +85
-55 to +125
-55 to +125
oC
oC
oC
oC
W
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
2.375
0
Typ.
Max.
Unit
V
(7)
A
T
DD
V
3.3
3.465
2.625
0
Industrial
Operating Temperature
DDQ
V
2.5
V
SS
V
0
V
BIAS
T
Temperature
Under Bias
____
DD
V
+0.3
Input High Voltage -
Inputs
V
IH
V
1.7
STG
T
Storage
Temperature
____
____
Input High Voltage - I/O
V
IH
V
DDQ
1.7
V
+0.3(1)
T
P
Power Dissipation
DC Output Current
2.0
50
Input Low Voltage
-0.3(2)
0.7
V
IL
V
OUT
I
mA
4876 tbl 05
4876 tbl 03
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature
119BGACapacitance
(TA = +25°C, f = 1.0MHz)
100TQFPCapacitance
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
7
7
pF
CIN
5
7
pF
CI/O
pF
CI/O
pF
4876 tbl 07a
4876 tbl 07
165fBGACapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
CIN
TBD pF
C
I/O
TBD pF
4876 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.442
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
2
79
78
77
3
4
5
76
75
74
73
6
7
8
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
70
69
68
67
66
65
64
VDDQ
I/O22
I/O23
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(3)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
VDD/NC(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
63
62
61
60
59
58
57
56
55
54
53
52
51
,
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4876 drw 02
100TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pins 38 and 39 can be either NC or connected to VSS.
3. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
A10
NC
NC
2
79
78
77
3
4
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(3)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
5
76
75
74
73
6
7
8
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
70
69
68
67
66
65
64
VDDQ
I/O10
I/O11
VDD/NC(1)
VDD
NC
VSS
63
62
61
60
59
58
57
56
55
54
53
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
NC
VSS
VDDQ
NC
NC
NC
,
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4876 drw 03
100TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pins 38 and 39 can be either NC or connected to VSS.
3. Pin 64 can be left unconnected and the device will always remain in active mode.
6.462
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
3
A
9
NC
NC
CS
NC
NC
1
CS
0
7
A
2
A
DD
V
12
15
A
A
16
I/O
P3
I/O
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
CE
V
V
V
17
I/O
18
I/O
SS
SS
13
I/O
14
I/O
DDQ
V
19
I/O
12
I/O
DDQ
V
OE
20
21
11
10
I/O
I/O
I/O
I/O
G
H
J
2
3
BW
ADV
GW
BW
22
I/O
23
I/O
SS
SS
V
9
I/O
8
I/O
V
DDQ
DD
DD
V
DD
DDQ
V
V
V
NC
NC
V
24
26
SS
4
SS
6
7
I/O
I/O
I/O
V
CLK
V
I/O
K
L
(2)
25
I/O
27
I/O
4
I/O
5
I/O
1
BW
NC
BW
DDQ
28
SS
SS
SS
SS
SS
SS
3
DDQ
V
V
I/O
V
V
V
V
V
V
I/O
M
N
P
R
T
BWE
29
I/O
30
I/O
1
0
2
I/O
1
I/O
A
31
P4
I/O
0
I/O
P1
I/O
I/O
NC
NC
A
(1)
VDD / NC
NC
5
DD
V
13
A
A
LBO
(3)
10
11
(2,4)
14
A
NC
A
A
NC
DNU
ZZ
,
(4)
(4)
(4)
(4)
DDQ
V
DDQ
V
DNU
DNU
DNU
DNU
U
4876 drw 04
Top View
Pin Configuration 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
3
2
9
A
NC
NC
CS
NC
NC
NC
1
CS
0
7
A
DD
V
13
17
A
A
8
SS
SS
SS
SS
SS
SS
SS
7
I/O
I/O
NC
NC
V
V
V
NC
V
V
V
V
9
I/O
6
I/O
NC
CE
OE
DDQ
V
5
I/O
DDQ
V
NC
10
I/O
4
I/O
NC
NC
G
H
J
BW2
SS
ADV
GW
11
I/O
SS
3
I/O
NC
V
V
NC
DDQ
V
DD
DD
V
DD
DDQ
V
V
NC
NC
V
12
SS
SS
2
I/O
NC
I/O
NC
V
CLK
V
NC
K
L
(2)
13
I/O
SS
1
V
I/O
NC
NC
1
BW
NC
DDQ
V
14
I/O
SS
SS
V
DDQ
V
V
V
V
M
N
P
R
T
BWE
15
SS
SS
1
SS
0
I/O
NC
NC
A
A
V
V
I/O
NC
NC
P2
I/O
0
SS
P1
I/O
(1)
5
DD
V
12
A
NC
NC
DDQ
A
NC
VDD / NC
14
LBO
(3)
10
15
11
A
A
A
NC
A
ZZ
(4)
(4)
(2,4)
(4)
(4)
DDQ
V
4876 drw 05
DNU
DNU
DNU
DNU
DNU
V
U
,
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. L4 and U4 can be either NC or connected to VSS.
3. T7 can be left unconnected and the device will always remain in active mode.
4. DNU = Do not use; Pins U2, U3, U4, U5 and U6 are reserved for respective JTAG Pins: TMS, TDI, TDO and TRST on future revisions. Within this current
version, these pins are left unconnected.
6.42
7
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(4)
A
B
C
D
E
F
NC
NC
A
A
NC
7
8
CE
BW
BW
CS
BWE
GW
ADSC
OE
ADV
ADSP
1
3
2
1
(4)
A
6
CS
CLK
A
9
NC
0
BW
BW
4
1
I/O
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
I/O
I/O
P2
P3
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
14
17
16
15
I/O
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
19
I/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
I/O
10
11
G
H
J
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
8
23
22
DDQ
DD
SS
SS
SS
DD
DDQ
9
(1)
(2)
(3)
V
DD
NC
I/O
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
I/O
ZZ
I/O
25
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
6
24
7
K
L
M
N
P
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
4
27
26
DDQ
DD
SS
SS
SS
DD
DDQ
5
I/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
I/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
(5)
(4)
(2)
I/O
P4
NC
V
DDQ
V
SS
DNU
NC
NC
V
SS
V
DDQ
NC
I/O
P1
(4)
(5)
(5)
(4)
NC
LBO
NC
A
A
DNU
A
DNU
A
10
A
A
14
NC
5
2
1
13
(4)
(5)
(5)
R
NC
A
A
DNU
A
DNU
A
A
A
15
A
16
4
3
0
11
12
4876 tbl 17
Pin Configuration 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(4)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
NC
BW1
A
A
10
7
8
CE
BW
CS
BWE
GW
ADSC
OE
ADV
ADSP
1
2
1
(4)
A
6
CS
NC
CLK
A
9
NC
0
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
I/O
P1
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
8
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
6
9
I/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
G
H
J
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
4
11
(1)
(2)
(3)
V
NC
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZZ
DD
I/O
NC
NC
NC
NC
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
NC
NC
NC
NC
NC
12
K
L
M
N
P
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
13
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
14
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
15
(5)
(4)
(2)
I/O
V
DDQ
V
SS
DNU
NC
NC
V
SS
V
DDQ
NC
P2
(4)
(5)
(5)
(4)
NC
LBO
NC
A
5
A
2
DNU
A
1
DNU
A
11
A
14
A
15
NC
(4)
(5)
(5)
R
NC
A
4
A
3
DNU
A
0
DNU
A
12
A
13
A
16
A
17
4876 tbl 17a
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. H2 & N7 can be either NC or connected to VSS.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. DNU = Do not use; Pins P5, P7, R5, R7 and N5 are reserved for respective JTAG Pins: TDI, TDO, TMS, TCK and TRST on future revisions. Within this
current version, these pins are not connected.
6.482
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1)
___
___
___
ZZ and LBO Input Leakage Current
Output Leakage Current
Output Low Voltage
|ILZZ|
|ILO|
VOL
VOH
VDD = Max., VIN = 0V to VDD
VOUT = 0V to VDDQ, Device Deselected
IOL = +6mA, VDD = Min.
30
5
µA
µA
V
0.4
___
Output High Voltage
IOH = -6mA, VDD = Min.
2.0
V
4876 tbl 08
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(1)
150MHz
133MHz
Com'l
Symbol
Parameter
Test Conditions
Com'l
Ind
Ind
Unit
DD
Operating Power Supply
Current
Device Selected, Outputs Open, V = Max.,
DDQ
V
295
30
305
250
260
mA
DD
I
(2)
IN IH IL MAX
= Max., V > V or < V , f = f
SB1
I
DD
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, V = Max.,
35
115
35
30
35
110
35
mA
mA
(2,3)
DDQ
V
IN HD LD
= Max., V > V or < V , f = 0
SB2
DD
I
Clock Running Power
Supply Current
Device Deselected, Outputs Open, V = Max.,
105
30
100
30
(2,3)
DDQ
V
IN
HD
LD
MAX
= Max., V > V or < V , f = f
HD, DD
ZZ > V V = Max.
Full Sleep Mode Supply
Current
mA
ZZ
I
4876 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
VDDQ/2
(VDDQ = 2.5V)
50Ω
Input Pulse Levels
0 to 2.5V
2ns
I/O
Z0 = 50Ω
Input Rise/Fall Times
,
4876 drw 06
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
(VDDQ/2)
(VDDQ/2)
See Figure 1
Figure 1. AC Test Load
6
5
4
3
4876 tbl 10
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
4876 drw 07
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,3)
CE
CS
1
ADSP ADSC ADV
GW
BWE BW
x
OE
Operation
Address
CS0
CLK
I/O
(2)
Used
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
DOUT
HI-Z
DOUT
DOUT
HI-Z
DIN
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Read Cycle, Begin Burst
L
L
L
H
L
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
Read Cycle, Begin Burst
L
L
L
L
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
Write Cycle, Begin Burst
L
L
L
L
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
X
X
X
X
L
Next
L
Next
L
X
L
X
L
DIN
Next
L
H
L
DIN
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
H
L
H
L
H
L
H
X
X
X
X
X
L
X
L
DIN
H
L
DIN
X
X
DIN
4876 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.1402
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1, 2)
1
2
3
4
GW
H
H
L
BWE
H
L
BW
X
H
X
L
BW
X
H
X
L
BW
X
H
X
L
BW
X
H
X
L
Operation
Read
Read
Write all Bytes
Write all Bytes
X
L
H
H
H
H
H
(3)
Write Byte 1
L
L
H
L
H
H
L
H
H
H
L
(3)
Write Byte 2
L
H
H
H
(3)
Write Byte 3
L
H
H
(3)
Write Byte 4
L
H
4876 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V2578.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Read
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
4876 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
A0
1
First Addre ss
0
0
1
1
0
0
1
1
1
1
0
0
Se cond Addres s
Third Addre ss
1
0
1
1
0
0
1
0
0
1
Fourth Addre ss (1)
1
0
0
1
0
4876 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
1
Second Address
Third Address
1
1
0
1
1
0
0
0
1
1
0
0
0
1
Fourth Address(1)
1
0
0
0
1
1
0
4876 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
150MHz
133MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
CYC
t
Clock Cycle Time
6.7
2.6
2.6
7.5
3
ns
ns
ns
(1)
CH
Clock High Pulse Width
Clock Low Pulse Width
t
____
____
(1)
CL
3
t
Output Parameters
____
____
CD
t
Clock High to Valid Data
Clock High to Data Change
3.8
4.2
ns
ns
ns
____
____
CDC
t
1.5
0
1.5
0
____
____
(2)
Clock High to Output Active
CLZ
t
(2)
Clock High to Data High-Z
1.5
3.8
1.5
4.2
ns
ns
ns
ns
CHZ
t
____
____
OE
t
Output Enable Access Time
3.8
4.2
____
____
(2)
(2)
Output Enable Low to Output Active
Output Enable High to Output High-Z
0
0
OLZ
t
____
____
3.8
4.2
OHZ
t
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
SA
t
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
SS
t
Address Status Setup Time
Data In Setup Time
SD
t
SW
t
Write Setup Time
SAV
t
Address Advance Setup Time
Chip Enable/Select Setup Time
SC
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
HA
t
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
HS
t
Address Status Hold Time
Data In Hold Time
HD
t
HW
t
Write Hold Time
HAV
t
Address Advance Hold Time
Chip Enable/Select Hold Time
HC
t
Sleep Mode and Configuration Parameters
____
____
____
____
ZZPW
t
ZZ Pulse Width
100
100
27
100
100
30
ns
ns
(3)
ZZR
ZZ Recovery Time
Configuration Set-up Time
t
____
____
(4)
CFG
ns
t
4876 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.1422
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipeline Read Cycle(1,2)
,
6.42
13
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
,
6.1442
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 GW Controlled(1,2,3)
,
.
6.42
15
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 Byte Controlled(1,2,3)
,
6.1462
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
6.42
17
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
4876 drw 14
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Forreadcycles, ADSP andADSCfunctionidenticallyandare therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
4876 drw 15
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.1482
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.42
19
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.2402
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
21
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
IDT
XXX
S
X
XX
X
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
PF
BG
BQ
150
133
Frequency in Megahertz
,
128K x 36 Pipelined Burst Synchronous SRAM with 2.5V I/O
256K x 18 Pipelined Burst Synchronous SRAM with 2.5V I/O
71V2576
71V2578
4876 drw 13
6.2422
IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
7/23/99
9/17/99
Updatedtonewformat
Revised ISB1 and IZZ for speeds 100–200MHz
Revised tCDC at 166MHz
Pg. 8
Pg. 11
Pg. 18
Added119-LeadBGApackage diagram
Pg. 20
AddedDatasheetDocumentHistory
12/31/99
04/04/00
Pg. 1, 8, 11, 19
Removed 166, 183, and 200MHz speed grade offerings
(See IDT71V25761 and IDT71V25781)
Pg. 1, 4, 8, 11, 19
Pg. 18
Pg. 4
AddedIndustrialTemperaturerangeofferings
Added100pinTQFPPackageDiagramOutline
AddcapacitancetablefortheBGApackage;Addindustrialtemperaturetotable;Insertnoteto
AbsoluteMaxRatingandRecommendedOperatingTemperaturetables
Addnewpackageoffering13x15mm165fBGA
Correct119BGAPackageDiagramOutline
06/01/00
07/15/00
Pg. 20
Pg. 7
AddnotereferencetoBG119pinout
Pg. 8
AddDNUreference note toBQ165pinout
Pg. 20
UpdateBG119PackageDiagramOutlineDimensions
RemovePreliminarystatus
10/25/00
Pg. 8
Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
sramhelp@idt.com
800-544-7726, x4033
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
23
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