IDT71V2579YS80PFG
更新时间:2024-09-19 00:00:02
品牌:IDT
描述:Cache SRAM, 256KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V2579YS80PFG 概述
Cache SRAM, 256KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100 SRAM
IDT71V2579YS80PFG 规格参数
生命周期: | Obsolete | 零件包装代码: | QFP |
包装说明: | LQFP, | 针数: | 100 |
Reach Compliance Code: | unknown | ECCN代码: | 3A991.B.2.A |
HTS代码: | 8542.32.00.41 | 风险等级: | 5.84 |
最长访问时间: | 8 ns | 其他特性: | FLOW-THROUGH ARCHITECTURE |
JESD-30 代码: | R-PQFP-G100 | JESD-609代码: | e0 |
长度: | 20 mm | 内存密度: | 4718592 bit |
内存集成电路类型: | CACHE SRAM | 内存宽度: | 18 |
湿度敏感等级: | 4 | 功能数量: | 1 |
端子数量: | 100 | 字数: | 262144 words |
字数代码: | 256000 | 工作模式: | SYNCHRONOUS |
最高工作温度: | 70 °C | 最低工作温度: | |
组织: | 256KX18 | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | LQFP | 封装形状: | RECTANGULAR |
封装形式: | FLATPACK, LOW PROFILE | 并行/串行: | PARALLEL |
峰值回流温度(摄氏度): | 225 | 认证状态: | Not Qualified |
座面最大高度: | 1.6 mm | 最大供电电压 (Vsup): | 3.465 V |
最小供电电压 (Vsup): | 3.135 V | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | COMMERCIAL | 端子面层: | TIN LEAD |
端子形式: | GULL WING | 端子节距: | 0.65 mm |
端子位置: | QUAD | 处于峰值回流温度下的最长时间: | 30 |
宽度: | 14 mm | Base Number Matches: | 1 |
IDT71V2579YS80PFG 数据手册
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PDF下载IDT71V2577S
IDT71V2579S
IDT71V2577SA
IDT71V2579SA
128K x 36, 256K x 18
3.3V Synchronous SRAMs
2.5V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Description
Features
◆
The IDT71V2577/79 are high-speed SRAMs organized as
128Kx36/256Kx18.TheIDT71V2577/79SRAMs containwrite,data,
address andcontrolregisters.Therearenoregisters inthedataoutput
path (flow-through architecture). Internal logic allows the SRAM to
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil
128K x 36, 256K x 18 memory configurations
◆
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
CommercialandIndustrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO input selects interleaved or linear burst mode
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball
grid array (fBGA)
the endofthe write cycle.
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V2577/79canprovidefourcyclesofdata
fora single address presentedtothe SRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe
next three rising clock edges. The order of these three addresses are
definedbytheinternalburstcounterandthe LBO inputpin.
◆
◆
◆
◆
◆
◆
◆
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS
0
, CS
1
Chip Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
BWE
BW , BW
1
2
, BW
3
, BW (1)
4
CLK
Clock
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
ADV
ADSC
ADSP
LBO
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
Test Clock
Test Data Output
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
JTAG Reset (Optional)
Sleep Mode
TRST
ZZ
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
N/A
4877 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V2579.
JUNE 2003
1
©2003ntegratedDeviceTechnology,Inc.
DSC-4877/08
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinition(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of
CLK and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
ADSC
ADSP
ADV
address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the
address registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst
counter is not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW
CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs
are blocked and only GW can initiate a write cycle.
1
-BW . If BWE is LOW at the rising edge of
4
BWE
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. BW
1
controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active
BW
1
-BW
4
byte write causes all outputs to be disabled.
Chip Enable
Synchronous chip enable. CE is used with CS
ADSP.
0
and CS to enable the IDT71V2577/79. CE also gates
1
CE
CLK
Clock
I
I
I
I
N/A
This is the clock input. All timing references for the device are made with respect to this input.
CS
CS
GW
0
Chip Select 0
Chip Select 1
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
0
is used with CE and CS
1
to enable the chip.
1
is used with CE and CS0 to enable the chip.
1
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising
edge of CLK. GW supersedes individual byte write enables.
I/O
I/OP1-I/OP4
0
-I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge
of CLK. The data output path is flow-through (no output register).
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is
selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not
change state while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the
chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
OE
TMS
TDI
Test ModeSelect
Test Data Input
I
I
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Test DataOutput
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST
can be left floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
LOW
HIGH
TRST
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V2577/79
to its lowest power consumption level. Data retention is guaranteed in Sleep Mod e.This pin has an internal
pull down.
ZZ
Sleep Mode
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
2.5V I/O Supply.
Ground.
V
V
NC
No Connect
NC pins are not electrically connected to the device.
4877 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
CLK
2
Burst
Logic
17/18
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
CLR
ADSP
2
CLK EN
A0,A1
A2 - A17
ADDRESS
REGISTER
A0 -
A
16/17
36/18
36/18
17/18
GW
BWE
Byte 1
Write Register
Byte 1
Write Driver
BW
1
9
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
Byte 3
Write Register
Byte 3
Write Driver
BW
3
9
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
CE
CS
CS
Q
D
0
Enable
DATA INPUT
REGISTER
1
Register
CLK EN
ZZ
Powerdown
OE
OUTPUT
BUFFER
OE
,
36/18
I/O
0
- I/O31
I/OP1 - I/OP4
4877 drw 01
TMS
TDI
TCK
TRST
JTAG
(SA Version)
TDO
(Optional)
6.42
3
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Commerical &
Symbol
Rating
Unit
Industrial Values
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
VDD
VDDQ
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
2.5V±5%
2.5V±5%
(3,6)
(4,6)
(5,6)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
4877 tbl 04
NOTES:
1. TA is the “instant on” case temperature.
VTERM
Terminal Voltage with
Respect to GND
VTERM
Terminal Voltage with
Respect to GND
V
RecommendedDCOperating
Conditions
Commercial
oC
oC
oC
oC
W
Operating Temperature
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
2.375
0
Typ.
3.3
Max.
Unit
V
T (7)
A
V
DD
DDQ
SS
IH
IH
IL
3.465
2.625
0
Industrial
-40 to +85
Operating Temperature
V
2.5
V
Temperature
Under Bias
-55 to +125
TBIAS
V
0
V
____
V
Input High Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
1.7
VDD + 0.3
V
Storage
-55 to +125
TSTG
(1)
____
____
V
1.7
V
DDQ + 0.3
V
Temperature
(2)
V
-0.3
0.7
V
P
T
Power Dissipation
DC Output Current
2.0
50
4877 tbl 05
NOTES:
IOUT
mA
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
4877 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the “instant on” case temperature.
100PinTQFPCapacitance
119BGACapacitance
(TA = +25°C, f = 1.0MHz)
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CIN
V
5
7
pF
CI/O
V
pF
CI/O
V
pF
4877 tbl 07a
4877 tbl 07
165fBGACapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
V
pF
4877 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.442
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP2
I/O15
I/O14
I/OP3
I/O16
I/O17
2
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
69
68
67
66
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
VDDQ
VDDQ
I/O22
I/O9
I/O8
VSS
NC
I/O23
(1)
VSS
VDD
65
64
NC
V
DD
ZZ(2)
VSS
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O24
I/O25
I/O7
I/O6
VDDQ
VDDQ
VSS
VSS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
,
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O1
I/O0
I/OP1
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
4877 drw 02a
100TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
A
NC
NC
10
NC
NC
NC
2
3
4
V
DDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
NC
NC
NC
I/OP1
I/O
I/O
7
8
I/O8
7
9
72
71
70
I/O9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
V
DDQ
VDDQ
69
68
67
66
65
64
I/O10
I/O
I/O
VSS
NC
5
4
I/O11
(1)
V
SS
VDD
NC
V
DD
ZZ(2)
VSS
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O12
I/O13
I/O
I/O
3
2
V
DDQ
V
V
DDQ
SS
VSS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
0
VSS
VSS
,
V
DDQ
NC
NC
NC
VDDQ
NC
NC
NC
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
4877 drw 02b
100TQFP
TopView
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.462
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
3
2
9
1
CS
NC
NC
NC
NC
CS
0
7
A
DD
V
12
15
A
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
CE
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
DDQ
19
I/O
12
I/O
DDQ
V
V
V
V
V
V
OE
20
I/O
21
I/O
3
2
BW
11
I/O
10
I/O
G
H
J
BW
ADV
GW
22
I/O
23
I/O
SS
SS
9
I/O
8
I/O
V
V
DDQ
24
DD
DD
V
DD
V
DDQ
V
NC
NC
26
I/O
SS
SS
6
I/O
7
I/O
K
L
I/O
V
CLK
NC
V
25
I/O
27
I/O
4
1
BW
4
I/O
5
I/O
BW
DDQ
28
I/O
SS
SS
SS
SS
SS
SS
SS
3
I/O
DDQ
V
V
V
V
V
V
V
M
N
P
R
T
BWE
29
I/O
30
1
0
2
I/O
1
I/O
I/O
A
I/O
I/O
0
I/O
31
I/O
P4
P1
A
5
DD
V
13
A
NC
NC
A
NC
NC
LBO
(3)
,
10
11
(2)
14
A
A
A
NC
ZZ
(2)
(2)
(2)
(2,4)
V
NC/TRST
DDQ
V
DDQ
U
NC/TDO
NC/TMS
NC/TDI
NC/TCK
4877 drw 02c
Top View
Pin Configuration – 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
A
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
ADSP
ADSC
3
2
9
1
CS
NC
NC
CS
NC
NC
NC
0
7
A
DD
V
13
17
A
A
8
I/O
SS
SS
SS
2
SS
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
CE
V
V
V
V
V
9
6
I/O
NC
I/O
NC
NC
DDQ
V
5
I/O
DDQ
V
OE
10
I/O
4
G
H
J
NC
NC
I/O
NC
BW
ADV
GW
11
I/O
SS
3
I/O
NC
V
DDQ
V
DD
DD
V
DD
V
DDQ
V
V
NC
NC
12
SS
SS
2
NC
I/O
V
V
CLK
NC
V
NC
I/O
K
L
SS
13
I/O
1
BW
1
I/O
NC
NC
DDQ
14
SS
SS
SS
SS
SS
SS
DDQ
V
V
I/O
V
V
V
V
V
V
V
A
NC
M
N
P
R
T
BWE
15
I/O
1
A
0
A
0
I/O
NC
NC
P2
I/O
P1
NC
NC
NC
NC
I/O
NC
5
DD
V
SS
14
12
11
A
A
A
LBO
(3)
10
15
A
ZZ
A
NC
,
(2)
(2)
(2)
(2)
(2,4)
V
DDQ
V
DDQ
U
NC/TDO
NC/TMS
NC/TDI
NC/TCK
NC/TRST
4877 drw 02d
NOTES:
Top View
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
7
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(4)
A
B
C
D
E
F
NC
A
7
A
8
NC
CE
1
BW
3
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
(4)
NC
A6
CS
0
CLK
A9
NC
BW4
BW1
I/OP3
I/O17
I/O19
I/O21
I/O23
NC
V
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
10
11
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/OP2
I/O14
I/O12
I/O10
I/O16
I/O18
I/O20
I/O22
NC
V
V
V
V
V
V
V
I/O15
I/O13
I/O11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
G
H
J
VDDQ
V
V
V
V
V
V
I/O
NC
I/O
I/O
I/O
I/O
NC
9
I/O8
(3)
V
SS(1)
NC
V
V
V
V
V
NC
ZZ
I/O
I/O
I/O
I/O
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
13
7
6
K
L
M
N
P
V
V
V
V
V
V
V
5
4
V
V
V
V
V
V
V
3
2
V
V
V
V
V
V
V
1
0
(4)
NC/TRST(2, 5)
V
V
NC
NC
V
V
I/OP1
(4)
(2)
(2)
(4)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A14
NC
(4)
(2)
R
NC
A4
A3
NC/TMS(2)
A0
NC/TCK
A
A12
A15
A16
LBO
4877 tbl 17
Pin Configuration – 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(4)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
7
NC
A
8
A10
CE
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
(4)
A6
CS
0
NC
CLK
A9
NC
BW1
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
11
12
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
I/OP1
I/O
8
V
V
V
V
V
V
V
I/O7
I/O
9
V
V
V
V
V
V
V
I/O
I/O
I/O
6
I/O10
I/O11
NC
V
V
V
V
V
V
V
5
G
H
J
V
V
V
V
V
V
V
4
(3)
V
SS(1)
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
NC
V
V
V
V
V
NC
ZZ
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
14
13
I/O
I/O
I/O
I/O
NC
3
NC
NC
NC
NC
NC
K
L
M
N
P
NC
V
V
V
V
V
V
V
2
NC
V
V
V
V
V
V
V
1
NC
V
V
V
V
V
V
V
0
(4)
NC
V
V
NC/TRST(2, 5)
NC
NC
V
V
(4)
(2)
(2)
(4)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A15
NC
(4)
(2)
R
NC
A4
A3
NC/TMS(2)
A0
NC/TCK
A
A
A16
A17
LBO
4877 tbl 17a
NOTES:
1. H1 does not have to be directly VSS as long as input voltage is < VIL.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.482
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI
|ILI
|ILO
|
Input Leakage Current
V
DD = Max., VIN = 0V to VDD
5
µA
(1)
___
___
___
ZZ, LBO and JTAG Input Leakage Current
Output Leakage Current
|
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VDDQ, Device Deselected
OL = +6mA, VDD = Min.
OH = -6mA, VDD = Min.
30
5
µA
µA
V
|
V
VOL
Output Low Voltage
I
0.4
___
VOH
Output High Voltage
I
2.0
V
4877 tbl 08
NOTE:
1. The LBO, TMS, TDI, TCK, and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
7.5ns
8ns
8.5ns
Com'l
Symbol
Parameter
Test Conditions
Com'l Only Com'l
Ind
Ind
Unit
Operating Power Supply Current
Device Selected, Outputs Open, VDD = Max.,
255
30
200
30
210
180
190
mA
I
DD
(2)
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
ISB1
CMOS Standby Power Supply
Current
Device Deselected, Outputs Open, VDD = Max.,
DDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
35
95
35
30
35
90
35
mA
mA
V
ISB2
Clock Running Power Supply
Current
Device Deselected, Outputs Open, VDD = Max.,
90
85
80
(2,3)
V
DDQ = Max., VIN > VHD or < VLD, f = fMAX
IZZ
Full Sleep Mode Supply Current
ZZ > VHD, DD = Max.
V
30
30
30
mA
4877 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
V
DDQ/2
(VDDQ = 2.5V)
50Ω
Input Pulse Levels
0 to 2.5V
2ns
I/O
Z0 = 50Ω
Input Rise/Fall Times
,
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
(VDDQ/2)
(VDDQ/2)
See Figure 1
4877d03
Figure 1. AC Test Load
6
5
4
4877 tbl 10
3
∆tCD
(Typical, ns)
2
1
,
20 30 50
80 100
Capacitance (pF)
200
4877d05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,3)
CE
CS1
ADSP ADSC ADV
GW
BWE BWx OE(2)
Operation
Address
Used
CS
0
CLK
I/O
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cycle, Begin Burst
L
L
L
H
L
HI-Z
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cycle, Begin Burst
L
L
L
L
DOUT
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
HI-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
OUT
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
HI-Z
Next
L
D
IN
IN
IN
IN
OUT
Next
L
X
L
X
L
D
Next
L
H
L
D
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
X
X
X
X
HI-Z
D
IN
IN
IN
IN
4877 tbl 11
X
L
X
L
D
H
L
D
X
X
D
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.1402
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousWrite Function Truth Table(1, 2)
GW
H
H
L
BWE
H
L
BW
X
H
X
L
1
BW
X
H
X
L
2
BW
X
H
X
L
3
BW4
Operation
Read
X
H
X
L
Read
Write all Bytes
Write all Bytes
X
L
H
H
H
H
H
(3)
Write Byte 1
L
L
H
L
H
H
L
H
H
H
L
(3)
Write Byte 2
L
H
H
H
(3)
Write Byte 3
L
H
H
(3)
Write Byte 4
L
H
4877 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V2579.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
Read
OE
ZZ
I/O Status
Power
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Read
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
4877 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
4877 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
4877 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
7.5ns(5)
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
Clock Parameter
____
____
____
____
____
____
t
CY C
Clock Cycle Time
8.5
3
10
4
11.5
4.5
ns
ns
ns
(1)
CH
Clock High Pulse Width
Clock Low Pulse Width
t
____
____
____
(1)
CL
3
4
4.5
t
Output Parameters
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
7.5
8
8.5
ns
ns
ns
____
____
____
tCDC
2
0
2
0
2
0
____
____
____
(2)
CLZ
t
(2)
Clock High to Data High-Z
2
3.5
2
3.5
2
3.5
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Output Active
3.5
3.5
3.5
____
____
____
(2)
(2)
0
0
0
t
OLZ
____
____
____
Output Enable High to Output High-Z
3.5
3.5
3.5
t
OHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SA
SS
SD
SW
SAV
SC
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
2
2
2
2
2
2
2
2
2
2
2
2
ns
ns
ns
ns
ns
ns
t
Address Status Setup Time
Data In Setup Time
t
t
Write Setup Time
t
Address Advance Setup Time
Chip Enable/Select Setup Time
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HA
HS
HD
HW
HAV
HC
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Status Hold Time
Data In Hold Time
t
t
Write Hold Time
t
Address Advance Hold Time
Chip Enable/Select Hold Time
t
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
____
____
____
t
ZZPW
ZZR(3)
CFG (4)
ZZ Pulse Width
100
100
34
100
100
40
100
100
50
ns
ns
t
ZZ Recovery Time
Configuration Set-up Time
t
ns
4877 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
6.1422
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Flow-Through Read Cycle(1,2)
,
6.42
13
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Flow-Through Read and Write Cycles(1,2,3)
,
6.1442
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3)
,
6.42
15
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled(1,2,3)
,
6.1462
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
6.42
17
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS
1
0
CS
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
4877 drw 10
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS
1
0
CS
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
4877 drw 11
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.1482
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
t
JCYC
t
JR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
3)
(
x
TRST
M4877 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
Register Name
Bit Size
____
____
t
ns
Instruction (IR)
4
1
t
40
ns
Bypass (BYR)
t
5(1)
ns
____
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
t
5(1)
ns
____
Note (1)
____
t
50
ns
I4877 tbl 03
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
t
20
ns
____
t
0
ns
____
____
t
25
25
ns
t
JTAG Hold
ns
I4877 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
19
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Value
Description
Revision Number (31:28)
0x2
0x22D, 0x22F
0x33
Reserved for version number.
IDT Device ID (27:12)
Defines IDT part number 71V2577SA and 71V2579SA, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
ID Register Indicator Bit (Bit 0)
1
I4877 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I4877 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.2402
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
IDT XXX
X
S
XX
X
X
Power Speed
Package
Process/
Temperature
Range
Device
Type
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF**
BG
BQ
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
75*
80
85
Access Time in Tenths of Nanoseconds
Standard Power
Standard Power with JTAG Interface
S
SA
First Generation or current stepping
Second Generation die step
Blank
Y
,
71V2577
71V2579
128K x 36 Flow-Through Burst Synchronous SRAM with 2.5V I/O
256K x 18 Flow-Through Burst Synchronous SRAM with 2.5V I/O
4877 drw 12
*Commercial temperature range only.
** JTAG (SA version) is not available with 100 pin TQFP package
PackageInformation
100-Pin Thin Quad Plastic Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Information available on the IDT website
6.42
21
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
7/23/99
9/17/99
Updatedtonewformat
RevisedI/Opindescription
Revisedblockdiagramforflow-throughfunctionality
Revised ISB1 and IZZ for speeds 7.5 to 8.5ns
Added119-leadBGApackagediagram
Pg. 2
Pg. 3
Pg. 8
Pg. 18
Pg. 20
AddedDatasheetDocumentHistory
12/31/99 Pg. 1, 4, 8, 11, 19
04/04/00 Pg. 18
Pg. 4
AddedIndustrialTemperaturerangeofferings
Add100pinTQFPPackageDiagramOutline
AddcapacitancetableforBGApackage;AddIndustrialtemperaturetotable;insertnoteto
AbsoluteMaxRatingtableandRecommendedOperatingTemperaturetables.
Addnewpackage offering, 13x15mm165fBGA
Correct119BGAPackageDiagramOutline
06/01/00
Pg. 20
07/15/00 Pg. 7
Pg. 8
AddnotereferencetoBG119pinout
AddDNUreference note toBQ165pinout
Pg. 20
UpdateBG119PackageDiagramOutlineDimensions
RemovePreliminarystatus
10/25/00
Pg. 8
Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
Updated165BGAtableinformationfromTBDto7
UpdateddatasheetwithJTAGinformation
Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))
requiringNCorconnectiontoVss.
04/22/03 Pg.4
06/30/03 Pg. 1,2,3,5-9
Pg. 5-8
Pg. 19,20
Pg. 21-23
Pg. 24
AddedtwopagesofJTAGSpecification,ACElectrical,DefinitionsandInstructions
Removedoldpackageinformationfromthedatasheet
UpdatedorderinginformationwithJTAGandYsteppinginformation. Addedinformation
regardingpackages availableIDTwebsite.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.2422
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