IDT71V321L35TF8 [IDT]
Dual-Port SRAM, 2KX8, 35ns, CMOS, PQFP64, STQFP-64;
| 型号： | IDT71V321L35TF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 2KX8, 35ns, CMOS, PQFP64, STQFP-64 静态存储器 |
| 文件： | 总15页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V321S/L
IDT71V421S/L
HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
Features
◆
◆
On-chip port arbitration logic (IDT71V321 only)
High-speed access
◆
◆
◆
◆
◆
BUSY output flag on IDT71V321; BUSY input on IDT71V421
Fully asynchronous operation from either port
Battery backup operation—2V data retention (L only)
TTL-compatible, single 3.3V power supply
Available in 52-pin PLCC, 64-pin TQFP and STQFP
packages
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
– Commercial: 25/35/55ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT71V321/IDT71V421S
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71V321/V421L
— Active: 325mW (typ.)
— Standby: 1mW (typ.)
◆
◆
◆
◆
Two INT flags for port-to-port communications
MASTER IDT71V321 easily expands data bus width to 16-
◆
or-more-bits using SLAVE IDT71V421
FunctionalBlockDiagram
OE
R
R
OE
L
CE
R/W
CEL
R
R/W
L
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
(1,2)
BUSYR
BUSY
L
A
10L
A
A
10R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
11
11
ARBITRATION
and
INTERRUPT
LOGIC
CE
OE
R/W
L
CE
OE
R/W
R
R
L
R
L
(2)
(2)
L
INTR
INT
3026 drw 01
NOTES:
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.
2. BUSY and INT are totem-pole outputs.
AUGUST 2006
1
DSC-3026/10
©2006IntegratedDeviceTechnology,Inc.
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Static RAMs with internal interrupt logic for interprocessor communica-
tions. The IDT71V321 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system ap-
plications results in full speed, error-free operation without the need for
additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (L)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71V321/IDT71V421 devices are packaged in a 52-pin
PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP
(super thin quad flatpack).
PinConfigurations(1,2,3)
INDEX
7 6 5 4 3 2
52 51 50 49 48 47
46
OE
R
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L
A
8
9
1
0R
A
A
A
A
A
A
A
A
A
A
A
45
44
43
42
41
40
39
38
37
36
35
34
1R
A
10
11
12
13
14
15
16
17
18
2R
3R
4R
5R
6R
7R
8R
9R
A
A
IDT71V321/421J
J52-1(4)
A
A
52-Pin PLCC
Top View(5)
A
A
I/O
I/O
I/O
I/O
NC
19
20
7R
I/O
21 22 23 24 25 26 27 28 29 30 31 32 33
,
3026 drw 02
INDEX
OER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OEL
A0L
48
47
46
0R
A
1R
A
A1L
A2L
A3L
A4L
A5L
2R
A
45
44
43
42
41
40
39
38
37
36
35
34
33
3R
A
4R
A
IDT71V321/421PF or TF
PP64-1(4)
&
5R
A
6R
A
A
6L
PN64-1(4)
N/C
N/C
A7L
7R
A
64-Pin STQFP
64-Pin TQFP
Top View(5)
8R
A
A
A
8L
9L
9R
A
N/C
N/C
N/C
I/O0L
NOTES:
7R
I/O
1L
I/O
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
I/O6R
2L
I/O
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3026 drw 03
2
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
RecommendedOperating
TemperatureandSupplyVoltage(1,2)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
Commercial
0OC to +70OC
0V
0V
3.3V
3.3V
+
+
0.3V
Industrial
-40OC to +85OC
0.3V
Operating
Temperature
TA
0 to +70
°C
oC
3026 tbl 02
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Temperature
Under Bias
-55 to +125
TBIAS
T
STG
Storage
-65 to +150
50
oC
Temperature
DC Output
Current
mA
IOUT
RecommendedDCOperating
Conditions
3026 tbl 01
NOTES:
Symbol
Parameter
Min.
Typ.
Max.
3.6
0
Unit
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
VCC
Supply Voltage
3.0
3.3
GND Ground
0
0
V
V
IH
Input High Voltage
Input Low Voltage
2.0
V
CC+0.3(2)
V
____
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
-0.3(1)
0.8
V
____
VIL
3026 tbl 03
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + 0.3V.
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
9
pF
COUT
V
10
pF
3026 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
71V321S
71V421S
71V321L
71V421L
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
(1)
___
___
Input Leakage Current
|ILI|
V
CC = 3.6V,
10
5
µA
V
IN = 0V to VCC
___
___
|ILO
|
Output Leakage Current
CE = VIH, VOUT = 0V to VCC
CC = 3.6V
10
5
µA
V
V
___
___
VOL
Output Low Voltage
Output High Voltage
IOL = 4mA
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
3026 tbl 05
NOTE:
1. At VCC < 2.0V input leakages are undefined.
3
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2) (VCC = 3.3V ± 0.3V)
71V321X25
71V421X25
Com'l
71V321X35
71V321X55
71V421X55
Com'l Only
71V421X35
Com'l Only
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.
Max.
Typ.
55
Max.
125
Typ.
55
Max. Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
55
55
130
100
115
85
mA
mA
mA
CE = VIL, Outputs Disabled
SEM = VIH
55
95
55
(3)
f = fMAX
IND
S
L
55
55
150
130
___
___
___
___
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
15
15
35
20
15
15
35
20
15
15
35
20
CE
R
= CE
L
= VIH
= VIH
SEM
R
= SEM
L
(3)
f = fMAX
S
L
15
15
50
35
___
___
___
___
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
25
25
75
55
25
25
70
50
25
25
60
40
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
S
L
25
25
95
75
SEMR
= SEML = VIH
___
___
___
___
I
SB3
Full Standby Current
(Both Ports - All
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VCC - 0.2V
L
and
COM'L
IND
S
L
1.0
0.2
5
3
1.0
0.2
5
3
1.0
0.2
5
3
mA
mA
R
CMOS Level Inputs)
V
V
S
L
1.0
0.2
10
6
___
___
___
___
R
L
ISB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
COM'L
IND
S
L
25
25
70
55
25
25
65
50
25
25
55
40
CE < 0.2V and
CE"BA" > VCC - 0.2V
(5)
SEM
R
= SEML > VCC - 0.2V
S
L
25
25
85
70
V
IN > VCC - 0.2V or VIN < 0.2V
___
___
___
___
Active Port Outputs Disabled
(3)
f = fMAX
3026 tbl 06
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.).
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC and using "AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
Data Retention Characteristics(L Version Only)
(1)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
___
V
DR
VCC for Data Retention
2.0
0
___
I
CCDR
Data Retention Current
µA
V
CC = 2V, CE > VCC - 0.2V
COM'L.
IND.
100
1500
(3)
CDR
___
t
Chip Deselect to Data
Retention Time
VIN > VCC - 0.2V or VIN < 0.2V
100
4000
µA
V
___
___
0
(3)
(2)
___
___
t
R
Operation Recovery Time
t
RC
V
3026 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
4
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Data Retention Waveform
Input Pulse Levels
GND to 3.0V
5ns
DATA RETENTION MODE
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
CC
V
DR
V
≥
2.0V
3.0V
3.0V
1.5V
CDR
R
t
t
Figures 1 and 2
DR
V
CE
3026 tbl 08
IH
V
IH
V
,
3026 drw 04
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
BUSY
435Ω
435Ω
INT
30pF
5pF
3026 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
AC Electrical Characteristics Over the
OperatingTemperatureSupplyVoltageRange(2)
71V321X25
71V421X25
Com'l
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
25
35
55
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
Chip Enable Access Time
25
25
35
35
55
55
____
____
____
____
____
____
t
t
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
12
20
25
____
____
____
t
3
3
3
____
____
____
t
0
0
0
Output High-Z Time(1,2)
12
15
30
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
0
____
____
____
____
____
____
t
50
50
50
ns
3026 tbl 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
5
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
t
RC
ADDRESS
tAA
tOH
t
OH
PREVIOUS DATA VALID
DATA VALID
DATAOUT
BUSYOUT
3026 drw 06
(2,3)
t
BDD
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
t
ACE
CE
OE
(4)
(2)
tHZ
tAOE
(2)
(1)
tHZ
tLZ
VALID DATA
DATAOUT
(1)
(4)
tLZ
t
PD
t
PU
ICC
CURRENT
50%
50%
ISS
3026 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
71V321X25
71V421X25
Com'l
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time(5)
25
20
20
0
35
30
30
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
20
0
30
0
40
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
t
12
20
20
____
____
____
t
12
15
30
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2)
15
15
30
____
____
____
t
0
0
0
ns
3026 tbl 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4. 'X' in part numbers indicates power rating (S or L).
5. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
7
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
OE
(7)
HZ
t
tAW
CE
(7)
(6)
AS
tHZ
(2)
WP
t
t
(3)
t
WR
R/W
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
t
DH
3026 drw 08
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
CE
t
AW
(6)
(2)
(3)
t
AS
tEW
tWR
R/W
t
DW
tDH
IN
DATA
3026 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
8
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
71V321X25
71V421X25
Com'l
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY Timing (For Master IDT71V321 Only)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WH
WDD
DDD
APS
BDD
20
20
20
20
20
20
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
t
t
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY(5)
t
20
20
30
____
____
____
t
12
15
20
(1)
____
____
____
t
Write Pulse to Data Delay
50
60
80
t
Write Data Valid to Read Data Delay(1)
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
35
45
65
____
____
____
____
____
____
t
5
5
5
____
____
____
t
30
30
45
BUSY Timing (For Slave IDT71V421 Only)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
WH
WDD
DDD
0
0
0
ns
ns
ns
t
Write Hold After BUSY(5)
12
15
20
(1)
____
____
____
t
Write Pulse to Data Delay
50
35
60
45
80
65
Write Data Valid to Read Data Delay(1)
ns
____
____
____
t
3026 tbl 11
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
t
WP
R/W"A"
t
DW
tDH
DATAIN "A"
VALID
(1)
tAPS
ADDR"B"
BUSY"B"
MATCH
tBDD
t
BDA
tBAA
tWDD
DATAOUT"B"
VALID
tDDD
NOTES:
3026 drw 10
1. To ensure that the earlier of the two ports wins. tAPS is ignored for SLAVE (71V421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
9
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(4)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
,
R/W"B"
(2)
3026 drw 11
NOTES:
1. tWH must be met for both BUSY input (71V421, slave) or output (71V321, master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. tWB is for the slave version (71V421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
ADDRESSES MATCH
"A" AND "B"
CE"B"
(2)
tAPS
CE"A"
tBAC
t
BDC
BUSY"A"
3026 drw 12
Timing Waveform of BUSY Arbritration Controlled
by Address Match Timing(1)
t
RC OR tWC
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
t
APS
t
BAA
tBDA
3026 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).
10
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
71V321X25
71V421X25
Com'l
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
25
25
25
25
45
45
____
____
____
t
Interrupt Reset Time
ns
3026 tbl 12
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
TimingWaveformof InterruptMode(1)
SET INT
tWC
INTERRUPT ADDRESS(2)
ADDR"A"
(4)
(3)
tAS
tWR
R/W"A"
INT"B"
(3)
tINS
3026 drw 14
CLEAR INT
t
RC
(2)
ADDR"B"
INTERRUPT CLEAR ADDRESS
(3)
AS
t
OE"B"
INT"B"
(3)
t
INR
,
3026 drw 15
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
11
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
TruthTables
Table I. Non-Contention
Read/WriteControl(4)
Left or Right Port(1)
R/W
D0-7
Function
CE
OE
Port Deselected and in Power-
Down Mode. ISB2 or ISB4
X
H
X
Z
CE
R = CEL = VIH, Power-Down Mode ISB1
X
H
X
Z
or ISB3
L
H
H
L
L
L
X
L
DATAIN
Data on Port Written Into Memory(2)
(3)
DATAOUT Data in Memory Output on Port
H
Z
High-impedance Outputs
3026 tbl 13
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
Table II. Interrupt Flag(1,4)
Left Port
Right Port
OE
R/WL
A10L-A0L
R/WR
A
10R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INT
L
CER
R
INTR
(2)
L
L
X
X
L
X
X
X
L
7FF
X
X
X
X
L
X
L
L
X
X
L
X
7FF
7FE
X
L
R
(3)
X
X
H
R
(3)
X
X
L
X
X
X
L
(2)
X
7FE
H
X
X
L
3026 tbl 14
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
TableIII—AddressBUSY Arbitration
Inputs
Outputs
A
OL-A10L
(1)
(1)
A
OR-A10R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
(3)
MATCH
(2)
(2)
Write Inhibit
3026 tbl 15
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71V321 (master). Both are inputs
for IDT71V421 (slave). BUSYX outputs on the IDT71V321 are totem-pole. On
slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. 'H' if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR
= LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level
on the pin.
12
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
beingexpandedindepth,thentheBUSYindicationfortheresultingarray
FunctionalDescription
requires the use of an external AND gate.
TheIDT7V1321/IDT71V421providestwoportswithseparatecontrol,
addressandI/Opinsthatpermitindependentaccessforreadsorwrites
toanylocationinmemory.TheIDT71V321/IDT71V421hasanautomatic
power down feature controlled by CE. The CE controls on-chip power
downcircuitrythatpermitstherespectiveporttogointoastandbymode
whennotselected(CE=VIH).Whenaportisenabled,accesstotheentire
memoryarrayispermitted.
Width Expansion with Busy Logic
Master/SlaveArrays
WhenexpandinganSRAMarrayinwidthwhileusingBUSYlogic,one
masterpartis usedtodecidewhichsideoftheSRAMarraywillreceive
a BUSY indication. Any number of slaves to be addressed in the same
addressrangeasthemaster,usetheBUSYsignalasawriteinhibitsignal.
ThusontheIDT71V321/IDT71V421SRAMstheBUSYpinisanoutput
ifthepartisMaster(IDT71V321),andtheBUSYpinisaninputifthepart
is a Slave (IDT71V421) as shown in Figure 3.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessage center)is assignedtoeachport. The leftportinterruptflag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), whereawriteisdefinedastheCER =R/WR=VILperTruthTable
II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag(INTR)isassertedwhentheleftportwritestomemorylocation7FF
(HEX)andtocleartheinterruptflag(INTR),therightportmustaccessthe
memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,
sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,
address locations 7FEand7FFare notusedas mailboxes, butas part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
SLAVE
Dual Port
RAM
MASTER
Dual Port
RAM
CE
CE
BUSY
R
BUSY
R
BUSY
L
BUSY
L
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY
L
BUSY
R
BUSY
L
BUSY
R
BUSY
R
BUSY
L
3026 drw 16
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71V321 (Master) and (Slave) IDT71V421 RAMs.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesabusyindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onaMaster,is basedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
TheuseofBUSYLogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.
TheBUSYoutputsontheIDT71V321RAMmasteraretotem-poletype
outputsanddonotrequirepull-upresistorstooperate.IftheseRAMsare
13
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT
XXXX
A
999
A
A
A
Device Type Power Speed Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
(1)
I
(2)
G
Green
J
PF
TF
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
,
64-pin STQFP (PP64-1)
25
35
55
Commercial & Industrial
Commercial Only
Commercial Only
Speed in nanoseconds
L
S
Low Power
Standard Power
71V321 16K (2K x 8-Bit) MASTER 3.3V
Dual-Port RAM w/ Interrupt
16K (2K x 8-Bit) SLAVE 3.3V
Dual-Port RAM w/ Interrupt
71V421
3026 drw 17
NOTES:
1. Contact your sales office Industrial temperature range is available for selected speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
03/24/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
Changed open drain to totem-pole in Table III, note 1
Deleted'does not'incopyfromBusyLogic
Replaced IDT logo
Movedfull"Description"topage 2andadjustedpage layouts
Increasedstoragetemperatureparameters
ClarifiedTAparameter
Page 2
06/15/99:
10/15/99:
10/21/99:
11/12/99:
01/12/01:
Page 12
Page 13
Pages 1 & 2
Page 3
Page 4
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
08/22/01:
01/17/06:
Pages 4, 5, 7,
9 & 11
Page 1
IndustrialtemprangeofferingremovedfromDC&ACElectricalCharacteristicsfor35and55ns
Addedgreenavailabilitytofeatures
Page 14
Page 1 & 14
Addedgreenindicatortoorderinginformation
Replaced old IDTTM with new IDTTM logo
Datasheet document history continued on page 15
14
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Datasheet Document History (con't)
08/25/06:
Page 11 Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode
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15
6.42
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