IDT71V3548S133PFI [IDT]
256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs; 256K ×18的3.3V同步ZBT SRAM 3.3VI / O ，突发计数器输出流水线
| 型号： | IDT71V3548S133PFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs |
| 文件： | 总26页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K x 18
IDT71V3548S
IDT71V3548SA
3.3V Synchronous ZBT SRAM
3.3V I/O, Burst Counter
Pipelined Outputs
Address and control signals are applied to the SRAM during one
clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit
read or write.
The IDT71V3548 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V3548
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, anypendingdata transfers (reads orwrites)willbe
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected
orawriteisinitiated.
The IDT71V3548 has an on-chip burst counter. In the burst
mode,theIDT71V3548canprovidefourcyclesofdataforasingleaddress
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
TheIDT71V3548SRAMsutilizeIDT's latesthigh-performanceCMOS
processandarepackagedinaJEDECstandard14mmx20mm100-pin
plasticthinquadflatpack(TQFP)as wellas a 119ballgridarray(BGA)
and 165 fine pitch ball grid array (fBGA).
Features
◆
256K x 18 memory configurations
◆
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
◆
◆
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
◆
◆
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
Optional Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
PinDescriptionSummary
0
17
A -A
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
1
2
2
CE , CE , CE
Output Enable
OE
R/W
CEN
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
1
2
3
4
BW , BW , BW , BW
CLK
ADV/LD
LBO
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Te st Data Inp ut
Synchronous
Static
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
TRST
ZZ
Te st Clo c k
Test Data Output
Synchronous
Asynchronous
Synchronous
Synchronous
Static
JTAG Reset (Optional)
Sleep Mode
0
15
P1
P2
I/O -I/O , I/O -I/O
Data Input / Output
Core Power, I/O Power
Ground
DD DDQ
V
, V
Supply
Supply
SS
V
Static
5296 tbl 01
MAY 2002
1
©2002IntegratedDeviceTechnology,Inc.
DSC-5296/03
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definition(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising
edge of CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address and
control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is
sampled high then the internal burst counter is advanced for any burst that was in progress.
The external addresses are ignored when ADV/LD is sampled high.
R/W
Read / Write
Clock Enable
I
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs,
including clock are ignored and outputs remain unchanged. The effect of CEN sampled high
on the device outputs is as if the low to high clock transition did not occur. For normal
operation, CEN must be sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On
load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal
(BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst
write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of
data are written into the device two cycles later. BW1-BW4 can all be tied low if always doing
write to the entire 36-bit word.
BW1-BW4
CE1, CE2
Chip Enables
Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the
IDT71V3548. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising
edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e., the data
bus will tri-state two clock cycles after deselect is initiated.
CE2
Chip Enable
Clock
I
I
HIGH
N/A
Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2
has inverted polarity but otherwise identical to CE1 and CE2.
CLK
This is the clock input to the IDT71V3548. Except for OE, all timing references for the device
are made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
Linear Burst Order
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Linear burst sequence is selected. LBO is a static input and it must not
change during device operation.
LBO
OE
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V3548. When OE is
high the I/O pins are in a high-impedance state. OE does not need to be actively controlled
for read and write cycles. In normal operation, OE can be tied low.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an
internal pullup.
TMS
TDI
Test Mode Select
Test Data Input
I
I
N/A
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This
pin has an internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising
edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an
internal pullup.
TCK
TDO
Test Clock
I
O
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the
state of the TAP controller.
Test Data Output
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required.
JTAG reset occurs automatically at power up and also resets using TMS and TCK per IEEE
1149.1. If not used TRST can be left floating. This pin has an internal pullup.
JTAG Reset
(Optional)
LOW
TRST
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V3548 to its lowest power consumption level. Data retention is guaranteed in Sleep
Mode. This pin has an internal pulldown
ZZ
Sleep Mode
I
HIGH
VDD
VDDQ
VSS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
5296 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.422
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
256x18 BIT
MEMORY ARRAY
LBO
Address A [0:17]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5296 drw 01
,
Data I/O [0:15],
I/O P[1:2]
TMS
TDI
TCK
JTAG
(SA Version)
TDO
TRST
(optional)
RecommendedOperating
TemperatureandSupplyVoltage
RecommendedDCOperating
Conditions
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
V
Symbol
VDD
VDDQ
VSS
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
3.135
0
Typ.
Max.
Unit
SS
DD
DDQ
V
3.3
3.465
V
V
V
V
V
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
3.3
3.465
3.3V±5%
0
0
5296 tbl 05
NOTES:
1. TA is the "instant on" case temperature.
____
VIH
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
VDD +0.3
VDDQ +0.3(2)
0.8
____
____
VIH
2.0
VIL
-0.3(1)
V
5296 tbl 04
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
6.42
3
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18
Absolute Maximum Ratings (1)
Commercial &
Industrial Values
Symbol
Rating
Unit
(2)
TERM
V
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
NC
NC
A
NC
NC
10
(3,6)
(4,6)
(5,6)
2
TERM
DD
V
Terminal Voltage with
Respect to GND
-0.5 to V
V
V
3
4
V
DDQ
V
DDQ
5
V
SS
76
75
74
73
VSS
TERM
V
DD
Terminal Voltage with
Respect to GND
-0.5 to V +0.5
6
NC
NC
NC
I/OP1
I/O
I/O
7
8
I/O8
7
9
I/O9
72
71
70
6
TERM
V
DDQ
Terminal Voltage with
Respect to GND
-0.5 to V +0.5
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
V
SS
V
DDQ
DDQ
I/O10
69
68
67
66
I/O
I/O
5
Commercial
Operating Temperature
-0 to +70
-40 to +85
-55 to +125
-55 to +125
oC
oC
oC
oC
W
I/O11
(1)
4
V
DD
V
SS
(7)
(1)
V
DD
V
V
V
DD
A
T
(1)
65
64
V
DD
DD
(3)
Industrial
Operating Temperature
V
SS
SS/ZZ
63
62
I/O12
I/O13
I/O
I/O
3
2
61
60
59
V
DDQ
V
V
DDQ
SS
BIAS
T
Temperature
Under Bias
VSS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
0
58
57
56
55
STG
T
Storage
Temperature
VSS
V
V
SS
54
53
,
V
DDQ
NC
NC
NC
DDQ
NC
NC
NC
P
T
Power Dissipation
DC Output Current
2.0
50
52
51
OUT
I
mA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5296 drw 02
5296 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH.
2. VDD terminals only.
3. VDDQ terminals only.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
100Pin TQFPCapacitance(1)
(TA = +25° C, f = 1.0MHz)
7. TA is the "instant on" case temperature.
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
119 BGA Capacitance(1)
5
7
pF
(TA = +25° C, f = 1.0MHz)
CI/O
pF
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
5296 tbl 07
7
7
pF
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
CI/O
pF
5296 tbl 07a
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
TBD pF
CI/O
TBD pF
5296 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.442
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(2)
ADV/LD
3
2
9
NC
NC
CE2
NC
NC
NC
2
CE
7
A
DD
V
13
17
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
V
V
V
V
9
I/O
6
I/O
NC
DDQ
CE1
NC
5
I/O
DDQ
V
V
NC
OE
10
I/O
4
I/O
NC
NC
G
H
J
NC(2)
BW2
11
I/O
SS
SS
3
I/O
NC
V
V
V
V
V
V
NC
R/W
DD(1)
SS
DD(1)
SS
DDQ
V
DD
DD
V
DD
DDQ
V
V
V
12
2
I/O
NC
I/O
NC
CLK
NC
NC
K
L
13
I/O
SS
1
I/O
V
NC
BW1
DDQ
14
SS
SS
V
DDQ
V
V
I/O
NC
V
V
V
NC
M
N
P
R
T
CEN
15
SS
SS
1
SS
0
I/O
I/O
NC
A
A
V
V
NC
P2
0
SS
P1
I/O
I/O
NC
5
DD
V
12
A
NC
NC
A
VDD(1)
14
NC
LBO
(5)
10
15
A
11
A
A
NC
A
NC/ZZ
,
(3)
(3)
(3)
(3)
(3,4)
NC/TMS
NC/TDI
NC/TCK
NC/TDO
NC/
DDQ
V
TRST
DDQ
V
5296 drw 13
U
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.42
5
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
A8
11
(2)
(2)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A7
NC
ADV/LD
NC
A10
CE1
BW2
NC
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CEN
R/W
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(2)
(2)
A6
CE2
NC
A9
NC
BW1
VSS
OE
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A2
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
A15
I/OP1
I/O7
I/O6
I/O5
I/O4
I/O8
I/O9
I/O10
I/O11
VSS
VSS
VSS
G
H
J
VSS
(1)
(1)
(5)
VDD
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
VDD
VSS
NC/ZZ
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A14
NC
K
L
M
N
P
VSS
NC
VSS
NC
VSS
NC
(1)
NC/TRST(3, 4)
VDD
NC
(2)
(3)
(3)
NC
NC/TDI
A1
NC/TDO
NC
(2)
(3)
R
NC
NC/TMS(3)
NC/TCK
4
A
3
A
0
A
12
A
13
A
16
A
17
A
LBO
5296 tbl 25
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 supports ZZ (sleep mode) on the latest die revision.
6.462
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1)
R/W
Chip(5)
Enable
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
(2 cycles later)
(7)
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
BURST WRITE
D
(7)
Q
(7)
Valid
LOAD WRITE /
BURST WRITE
D
(2)
(Advance burst counter)
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(2)
(Advance burst counter)
DESELECT or STOP(3)
NOOP
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
HiZ
HiZ
X
X
DESELECT / NOOP
X
(4)
SUSPEND
Previous Value
5296 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes (1)
(3)
(3)
OPERATION
R/W
H
L
BW1
X
BW2
X
BW3
BW4
READ
X
L
X
L
WRITE ALL BYTES
L
L
(2)
(2)
P1
WRITE BYTE 1 (I/O[0:7], I/O )
L
L
H
H
H
H
H
H
P2
WRITE BYTE 2 (I/O[8:15], I/O )
NO WRITE
L
H
L
L
H
H
H
5296 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
7
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5296 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5296 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram (1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A17)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:15], I/O P[1:2]
,
5296 drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.482
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles (2)
CE(1)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWx
X
X
X
X
X
X
X
X
L
OE
X
X
L
0
A
n
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
X
X
Load read
Burst read
Load read
Deselect or STOP
NOOP
n+1
X
X
L
1
A
0
Q
n+2
0+1
Q
n+3
X
X
H
X
L
L
1
Q
n+4
L
2
A
n+5
X
X
L
Z
Z
Load read
Burst read
Deselect or STOP
Load write
Burst write
Load write
Deselect or STOP
NOOP
n+6
X
X
X
H
L
2
Q
n+7
3
A
2+1
Q
n+8
L
n+9
X
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
4
A
3
D
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
L
3+1
D
X
X
X
X
L
H
X
L
X
X
L
4
D
5
A
Z
Z
Load write
Load read
Load write
Burst write
Load read
Burst read
Load write
6
A
H
L
L
X
L
7
A
5
D
L
6
Q
X
X
H
X
L
X
L
L
8
A
7
D
X
X
L
X
X
L
7+1
D
X
X
L
9
A
8
Q
5296 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Read Operation (1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
0
A
n
H
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
L
X
X
0
Q
0
X
X
X
L
Contents of Address A Read Out
5296 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
9
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation (1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
X
L
0
n
A
H
X
X
X
X
H
X
X
H
L
H
H
H
H
L
X
X
Address and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
L
X
Clock Setup Valid, Advance Counter
0
Q
0
X
L
X
Address A Read Out, Inc. Count
0+1
Q
0+1
X
L
X
L
Address A Read Out, Inc. Count
0+2
Q
0+2
X
L
X
L
Address A Read Out, Inc. Count
1
A
0+3
Q
0+3
1
L
L
X
L
Address A Read Out, Load A
0
Q
0
X
X
H
H
L
X
L
X
L
Address A Read Out, Inc. Count
1
Q
1
X
L
X
L
Address A Read Out, Inc. Count
2
A
1+1
Q
1+1
2
L
L
X
L
Address A Read Out, Load A
5296 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation (1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
0
A
n
L
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
L
X
X
0
D
0
X
L
X
X
Write to Address A
5296 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation (1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
X
X
X
X
X
X
X
X
0
A
n
L
X
X
X
X
L
L
H
H
H
H
L
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
A1
X
X
X
L
L
0
D
0
X
L
L
Address A Write, Inc. Count
0+1
D
0+1
X
L
L
Address A Write, Inc. Count
0+2
D
0+2
X
L
L
Address A Write, Inc. Count
0+3
D
0+3
1
L
L
L
Address A Write, Load A
0
D
0
X
X
L
H
H
L
X
L
L
Address A Write, Inc. Count
1
D
1
X
L
L
Address A Write, Inc. Count
2
A
1+1
D
1+1
2
L
L
L
Address A Write, Load A
5296 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1402
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used (1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
L
0
A
n
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
X
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
A1
X
X
L
H
L
X
X
Clock Valid
0
Q
0
X
X
L
H
H
L
X
Clock Ignored. Data Q is on the bus.
0
Q
0
X
X
L
Clock Ignored. Data Q is on the bus.
2
A
0
Q
0
X
L
Address A Read out (bus trans.)
3
A
1
Q
1
L
L
X
L
Address A Read out (bus trans.)
A4
L
L
X
L
Q2
Address A2 Read out (bus trans.)
5296 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used (1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
X
X
X
X
X
0
A
n
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
L
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
H
L
X
L
1
A
X
X
X
X
L
H
H
L
X
X
L
Clock Ignored.
Clock Ignored.
2
A
0
D
0
Write Data D
3
A
1
D
1
L
L
L
Write Data D
4
A
2
D
2
L
L
L
Write Data D
5296 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with CHIP Enable Used (1)
(3)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
Deselected.
0
A
Z
Z
Address and Control meet setup
Deselected or STOP.
X
H
L
1
A
0
Q
0
1
Address A Read out. Load A .
X
X
H
H
L
X
L
Z
Deselected or STOP.
1
1
Q
Z
Z
Address A Read out. Deselected.
2
A
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
2
Q
2
Address A Read out. Deselected.
5296 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used (1)
(3)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
Deselected.
A0
X
Z
Address and Control meet setup
Deselected or STOP.
Address D0 Write in. Load A1.
Deselected or STOP.
X
L
H
L
X
L
Z
A1
X
D0
Z
X
X
L
H
H
L
X
X
L
1
D
1
X
Address D Write in. Deselected.
A2
X
Z
Z
Address and control meet setup.
Deselected or STOP.
X
X
H
H
X
X
X
D2
Address D2 Write in. Deselected.
5296 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1422
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
|ILI
|ILI
|ILO
VOL
Parameter
Test Conditions
Min.
Max.
Unit
___
|
Input Le akage Curre nt
V
DD = Max., VIN = 0V to VDD
5
µA
LBO, JTAG and ZZ Input Leakage Current(1)
Output Leakage Curre nt
___
___
___
|
V
DD = Max., VIN = 0V to VDD
30
5
µA
µA
V
|
V
OUT = 0V to VDDQ, De vice De se le cted
Output Low Voltage
IOL = +8mA, VDD = Min.
OH = -8mA, VDD = Min.
0.4
___
V
OH
Output High Voltage
I
2.4
V
5296 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%)
133MHz
100MHz
Com'l
Symbol
Parameter
Test Conditions
Com'l
Ind
Ind
Unit
IDD
Device Selected, Outputs Open,
ADV/LD = X, VDD = Max.,
Operating Power
Supply Current
300
40
310
250
255
mA
(2)
VIN > VIH or < VIL, f = fMAX
ISB1
ISB2
ISB3
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
CMOS Standby Power
Supply Current
45
120
45
40
45
110
45
mA
mA
(2,3)
f = 0
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
Clock Running Power
Supply Current
110
40
100
40
(2.3)
f = fMAX
Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
Idle Power
Supply Current
mA
(2,3)
VIN > VHD or < VLD, f = fMAX
5296 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Loads
AC Test Conditions
(VDDQ = 3.3V)
VDDQ/2
50Ω
6
5
4
I/O
Input Pulse Levels
0 to 3V
2ns
Z0 = 50Ω
,
5296 drw 04
Input Rise/Fall Times
Figure 1. AC Test Load
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
1.5V
3
∆tCD
(Typical, ns)
See Figure 1
2
5296 tbl 23
1
,
20 30 50
80 100
Capacitance (pF)
200
5296 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
13
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
tCYC
Clock Cycle Time
7.5
10
ns
MHz
ns
____
____
(1)
Clock Frequence
133
100
tF
____
____
(2)
Clock High Pulse Width
Clock Low Pulse Width
2.2
2.2
3.2
3.2
tCH
____
____
(2)
ns
tCL
Output Parameters
____
____
tCD
Clock High to Valid Data
4.2
5
ns
ns
ns
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
1.5
1.5
1.5
1.5
____
____
(3, 4,5)
tCL Z
(3, 4,5)
1.5
3
1.5
3.3
ns
ns
ns
ns
tCHZ
____
____
tOE
4.2
5
____
____
(3,4)
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
tOLZ
____
____
(3,4)
4.2
5
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSE
Clock Enable Setup Time
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
tSA
tSD
tSW
tSADV
tSC
Address Setup Time
Data In Setup Time
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
tSB
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHE
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tHA
tHD
tHW
tHADV
tHC
Address Hold Time
Data In Hold Time
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
tHB
ns
5296 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.1442
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle (1,2,3,4)
,
,
6.42
15
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles (1,2,3,4,5)
,
,
6.1462
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles (1,2,3)
,
,
,
6.42
17
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation (1,2,3,4)
,
6.1482
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation (1,2,3,4)
,
6.42
19
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
JCYC
t
tJR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
JDC
t
JS
t
JH
t
Device Outputs(2)/
TDO
tJRSR
JCD
t
3)
(
x
TRST
M5296 drw 01
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
tJCYC
tJCH
tJCL
tJR
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
Register Name
Instruction (IR)
Bit Size
____
____
ns
4
1
40
ns
Bypass (BYR)
5(1)
ns
____
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
tJF
5(1)
ns
____
Note (1)
____
tJRST
tJRSR
tJCD
tJDC
tJS
50
ns
I5296 tbl 03
____
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
20
ns
____
0
ns
____
____
25
25
ns
tJH
JTAG Hold
ns
I5296 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.2402
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Revision Number (31:28)
Value
0x2
Description
Reserved for version number.
IDT Device ID (27:12)
0x20A
0x33
1
Defines IDT part number 71V3548SA.
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
ID Register Indicator Bit (Bit 0)
I5296 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5296 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
21
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack Package Diagram Outline
6.2422
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
23
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
165 Fine PItch Ball Grid Array (fBGA) Package Diagram Outline
6.2442
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation (1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
,
5296 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
XX
IDT
71V3548
XX
XX
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
PF*
BG
BQ
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
,
165 fine Pitch Ball Grid Array (fBGA)
133
100
Clock Frequency in Megahertz
S
SA
Standard Power
Standard Power with JTAG Interface
* JTAG (SA version) is not available with 100-pin TQFP package
5296 drw 12
6.42
25
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
04/30/00
CreatedpreliminaryZBTdatasheetfrom71V3558datasheet.
ChangedtCDC, tCLZ, andtCHZ minimums from1.0ns to1.5ns.
AddclarificationnotetoRecommendedOperatingTemperatureandAbsoluteMaxRatings
tables
Pg. 3,4
Pg. 4
AddBGAcapacitancetable
Pg. 4,5
Pg. 20
AddnotestoPinconfigurations
InsertTQFPPackageDiagramOutline
05/26/00
07/26/00
Addnewpackageoffering,13x15mmfBGA
Correct119BGAPackageDiagramOutline
Add ZZ sleep mode reference note to TQFP, BG and BQ pinouts
UpdateBQ165pinout
Pg. 23
Pg. 4-6
Pg. 6
Pg. 21
UpdateBG119packagediagramoutlinedimensions
RemovePreliminaryStatus
10/25/00
05/20/02
Pg. 6
Pg. 1-6,13,20,21,25
Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
AddedJTAG"SA"versionfunctionalityandupdatedZZpindescriptions andnotes.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
sramhelp@idt.com
800-544-7726, x4033
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
6.2462
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