IDT71V3557S85PFG8 [IDT]
Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFP-100;
| 型号： | IDT71V3557S85PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总28页 (文件大小：994K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K x 36, 256K x 18,
IDT71V3557S
IDT71V3559S
IDT71V3557SA
IDT71V3559SA
3.3V Synchronous ZBT™ SRAMs
3.3V I/O, Burst Counter,
Flow-Through Outputs
Features
it read or write.
◆
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
The IDT71V3557/59 contain address, data-in and control signal
registers.Theoutputsareflow-through(nooutputdataregister).Output
enable is the only asynchronous signal and can be used to disable the
outputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V3557/59
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired.Ifanyoneofthesethreeisnotasserted
when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will
be completed. The data bus will tri-state one cycle after chip is de-
selectedorawriteisinitiated.
The IDT71V3557/59 have an on-chip burst counter. In the burst
mode, the IDT71V3557/59 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter
(ADV/LD = HIGH).
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates
the need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)
Optional Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array (fBGA)
◆
◆
◆
◆
◆
◆
◆
Description
TheIDT71V3557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-
bit)synchronous SRAMs organizedas 128Kx36/256Kx18. Theyare
designed to eliminate dead bus cycles when turning the bus around
between reads and writes, or writes and reads. Thus they have been
given the name ZBTTM, or Zero Bus Turnaround.
The IDT71V3557/59 SRAMs utilize IDT's latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pin thinplasticquadflatpack(TQFP)aswellasa119 ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andonthenextclockcycletheassociateddatacycleoccurs,be
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE2, CE2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW1, BW2, BW3, BW4
CLK
ADV/LD
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
LBO
TMS
Synchronous
Synchronous
N/A
TDI
TCK
Te s t Cl o c k
TDO
Te s t Data Outp ut
Synchronous
Asynchronous
Synchronous
Synchronous
Static
JTAG Reset (Optional)
Sleep Mode
TRST
ZZ
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Ground
Supply
Supply
VSS
Static
52 82 tb l 01
DECEMBER 2005
1
©2004IntegratedDeviceTechnology,Inc.
DSC-5282/08
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions (1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/ is low with the chip
LD
deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is
sampled high.
R/W
Read / Write
Clock Enable
I
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place one clock cycle later.
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if
the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge
of clock.
CEN
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid.
The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when
R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW1-BW4
can all be tied low if always doing write to the entire 36-bit word.
BW1-BW4
Chip Enables
Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V3557/59. (CE1 or
CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect
cycle. The ZBTTM has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is
initiated.
,
2
CE1 CE
CE2
Chip Enable
Clock
I
I
HIGH
N/A
Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted
polarity but otherwise identical to CE1 and CE2.
CLK
This is the clock input to the IDT71V3557/59. Except for OE, all timing references for the device are made
with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
Linear Burst Order
Output Enable
I/O
I
N/A
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data
output path is flow-through (no output register).
LOW
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation..
LBO
I
Asynchronous output enable. OE must be low to read data from the 71V3557/59. When OE is HIGH the I/O
pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In
normal operation, OE can be tied low.
OE
TMS
TDI
Test Mode Select
Test Data Input
I
I
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Test Data Output
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup.
JTAG Reset
(Optional)
I
I
LOW
HIGH
TRST
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3557/3559 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
ZZ
Sleep Mode
VDD
VDDQ
VSS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
5282 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.422
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram 128K x 36
LBO
128K x 36 BIT
MEMORY ARRAY
Address A [0:16]
D
D
Q
Q
Address
1, CE2
CE
2
CE
R/W
Control
CEN
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
Clock
Gate
OE
TMS
TDI
TCK
Data I/O [0:31], I/O P[1:4]
,
JTAG
(SA Version)
TDO
5282 drw 01
TRST
(optional)
6.42
3
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram 256K x 18
256K x 18 BIT
MEMORY ARRAY
LBO
Address A [0:17]
D
D
Q
Q
Address
CE1, CE2 CE2
R/W
CEN
Control
ADV/LD
DI
DO
x
BW
D
Q
Control Logic
Clk
Mux
Sel
Clock
Gate
OE
,
Data I/O [0:15], I/O P[1:2]
TMS
TDI
TCK
JTAG
(SA Version)
5282 drw 01a
TDO
TRST
(optional)
RecommendedDCOperating
Conditions
Symbol
Parameter
Min. Typ.
3.135 3.3
3.135 3.3
Max.
Unit
V
VDD Core Supply Voltage
VDDQ I/O Supply Voltage
3.465
3.465
V
VSS
VIH
VIH
VIL
Ground
0
0
0
V
____
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
VDD + 0.3
VDDQ + 0.3(2 )
0.8
V
____
____
2.0
V
-0.3(1 )
V
5282 tbl 04
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
6.442
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
VSS
0V
0V
VDD
VDDQ
Commercial
Industrial
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
5282 tbl 05
NOTES:
1. TA is the "instant on" case temperature.
Pin Configuration 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
79
78
77
3
4
V
DDQ
V
DDQ
5
VSS
I/O18
I/O19
I/O20
I/O21
76
75
74
73
VSS
I/O13
I/O12
I/O11
I/O10
6
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
SS
VDDQ
I/O22
V
DDQ
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O9
I/O8
I/O23
(1)
V
SS
V
VSS
SS
(1)
V
DD
DD
(2)
V
V
DD
(1,4)
VSS/ZZ
I/O
I/O6
V
SS
I/O24
I/O25
7
V
DDQ
V
DDQ
V
SS
V
SS
I/O26
I/O27
I/O28
I/O29
I/O
5
I/O4
I/O3
I/O
2
V
SS
V
SS
V
DDQ
V
DDQ
I/O30
I/O31
I/OP4
I/O1
I/O0
I/OP1
,
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5282 drw 02
Top View
100TQFP
NOTES:
1. Pins 14, 64, and 66 do not have to be connected directly to VSS as long as the input voltage is< VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. Pins 83 and 84 are reserved for future 8M and 16M respectively.
4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.
6.42
5
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 18
Absolute Maximum Ratings (1)
Commercial &
Industrial Values
Symbol
Rating
Unit
(2 )
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
NC
NC
DDQ
V
SS
V
NC
NC
10
A
(3,6)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
2
NC
NC
3
4
DDQ
V
V
5
(4,6)
76
75
74
73
SS
VTERM
Terminal Voltage with
Respect to GND
6
NC
7
P1
I/O
8
8
I/O
7
I/O
(5,6)
9
9
I/O
72
71
70
6
I/O
VTERM
Terminal Voltage with
Respect to GND
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
SS
V
V
DDQ
V
DDQ
5
69
68
67
66
10
I/O
I/O
11
Commercial
Operating Temperature
oC
oC
oC
oC
W
I/O
4
I/O
(1)
SS
V
SS
V
(7)
(1)
TA
VDD
(2)
VSS
65
64
DD
DD
V
SS/ZZ
V
3
I/O
2
I/O
V
Industrial
Operating Temperature
-40 to +85
(1,4)
SS
V
63
62
61
60
59
58
57
56
55
12
I/O
13
I/O
DDQ
DDQ
V
V
V
TBIAS
Temperature
Under Bias
-55 to +125
SS
14
V
I/O
SS
1
I/O
15
I/O
0
I/O
NC
NC
P2
I/O
Storage
Temperature
-55 to +125
TSTG
NC
SS
V
SS
V
V
,
54
53
DDQ
V
DDQ
PT
Power Dissipation
DC Output Current
2.0
50
NC
NC
NC
NC
NC
NC
52
51
IOUT
mA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5282 tbl 06
5282 drw 02a
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
100TQFP
NOTES:
1. Pins14,64,and66donothavetobeconnecteddirectlytoVSSaslongastheinputvoltage
is < VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage
is > VIH.
3. Pins 83 and 84 are reserved for future 8M and 16M respectively.
4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.
7. TA is the "instant on" case temperature.
100TQFPCapacitance(1)
(TA = +25°C, F = 1.0MHZ)
119BGACapacitance(1)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
(TA = +25°C, F = 1.0MHZ)
Symbol
CIN
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
5
7
pF
7
7
pF
CI/O
pF
5282 tbl 07
CI/O
pF
5282 tbl 07a
119BGACapacitance(1)
(TA = +25°C, F = 1.0MHZ)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
TBD pF
CI/O
TBD pF
5282 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.462
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
B
C
D
E
F
NC(3)
ADV/LD
2
3
A
9
NC
NC
CE
NC
NC
2
CE
7
2
A
DD
12
15
A
A
V
A
16
I/O
P3
I/O
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
SS
SS
13
I/O
14
I/O
1
CE
DDQ
19
I/O
12
I/O
DDQ
V
V
V
V
V
V
OE
20
I/O
21
I/O
11
I/O
10
I/O
NC(3)
G
H
J
2
BW3
BW
22
I/O
23
I/O
SS
SS
9
I/O
8
I/O
V
V
V
V
R/W
DDQ
24
DD
DD
V
DD
V
DDQ
DD(2)
SS(1)
SS
V
V
26
I/O
SS
6
I/O
7
I/O
I/O
V
CLK
NC
K
L
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
1
BW
DDQ
29
28
I/O
SS
SS
SS
SS
SS
SS
3
I/O
DDQ
V
V
V
V
V
V
M
N
P
R
T
CEN
30
I/O
1
A
2
I/O
1
I/O
I/O
31
I/O
P4
I/O
0
A
P1
I/O
0
I/O
5
DD
VSS(1)
14
13
NC
NC
DDQ
A
NC
V
A
A
NC
LBO
(6)
10
11
A
A
NC
NC/ZZ
,
(4)
(4)
(4)
(4)
(4,5)
DDQ
V
NC/TDI
NC/TCK
V
NC/TMS
U
NC/
TRST
NC/TDO
5282 drw 13A
Top View
Pin Configuration - 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(3)
3
2
9
NC
NC
CE2
NC
NC
NC
2
CE
ADV/
LD
7
A
DD
13
17
A
V
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
P1
I/O
NC
V
V
V
NC
V
V
V
V
9
7
I/O
NC
DDQ
I/O
NC
1
CE
NC
6
I/O
DDQ
V
V
OE
10
5
I/O
NC
I/O
NC
NC
G
H
J
NC(3)
BW2
11
I/O
SS
V
SS
4
I/O
V
NC
R/W
DD(2)
SS(1)
DDQ
DD
DD
V
DD
DDQ
V
V
V
V
V
V
V
V
12
SS
SS
3
I/O
NC
I/O
NC
CLK
NC
NC
K
L
13
I/O
SS
2
I/O
V
V
V
V
NC
1
BW
DDQ
14
I/O
SS
SS
SS
SS
SS
SS
DDQ
V
V
V
V
V
NC
M
N
P
R
T
CEN
15
I/O
1
A
1
I/O
NC
NC
P2
I/O
0
A
0
I/O
NC
NC
NC
DDQ
NC
5
A
DD
12
11
V
VSS(1)
14
A
NC
LBO
(6)
10
15
NC/ZZ
A
A
NC
A
A
,
(4)
(4)
(4)
(4,5)
(4)
DDQ
V
NC/TDI
NC/TCK
NC/TDO
NC/TRST
V
NC/TMS
U
5282 drw 13B
Top View
NOTES:
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. J3 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.
3. G4 and A4 are reserved for future 8M and 16M respectively.
4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.
6. Pin T7 supports ZZ (sleep mode) for the latest die revisions.
6.42
7
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(3)
(3)
A
B
C
D
E
F
NC
A
ADV/LD
OE
NC
A
NC
7
8
CE
BW
BW
BW
CE
2
CEN
R/W
1
3
2
(3)
(3)
NC
A
6
CE
2
CLK
NC
A
9
NC
I/O
BW
4
1
I/O
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
NC
I/O
P3
DDQ
P2
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
14
17
16
DDQ
15
I/O
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
13
I/O
12
19
DDQ
I/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
I/O
10
DDQ
11
G
H
J
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
8
23
22
DDQ
DD
SS
SS
SS
DD
DDQ
9
(1)
(2)
(6)
V
SS
V
DD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
I/O
NC/ZZ
I/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
6
7
K
L
M
N
P
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
4
27
26
DDQ
DD
SS
SS
SS
DD
DDQ
5
I/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
I/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
(1)
NC/
TRST(4, 5)
I/O
P4
NC
V
DDQ
V
SS
NC
V
SS
V
SS
V
DDQ
NC
I/O
P1
(3)
(4)
(4)
NC
LBO
NC
A
A
NC/TDI
A
NC/TDO
A
10
A
A
14
NC
5
2
1
13
(3)
(4)
R
NC
A
A
NC/TMS(4)
A
NC/TCK
A
A
A
15
A
16
4
3
0
11
12
5282 tbl 25
Pin Configuration - 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(3)
(3)
A
B
C
D
E
F
NC
NC
A
NC
ADV/LD
NC
A
A
10
7
8
CE
BW
CE
2
CEN
R/W
1
2
(3)
(3)
A
6
CE
2
NC
CLK
NC
A
9
NC
BW
OE
1
NC
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
NC
NC
NC
NC
NC
NC
I/O
P1
DDQ
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
7
8
DDQ
NC
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
6
9
DDQ
NC
I/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
5
DDQ
G
H
J
NC
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
4
11
DDQ
Vss(1)
V
DD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC/ZZ
(2)
(6)
I/O
NC
NC
NC
NC
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
3
NC
12
DDQ
K
L
M
N
P
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
2
NC
13
DDQ
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
1
NC
14
DDQ
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
0
NC
15
DDQ
(1)
I/O
V
DDQ
V
SS
NC
V
SS
V
SS
V
DDQ
NC
NC
P2
NC/
TRST(4, 5)
(3)
(4)
(4)
NC
LBO
NC
A
5
A
2
NC/TDI
A
1
NC/TDO
A
11
A
A
15
NC
14
(3)
(4)
R
NC
A
4
A
3
NC/TMS(4)
A
0
NC/TCK
A
12
A
A
16
A
17
13
5282 tbl 25a
NOTES:
1. H1 and N7 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. H2 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.
3. A9, B9, B11, A1, R2, and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively.
4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.
6. Pin H11 supports ZZ (sleep mode) for the latest die revisions.
6.482
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1)
,
CEN
CE1
CE2
BWx
R/W
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(5 )
(One cycle later)
(7 )
L
L
L
L
H
X
L
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D
(7 )
L
Q
(7 )
X
Valid
LOAD WRITE /
BURST WRITE
BURST WRITE
D
(Advance burst counter)(2 )
(7 )
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(Advance burst counter)(2 )
L
L
H
X
X
X
H
X
X
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3 )
NOOP
HIZ
HIZ
DESELECT / NOOP
X
(4 )
SUSPEND
Previous Value
5282 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes (1)
(3 )
(3 )
BW1
X
BW2
X
BW3
BW4
OPERATION
R/W
H
L
READ
X
L
X
L
WRITE ALLBYTES
WRITE BYTE 1 (I/O[0:7], I/OP1)
L
L
(2 )
(2 )
L
L
H
H
H
L
H
H
H
L
WRITE BYTE 2 (I/O[8:15], I/OP2)
L
H
L
(2,3)
WRITE BYTE 3 (I/O[16:23], I/OP3)
L
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)
L
H
H
H
H
NO WRITE
L
H
H
H
5282 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
Second Address
Third Address
1
0
1
1
0
0
1
0
0
1
Fourth Address(1)
1
0
1
0
0
5282 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
6.42
9
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5282 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram (1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A16
)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
,
I/O [0:31], I/O P[1:4]
5282 drw 03
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.1402
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles (2)
(1 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
L
D1
Q0
Load read
Burst read
n+1
X
L
n+2
A1
X
L
Q0+1 Load read
n+3
H
X
L
L
Q1
Z
Deselect or STOP
n+4
X
X
X
L
NOOP
n+5
A2
X
Z
Load read
Burst read
n+6
X
H
L
Q2
n+7
X
L
Q2+1 Deselect or STOP
n+8
A3
X
X
X
X
X
X
X
X
L
Z
Load write
Burst write
n+9
X
L
X
L
L
D3
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A4
X
L
D3+1 Load write
X
X
L
H
X
L
X
X
L
D4
Z
Deselect or STOP
X
NOOP
A5
A6
A7
X
Z
Load write
Load read
Load write
Burst write
H
L
L
X
L
D5
Q6
D7
L
X
H
X
L
X
L
L
X
X
L
A8
X
X
X
L
D7+1 Load read
Q8 Burst read
Q8+1 Load write
X
L
A9
L
5282 tbl 12
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
6.42
11
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation (1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
H
X
L
L
L
X
X
X
L
X
Address and Control meet setup
Contents of Address A0 Read Out
n+1
X
X
X
Q0
5282 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Read Operation (1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
H
X
X
X
X
H
X
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
Address and Control meet setup
Address A0 Read Out, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
X
X
L
Q0
X
Q0+1 Address A0+1 Read Out, Inc. Count
X
Q0+2
Q0+3
Q0
Address A0+2 Read Out, Inc. Count
Address A0+3 Read Out, Load A1
Address A0 Read Out, Inc. Count
Address A1 Read Out, Inc. Count
X
A1
X
H
L
X
L
Q1
A2
Q1+1 Address A1+1 Read Out, Load A2
5282 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation (1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
L
L
L
L
L
L
X
X
X
Address and Control meet setup
Write to Address A0
n+1
X
X
X
X
D0
5282 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Write Operation (1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
L
X
X
X
X
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
Address and Control meet setup
Address A0 Write, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
X
X
L
D0
X
D0+1 Address A0+1 Write, Inc. Count
X
D0+2
D0+3
D0
Address A0+2 Write, Inc. Count
Address A0+3 Write, Load A1
Address A0 Write, Inc. Count
Address A1 Write, Inc. Count
X
A1
X
X
L
H
L
X
L
D1
A2
D1+1 Address A1+1 Write, Load A2
5282 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.1422
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used (1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
X
X
AddressA0 and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
L
A1
X
Q0
Q0
Q0
Q1
Q2
Q3
Address A0 Read out, Load A1
Clock Ignored. Data Q0 is on the bus.
Clock Ignored. Data Q0 is on the bus.
Address A1 Read out, Load A2
Address A2 Read out, Load A3
X
X
L
X
A2
A3
A4
L
L
Address A3 Read out, Load A4
5282 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation with Clock Enable Used (1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
Address A0 and Control meet setup.
Clock n+1 Ignored.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
L
A1
X
D0
X
Write data D0, Load A1.
Clock Ignored.
X
X
L
X
X
Clock Ignored.
A2
A3
A4
D1
D2
D3
Write Data D1, Load A2
Write Data D2, Load A3
Write Data D3, Load A4
L
L
5282 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42
13
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used (1)
(2 )
(3 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
CE1
H
H
L
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Z
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Deselected.
A0
X
Z
Address A0 and Control meet setup.
Address A0 read out, Deselected.
Address A1 and Control meet setup.
Address A1 read out, Deselected.
Deselected.
H
L
Q0
Z
A1
X
X
L
H
H
L
Q1
Z
X
X
X
L
A2
X
Z
Address A2 and Control meet setup.
Address A2 read out, Deselected.
Deselected.
H
H
Q2
Z
X
X
5282 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Write Operation with Chip Enable Used (1)
CE(2)
H
H
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
X
X
A0
X
A1
X
X
A2
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Z
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Deselected.
Z
Address A0 and Control meet setup
Data D0 Write In, Deselected.
Address A1 and Control meet setup
Data D1 Write In, Deselected.
Deselected.
X
L
H
L
X
L
D0
Z
X
X
L
H
H
L
X
X
L
D1
Z
Z
Address A2 and Control meet setup
Data D2 Write In, Deselected.
Deselected.
X
X
H
H
X
X
D2
Z
5282 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1442
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1 )
___
___
___
LBO, JTAG and ZZ Input Leakage Current
Output Leakage Current
Output Low Voltage
|ILI|
VDD = Max., VIN = 0V to VDD
VOUT = 0V to VCC
30
5
µA
µA
V
|ILO|
VOL
VOH
IOL = +8mA, VDD = Min.
IOH = -8mA, VDD = Min.
0.4
___
Output High Voltage
2.4
V
5282 tbl 21
NOTE:
1. The LBO, JTAG and ZZ pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
DC Electrical Characterics Over the Operating
Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%)
7.5ns
Com'l Only
275
8ns
8.5ns
Symbol
Parameter
Test Conditions
Com'l
Ind
Com'l
Ind
Unit
Operating Power
Supply Current
Device Selected, Outputs Open,
250
260
225
235
mA
IDD
ADV/LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX
(2 )
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = 0
40
105
40
40
100
40
45
110
45
40
95
40
45
105
45
mA
mA
ISB1
ISB2
ISB3
(2,3)
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
(2,3)
f = fMAX
Idle Power
Device Selected, Outputs Open,
mA
Supply Current
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX
(2,3)
5282 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
VDDQ/2
AC Test Loads
AC Test Conditions (VDDQ = 3.3V)
Input Pulse Levels
0 to 3V
Ω
50
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
2ns
I/O
Z0 = 50Ω
,
1.5V
5282 drw 04
6
5
4
3
Figure 1. AC Test Load
1.5V
Figure 1
5282 tbl 23
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
,
5282 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
7.5ns(5)
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
tCY C
Clock Cycle Time
10
2.5
2.5
10.5
2.7
11
3.0
3.0
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
tCH
____
____
____
(1)
2.7
tCL
Output Parameters
____
____
____
tCD
Clock High to Valid Data
7.5
8
8.5
ns
ns
ns
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
2
2
2
____
____
____
(2,3,4)
3
3
3
tCL Z
____
____
____
(2,3,4)
5
5
5
ns
ns
ns
ns
tCHZ
____
____
____
tOE
5
5
5
____
____
____
(2,3)
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
0
tOLZ
____
____
____
(2,3)
5
5
5
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSE
Clock Enable Setup Time
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
tSA
Address Setup Time
tSD
Data In Setup Time
tSW
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
tSADV
tSC
tSB
Hold Times
tHE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tHA
Address Hold Time
tHD
Data In Hold Time
tHW
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
tHADV
tHC
tHB
ns
5282 tbl 24
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and
voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions
(0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V).
5. Commercial temperature range only.
6.1462
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle (1,2,3,4)
.
,
6.42
17
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles (1,2,3,4,5)
.
,
6.1482
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles (1,2,3)
.
,
6.42
19
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation (1,2,3,4)
.
,
6.2402
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation (1,2,3,4)
.
,
6.42
21
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
t
JCYC
t
JR
t
JF
t
JCL
t
JCH
TCK
Device Inputs(1)/
TDI/TMS
JDC
t
t
JS
t
JH
Device Outputs(2)/
TDO
t
JRSR
t
JCD
3)
(
x
TRST
M5282 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
tJCYC
tJCH
tJCL
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
Register Name
Instruction (IR)
Bit Size
____
____
ns
4
1
40
ns
Bypass (BYR)
(1 )
____
tJR
5
ns
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
(1 )
____
tJF
5
ns
Note (1)
____
____
tJRST
tJRSR
tJCD
tJDC
tJS
50
ns
I5282 tbl 03
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
20
ns
____
0
ns
____
____
25
25
ns
tJH
JTAG Hold
ns
I5282 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.2422
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Revision Number (31:28)
Value
Description
0x2
0x209, 0x20B
0x33
Reserved for version number.
IDT Device ID (27:12)
Defines IDT part number 71V3557SA and 71V3559SA, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
ID Register Indicator Bit (Bit 0)
1
I5282 tbl 02
Available JTAG Instructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5282 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
23
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
100-Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.2442
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
25
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.2462
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation (1)
OE
tOE
tOHZ
tOLZ
DATA Out
Q
Q
,
5282 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
X
IDT
XXXX
XX
XX
X
XX
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
Restricted Hazardous Substance Device
G
PF**
BG
BQ
100-Pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
,
75*
80
85
Access time (tCD) in tenths of nanoseconds
Standard Power
Standard Power with JTAG Interface
S
SA
IDT71V3557
IDT71V3559
128Kx36 Flow-Through ZBT SRAM with 3.3V I/O
256Kx18 Flow-Through ZBT SRAM with 3.3V I/O
5282 drw 12
*Com m ercial tem perature range only.
** JTA G (S A version) is not available with 100-pin TQFP package
6.42
27
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
6/30/99
8/23/99
Updated to new format
Added Pin 64 to Note 1 and changed Pins 38, 42, and 43 to DNU
Changed U2–U6 to DNU
Pg. 5, 6
Pg. 7
Pg. 15
Improved tCH, tCL; revised tCLZ
Pg. 21
Added BGA package diagrams
Pg. 23
AddedDatasheetDocumentHistory
12/31/99
05/02/00
Pg. 5, 14, 15, 22
Pg. 5,6
AddedIndustrialTemperaturerangeofferings
InsertclarificationnotetoRecommendedOperatingTemperatureandAbsoluteMaxratings
tables
Pg. 5,6,7
Pg. 6
ClarifynoteonTQFPandBGApinconfigurations;correctedtypoinpinout
Add BGAcapacitancetable
Pg. 21
AddTQFPPackageDiagramOutline
05/26/00
07/26/00
Add new package offering 13 x 15mm 165 fBGA
Correct119BGAPackageDiagramOutline
Add ZZ sleep mode reference note to TQFP, BG119 and BQ165
UpdateBQ165pinout
Pg. 23
Pg. 5-8
Pg. 8
Pg. 23
UpdateBG119pinoutpackagediagramdimensions
Removepreliminarystatus
10/25/00
Pg. 8
Pg. 1-8,15,22,23,27
Pg. 7
Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
AddedJTAG"SA"versionfunctionalityandupdatedZZpindescriptions andnotes.
Updated pin configuration for the 119 BGA - reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
Added"Restrictedhazardoussubstancedevice"toorderinginformation.
05/20/02
10/15/04
12/07/05
Pg. 27
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Rd
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
800-345-7015 or
408/284-4555
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
6.2482
相关型号：
IDT71V3557S85PFGI
Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT
IDT71V3557S85PFI
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
IDT
IDT71V3557S85PFI8
ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT
IDT71V3557SA
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
IDT
IDT71V3557SA75BG
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
IDT
IDT71V3557SA75BGG
Cache SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, BGA-119
IDT
IDT71V3557SA75BGG8
Cache SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, BGA-119
IDT
IDT71V3557SA75BGI
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
IDT
©2020 ICPDF网 联系我们和版权申明