IDT71V35761SA183BQG [IDT]

3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect;


型号：	IDT71V35761SA183BQG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect 静态存储器
文件：	总21页 (文件大小：972K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

◆

128K x 36

IDT71V35761S/SA

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

Power down controlled by ZZ input

Features

128K x 36 memory configurations

Supports high system speed:

3.3V I/O

Commercial:

– 200MHz 3.1ns clock access time

CommercialandIndustrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO input selects interleaved or linear burst mode

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array

Green parts available, see ordering information

3.3V core power supply

FunctionalBlockDiagram

LBO

ADV

INTERNAL

ADDRESS

Sequence

Burst

CEN

128K x 36-

BIT

MEMORY

ARRAY

CLK

Burst

Logic

17/18

Binary

Counter

ADSC

A0*

A1*

CLR

ADSP

CLK EN

A0,A1

A2–A17

A0 - A16/17

ADDRESS

17/18

Byte 1

Write Register

BWE

Byte 1

Write Driver

BW1

BW2

Byte 2

Write Register

Byte 2

Write Driver

Byte 3

Write Register

Byte 3

Write Driver

BW3

BW4

Byte 4

Write Register

Byte 4

Write Driver

OUTPUT

CS0

Enable

CLK EN

DATA

INPUT

CS1

Powerdown

Enable

Delay

OUTPUT

BUFFER

I/O0 — I/O31

I/OP1 — I/OP4

5301 drw 01

TMS

TDI

TCK

JTAG

(SA Version)

TDO

TRST

(Optional)

NOVEMBER2014

DSC-5301/07

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

for one cycle before it is available on the next rising clock edge. If

burst mode operation is selected (ADV=LOW), the subsequent

three cycles of output data will be available to the user on the next

three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the LBO input pin.

The IDT71V35761 SRAMs utilize a high-performance CMOS

process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array(fBGA).

Description

The IDT71V35761 are high-speed SRAMs organized as

128Kx36.TheIDT71V35761SRAMscontainwrite,data,addressand

controlregisters. InternallogicallowstheSRAMtogenerateaself-timed

writebaseduponadecisionwhichcanbeleftuntiltheendofthewritecycle.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V35761canprovidefourcyclesofdatafor

a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating

the access sequence. The first cycle of output data will be pipelined

Pin Description Summary

0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW2, BW3, BW4

(1)

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

ADV

ADSC

ADSP

LBO

TMS

TDI

Synchronous

N/A

TCK

TDO

TRST

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

N/A

5301 tbl 01

6.422

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Definitions⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

0-A17

Address Inputs

N/A

Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and

ADSC Low or ADSP Low and CE Low.

Address Status

(Cache Controller)

LOW

Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the

address registers with new addresses.

ADSC

ADSP

ADV

Address Status

(Processor)

Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address

registers with new addresses. ADSP is gated by CE.

Burst Address

Advance

Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,

controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not

incremented; that is, there is no address advance.

Byte Write Enable

LOW

Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK

then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are

blocked and only GW can initiate a write cycle.

BWE

Individual Byte

Write Enables

Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte

BW1-BW4

write causes all outputs to be disabled.

Chip Enable

Clock

LOW

N/A

Synchronous chip enable. CE is used with CS

0 and CS1 to enable the IDT71V35761. CE also gates ADSP.

CLK

This is the clock input. All timing references for the device are made with respect to this input.

Chip Select 0

Chip Select 1

HIGH

LOW

Synchronous active HIGH chip select. CS

Synchronous active LOW chip select. CS

is used with CE and CS

to enable the chip.

is used with CE and CS

0 to enable the chip.

Global Write

Enable

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of

CLK. GW supersedes individual byte write enables.

I/O

I/OP1-I/OP4

-I/O31

Data Input/Output

I/O

N/A

Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and

triggered by the rising edge of CLK.

Linear Burst Order

LOW

Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected. When

LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the

device is operating.

LBO

Output Enable

LOW

Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is

also selected. When OE is HIGH the I/O pins are in a high-impedance state.

TMS

TDI

Test ModeSelect

Test Data Input

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal

pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while

test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TCK

TDO

Test Clock

N/A

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP

controller.

Test DataOutput

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset

occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can

be left floating. This pin has an internal pullup. Only available in BGA package.

JTAG Reset

(Optional)

LOW

TRST

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761 to its

lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down.

Sleep Mode

HIGH

DDQ

Power Supply

Ground

N/A

3.3V core power supply.

3.3V I/O Supply.

Ground.

No Connect

NC pins are not electrically connected to the device.

5301tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage

Commercial &

Symbol

Rating

Industrial

Unit

Grade

Commercial

Industrial

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

DDQ

(2)

TERM

Terminal Voltage with

Respect to GND

-0.5 to +4.6

3.3V±5%

(3,6)

(4,6)

(5,6)

TERM

Terminal Voltage with

Respect to GND

-0.5 to VDD

-0.5 to VDD +0.5

-0.5 to VDDQ +0.5

-0 to +70

5301 tbl 04

NOTES:

1. TA is the "instant on" case temperature.

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

RecommendedDCOperating

Conditions

Commercial

^oC

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Min. Typ.

3.135 3.3

Max.

Unit

Operating Temperature

A⁽⁷⁾

DDQ

3.465

Industrial

-40 to +85

Operating Temperature

Te mp e rature

Under Bias

-55 to +125

TBIAS

____

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

2.0

DD +0.3

Storage

-55 to +125

TSTG

2.0

DDQ +0.3⁽¹⁾

0.8

____

Te mp e rature

-0.3⁽²⁾

Power Dissipation

DC Output Current

2.0

IOUT

5301 tbl 06

NOTES:

5301 tbl 03

1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

119BGACapacitance

100 Pin TQFP Capacitance

(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

Symbol

CIN

CI/O

5301 tbl 07

5301 tbl 07a

165fBGACapacitance

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

Max. Unit

CIN

CI/O

VOUT = 3dV

5301 tbl 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.442

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 128K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/OP3

I/O16

I/O17

I/OP2

I/O15

I/O14

VDDQ

I/O18

I/O19

I/O20

I/O21

I/O13

I/O12

I/O11

I/O10

VSS

DDQ

I/O22

I/O

I/O23

DD / NC⁽¹⁾

VSS

VDD

I/O24

I/O25

ZZ⁽²⁾

I/O

DDQ

VSS

I/O26

I/O27

I/O28

I/O29

I/O

VSS

DDQ

I/O30

I/O31

I/OP4

I/O

I/OP1

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5301drw 02

100TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 128K x 36, 119 BGA

DDQ

ADSP

ADSC

I/O

DDQ

I/O

DDQ

I/O

ADV

I/O

DDQ

I/O

CLK

I/O

DDQ

I/O

DDQ

BWE

I/O

(1)

DD / NC

LBO

(3)

(2)

(2,4)

DDQ

NC/TDO

DDQ

NC/TMS

NC/TDI

NC/TCK

NC/TRST

5301 drw 04

Top View

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. T7 can be left unconnected and the device will always remain in active mode.

4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6.462

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 128K x 36, 165 fBGA

NC⁽⁴⁾

BWE

ADSC

ADV

ADSP

CLK

NC⁽⁴⁾

I/OP2

I/O14

I/O12

I/O10

BW4

BW1

I/OP3

I/O17

I/O19

I/O21

I/O23

DDQ

I/O16

I/O18

I/O20

I/O22

I/O15

I/O13

I/O11

I/O

I/O8

(3)

DD⁽¹⁾

I/O25

I/O27

I/O29

I/O31

I/OP4

I/O24

I/O26

I/O28

I/O30

DDQ

I/O

I/O6

I/O4

I/O2

I/O0

I/O

NC/TRST^{(2, 5)}

NC/TDI⁽²⁾

NC⁽⁴⁾

I/OP1

NC⁽⁴⁾

NC/TDO⁽²⁾

NC/TCK⁽²⁾

NC/TMS⁽²⁾

LBO

5301 tbl 17

NOTES:

1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. H11 can be left unconnected and the device will always remain in active mode.

4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.

5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6.42

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

DD = Max., VIN = 0V to VDD

µA

ZZ, LBO and JTAG Input Leakage Current⁽¹⁾

Output Leakage Current

___

|I^LZZ

DD = Max., VIN = 0V to VDD

µA

|I^LO

OUT = 0V to VDDQ, Device Deselected

Output Low Voltage

IOL = +8mA, VDD = Min.

0.4

___

Output High Voltage

IOH = -8mA, VDD = Min.

2.4

5301 tbl 08

NOTE:

1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.

DC Electrical Characteristics Over the Operating

TemperatureandSupplyVoltageRange⁽¹⁾

200MHz

Com'l

360

183MHz

Com'l

166 MHz

Com'l

Symbol

Parameter

Test Conditions

Device Selected, Outputs Open,

Ind

Unit

Operating Power Supply

Current

DD = Max.,

340

350

320

330

IDD

(2)

DDQ = Max., VIN > VIH or < VIL, f = fMAX

SB1

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

130

120

DDQ = Max., VIN > VHD or < VLD, f = 0^(2,3)

ISB2

Clock Running Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

120

110

(2,3)

DDQ = Max., VIN > VHD or < VLD, f = fMAX

ZZ > VHD, DD = Max.

Full Sleep Mode Supply

Current

5301 tbl 09

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

AC Test Conditions

AC Test Load

DDQ/2

(VDDQ = 3.3V)

50Ω

Input Pulse Levels

0 to 3V

2ns

I/O

Z0 = 50Ω

Input Rise/Fall Times

5301 drw 06

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

1.5V

Figure 1. AC Test Load

1.5V

See Figure 1

5301 tbl 10

∆tCD

(Typical, ns)

20 30 50

80 100

Capacitance (pF)

200

5301 drw 07

Figure 2. Lumped Capacitive Load, Typical Derating

6.482

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

SynchronousTruthTable^(1,3)

Operation

Address

Used

CS0

CLK

I/O

CS1

ADSP ADSC ADV

BWE

BWx

(2)

Deselected Cycle, Power Down

Read Cycle, Begin Burst

None

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

None

External

Read Cycle, Begin Burst

Write Cycle, Begin Burst

DIN

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

Current

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

5301tbl 11

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

6.42

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

SynchronousWriteFunctionTruthTable⁽¹⁾

Operation

BWE

BW2

BW3

BW4

Read

Write all Bytes

Write Byte 1⁽³⁾

Write Byte 2⁽³⁾

Write Byte 3⁽³⁾

Write Byte 4⁽³⁾

5301 tbl 12

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

3. Multiple bytes may be selected during the same cycle.

AsynchronousTruthTable⁽¹⁾

Operation⁽²⁾

I/O Status

Power

Read

Data Out

High-Z

Active

Standby

Sleep

Write

High-Z – Data In

High-Z

Deselected

Sleep Mode

High-Z

5301 tbl 13

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

5301 tbl 14

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

5301 tbl 15

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

6.1402

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

200MHz⁽⁵⁾

183MHz

166MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC

Clock Cycle Time

—

5.5

2.2

—

(1)

Clock High Pulse Width

Clock Low Pulse Width

2.4

(1)

Output Parameters

Clock High to Valid Data

Clock High to Data Change

Clock High to Output Active

—

1.0

3.1

—

1.0

3.3

—

1.0

3.5

—

tCDC

(2)

CLZ

—

(2)

Clock High to Data High-Z

1.5

—

3.1

—

1.5

—

3.3

—

1.5

—

3.5

—

CHZ

tOE

Output Enable Access Time

(2)

Output Enable Low to Output Active

Output Enable High to Output High-Z

tOLZ

—

3.1

—

3.3

—

3.5

OHZ

Set Up Times

SAV

Address Setup Time

1.2

—

1.5

—

1.5

—

Address Status Setup Time

Data In Setup Time

Write Setup Time

Address Advance Setup Time

Chip Enable/Select Setup Time

Hold Times

HAV

Address Hold Time

0.4

—

0.5

—

0.5

—

Address Status Hold Time

Data In Hold Time

Write Hold Time

Address Advance Hold Time

Chip Enable/Select Hold Time

Sleep Mode and Configuration Parameters

ZZPW

ZZ Pulse Width

100

—

100

—

100

—

(3)

ZZ Recovery Time

Configuration Set-up Time

tZZR

(4)

tCFG

5301tbl 16

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

5. Commercial temperature range only.

6.42

CYC

CLK

tCL

ADSP

ADSC

(1)

ADDRESS

tSW

tHW

GW,BWE,BWx

CE, CS

(Note 3)

SAV

HAV

ADV

ADV HIGH suspends

burst

tOE

tCD

tOHZ

CDC

(Burst wraps around

to its initial state)

OLZ

tCHZ

CLZ

O3(Ay)

O2(Ay)

O4(Ay)

O1(Ay)

O1(Ax)

O1(Ay)

DATAOUT

Output

Disabled

Pipelined

Read

Burst Pipelined Read

5301 drw 08

NOTES:

1. O1(Ax)representsthefirstoutputfromtheexternaladdressAx. O1(Ay)representsthefirstoutputfromtheexternaladdressAy;O2(Ay)representsthenextoutputdataintheburstsequence

of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

tCYC

CLK

tSS

tHS

tCH

(2)

ADSP

tSA

tHA

ADDRESS

ADV

tSD

tHD

tOE

OLZ

tCD

I1(Ay)

DATAIN

tOHZ

tCDC

tCLZ

DATAOUT

O1(Ax)

O1(Az)

O2(Az)

O3(Az)

tCD

Pipelined

Write

Pipelined Burst Read

Single Read

5301 drw 09

NOTES:

1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. O1(Ax)representsthefirstoutputfromtheexternaladdressAx. I1(Ay)representsthefirstinputfromtheexternaladdressAy;O1(Az)representsthefirstoutputfromtheexternaladdressAz;O2(Az)represents

the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

CYC

CLK

ADSP

tCL

tCH

ADSC

tSA

tHA

ADDRESS

tHW

GW is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge

^SCtHC

CE, CS

(Note 3)

tHAV

tSAV

ADV

(ADV HIGH suspends burst)

DATAIN

tHD

I1(Ay)

I2(Az)

I3(Az)

I1(Ax)

I4(Ay)

I1(Az)

I2(Ay)

I3(Ay)

tOHZ

DATAOUT

O3(Aw)

O4(Aw)

Burst Write

Burst Read

Burst Write

Single

Write

5301 drw 10

NOTES:

1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external

address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined

by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

tCYC

CLK

ADSP

tCH

tCL

ADSC

ADDRESS

BWE is ignored when ADSP initiates a cycle and is sampled on next clock rising edge

BWE

BWx

tHW

BWx is ignored when ADSP initiates a cycle and is sampled on next clock rising edge

^SCtHC

CE, CS

(Note 3)

tSAV

ADV

(ADV suspends burst)

DATAIN

tHD

I1(Ay)

I1(Ax)

I2(Ay)

I3(Ay)

I2(Az)

I3(Az)

I4(Ay)

I2(Ay)

I1(Az)

tOHZ

DATAOUT

O3(Aw)

O4(Aw)

Burst

Read

Extended

Burst Write

Single

Write

Burst Write

5301 drw 11

NOTES:

1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.

address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined

by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

tCYC

CLK

tCH

tCL

tSS

tHS

ADSP

ADSC

tSA

tHA

ADDRESS

tSC

tHC

CE, CS

(Note 4)

ADV

tOE

DATAOUT

tOLZ

O1(Ax)

tZZR

tZZPW

Snooze Mode

Single Read

5301 drw 12

NOTES:

1. Device must power up in deselected Mode

2. LBO is Don't Care for this cycle.

3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.

4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

ADDRESS

GW, BWE, BWx

CE, CS

(Av)

(Aw)

(Ax)

(Ay)

DATA^OUT

5301 drw 14

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles, ADSP andADSCfunction identically and are therefore interchangable.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

ADSC

ADDRESS

CE, CS

CS0

(Av)

(Aw)

(Ax)

(Ay)

(Az)

DATAIN

5301 drw 15

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

6.42

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

JCYC

tJR

tJF

tJCL

tJCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

tJDC

tJS

tJH

Device Outputs⁽²⁾/

TDO

tJRSR

tJCD

(

TRST

M5301 drw 01

tJRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

JTAG AC Electrical

Characteristics^(1,2,3,4)

Symbol

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

Max.

Units

ScanRegisterSizes

____

JCYC

JCH

JCL

JRST

JRSR

JCD

JDC

Bit Size

____

Instruction (IR)

Bypass (BYR)

5⁽¹⁾

____

JTAG Identification (JIDR)

Boundary Scan (BSR)

5⁽¹⁾

____

Note (1)

____

I5301 tbl 03

____

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

____

JTAG Hold

I5301 tbl 01

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.1482

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions (SA Version only)

Instruction Field

Value

Description

Revision Number (31:28)

0x2

Reserved for version number.

IDT Device ID (27:12)

0x23C, 0x23E

Defines IDT part number 71V35761SA.

IDT JEDEC ID (11:1)

0x33

Allows unique identification of device vendor as IDT.

Indicates the presence of an ID register.

ID Register Indicator Bit (Bit 0)

I5301 tbl 02

AvailableJTAGInstructions

Instruction

Description

OPCODE

Forces contents of the boundary scan cells onto the device outputs⁽¹⁾.

Places the boundary scan register (BSR) between TDI and TDO.

EXTEST

0000

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs⁽²⁾and outputs⁽¹⁾to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the bo undary scan cells via the TDI.

SAMPLE/PRELOAD

0001

Loads the JTAG ID register (JIDR) with the vendor ID code and places

the register between TDI and TDO.

DEVICE_ID

HIGHZ

0010

0011

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

RESERVED

0100

0101

0110

0111

Several combinations are reserved. Do not use codes other than those

identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,

VALIDATE and BYPASS instructions.

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

CLAMP

1000

RESERVED

1001

1010

1011

1100

Same as above.

Automatically loaded into the instruction register whenever the TAP

controller passes through the CAPTURE-IR state. The lower two bits '01'

are mandated by the IEEE std. 1149.1 specification.

VALIDATE

1101

RESERVED

BYPASS

Same as above.

1110

1111

The BYPASS instruction is used to truncate the boundary scan register

as a single bit in length.

I5301 tbl 04

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

6.42

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

OrderingInformation

Package Information

100-PinThinQuadPlasticFlatpack(TQFP)

119 Ball Grid Array (BGA)

165FinePitchBallGridArray(fBGA)

InformationavailableontheIDTwebsite

6.2402

IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DatasheetDocumentHistory

12/31/99

04/04/00

Creatednewdatasheetfrom71v3576and71v3578datasheet.

Addedindustrialtemperaturerangeofferingfrom166MHzand183MHz

Added 100 pin TQFP package Diagram Outline

Pg. 1, 4, 8, 11, 19

Pg. 18

Pg. 4

Add BGA capacitance table; Add industrial temperature to table; Insert note to Absolute

Max Rating and Recommended Operating Temperature tables

Add new package diagram outline, 13 x 15mm 165fBGA

CorrectBG119PackageDiagramOutline

06/01/00

07/15/00

Pg. 20

Pg. 7

AddnotereferencetoBG119pinout

Pg. 8

Add DNU reference note to BQ165 pinout

Pg. 20

UpdateBG119PackageDiagramOutlineDimensions

RemovePreliminarystatus

10/25/00

Pg. 8

Pg.4

Add reference note to N5 on the BQ165 pinout, reserved for JTAG TRST

Updated165BGAtableinformationfromTBDto7

04/22/03

06/30/03

Pg. 1,2,3,5-9

Pg. 5-8

UpdateddatasheetwithJTAGinformation

Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))

requiring NC or connection to Vss.

Pg. 19,20

Pg. 21-23

Pg. 24

AddedtwopagesofJTAGSpecification,ACElectrical,DefinitionsandInstructions

Removedoldpackageinformationfromthedatasheet

UpdatedorderinginformationwithJTAGandYsteppinginformation. Addedinformation

regarding packages available IDT website.

03/02/09

06/01/10

Pg. 21

Pg. 1-21

Removed "IDT" from orderable part number

Added"Restrictedhazardoussubstancedevice"totheorderinginformation.

Removed IDT71V35781S/SA from datasheet.

08/01/14 Pg. 1-3

Pg. 20

Moved the FBD, the pin description and pin definition tables to pages 1 - 3 respectively to

align the datasheet reading flow to that of our other established datasheets

In the Ordering Information, Tape & Reel added & RoHS designation changed to Green

Removed "Y" stepping from the datasheet part number. Changed DS Device to

IDT71V35761S/SA

11/06/14

Pg. 1

Pg. 2

Pg. 3

Pg. 21

Pg. 22

InFeatures:Addedtext:"Greenpartsavailable,seeorderinginformation"

InDescription:Clarifiedtextinlastparagraph

Removeddevice71V35781inthePinDefinitionsTable

RemovedsteppingfromOrderingInformation

Updatedsramhelpcontactinformation

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

sramhelp@idt.com

408-284-4532

800-345-7015or

408-284-8200

fax:408-284-2775

www.idt.com

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

6.42

IDT71V35761SA183BQG [IDT]

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