IDT71V3577YS85PF [IDT]
暂无描述;型号: | IDT71V3577YS85PF |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | 暂无描述 计数器 静态存储器 |
文件: | 总22页 (文件大小:522K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT71V3577S
IDT71V3579S
IDT71V3577SA
IDT71V3579SA
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Description
Features
◆
The IDT71V3577/79 are high-speed SRAMs organized as
128Kx36/256Kx18.TheIDT71V3577/79SRAMs containwrite,data,
address andcontrolregisters.Therearenoregisters inthedataoutput
path(flow-througharchitecture).InternallogicallowstheSRAMtogen-
erateaself-timedwritebaseduponadecisionwhichcanbeleftuntilthe
endofthe write cycle.
128K x 36, 256K x 18 memory configurations
◆
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
CommercialandIndustrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO input selects interleaved or linear burst mode
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V3577/79canprovidefourcyclesofdata
forasingleaddress presentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe
next three rising clock edges. The order of these three addresses are
definedbytheinternalburstcounterandtheLBO inputpin.
◆
◆
◆
◆
◆
◆
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball
grid array
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS0, CS1
OE
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
GW
BWE
(1)
BW1, BW2, BW3, BW4
CLK
ADV
ADSC
ADSP
LBO
Clock
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
Test Clock
Test Data Output
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
JTAG Reset (Optional)
Sleep Mode
TRST
ZZ
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Ground
Supply
Supply
VSS
N/A
NOTE:
5280 tbl 01
1. BW3 and BW4 are not applicable for the IDT71V3579.
FEBRUARY 2005
1
©2005IntegratedDeviceTechnology,Inc.
DSC-5280/08
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
ADSC
ADSP
ADV
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,
controlling burst access after the initial address is loaded. When the input is HIGHthe burst counter is not
incremented; that is, there is no address advance.
Byte Write Enable
I
I
LOW
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
BWE
Individual Byte
Write Enables
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte
write causes all outputs to be disabled.
BW1-BW4
Chip Enable
Clock
I
I
I
I
I
LOW
N/A
Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V3577/79. CE also gates ADSP.
This is the clock input. All timing references for the device are made with respect to this input.
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
CE
CLK
CS0
CS1
GW
Chip Select 0
Chip Select 1
HIGH
LOW
LOW
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of
CLK. The data outputpath is flow-through (no output register).
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
OE
TMS
TDI
Test ModeSelect
Test Data Input
I
I
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Test DataOutput
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
LOW
TRST
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3577/79 to
HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
down.
ZZ
Sleep Mode
VDD
VDDQ
VSS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
NC
No Connect
NC pins are not electrically connected to the device.
5280 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
128K x 36/
CLK
2
Burst
17/18
256K x 18-
Binary
Logic
Counter
ADSC
A0*
A1*
BIT
MEMORY
ARRAY
Q0
Q1
CLR
ADSP
2
CLK EN
A0,A1
A2 - A17
ADDRESS
REGISTER
A0 - A16/17
GW
36/18
36/18
17/18
BWE
Byte 1
Write Register
Byte 1
Write Driver
BW1
BW2
9
9
Byte 2
Write Register
Byte 2
Write Driver
Byte 3
Write Register
Byte 3
Write Driver
BW3
BW4
9
9
Byte 4
Write Register
Byte 4
Write Driver
CE
Q
D
CS0
CS1
Enable
DATA INPUT
REGISTER
Register
CLK EN
ZZ
Powerdown
OE
OUTPUT
BUFFER
OE
,
36/18
I/O0 - I/O31
I/OP1 - I/OP4
5280 drw 01
TMS
TDI
TCK
TRST
JTAG
(SA Version)
TDO
(Optional)
6.42
3
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureSupplyVoltage
Commercial &
Industrial Values
Symbol
Rating
Unit
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
VSS
0V
0V
VDD
VDDQ
(2)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
(3,6)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
5280 tbl 04
NOTES:
1. TA is the "instant on" case temperature.
(4,6)
VTERM
Terminal Voltage with
Respect to GND
(5,6)
VTERM
Terminal Voltage with
Respect to GND
V
RecommendedDCOperating
Conditions
Commercial
oC
oC
oC
oC
W
Symbol
Parameter
Min. Typ.
3.135 3.3
3.135 3.3
Max.
Unit
V
Operating Temperature
(7)
TA
VDD
Core Supply Voltage
3.465
3.465
Industrial
-40 to +85
Operating Temperature
VDDQ I/O Supply Voltage
V
TBIAS
Temperature
Under Bias
-55 to +125
VSS
VIH
Supply Voltage
0
0
0
V
____
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
VDD +0.3
VDDQ +0.3(1 )
0.8
V
Storage
-55 to +125
TSTG
____
____
VIH
2.0
V
Temperature
VIL
-0.3(2 )
V
PT
Power Dissipation
DC Output Current
2.0
50
5280 tbl 06
NOTES:
IOUT
mA
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
5280 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
100PinTQFPCapacitance
(TA = +25° C, f = 1.0mhz)
119BGACapacitance
(TA = +25° C, f = 1.0mhz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
5
7
pF
7
7
pF
CI/O
pF
CI/O
pF
5280 tbl 07
5280 tbl 07a
165fBGACapacitance
(TA = +25° C, f = 1.0mhz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
7
7
pF
CI/O
pF
5280 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.442
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
I/OP3
2
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
3
4
5
76
75
74
73
72
71
70
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
69
68
67
66
65
64
I/O22
I/O23
(1)
VSS
VDD
NC
VSS
VDD
ZZ (2)
I/O7
I/O6
VDDQ
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
VSS
I/O5
,
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5280 drw 02a
100TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(2)
I/O3
I/O2
VDDQ
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
2
79
3
78
77
4
5
76
75
74
73
6
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
69
68
67
66
I/O10
I/O11
(1)
VSS
VDD
NC
VSS
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
,
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5280 drw 02b
100TQFP
TopView
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.462
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
3
2
9
1
CS
NC
NC
CS
NC
NC
0
7
A
DD
V
12
15
A
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
CE
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
DDQ
19
I/O
12
I/O
DDQ
V
V
V
V
V
V
OE
20
I/O
21
I/O
3
2
BW
11
I/O
10
I/O
G
H
J
BW
ADV
GW
22
I/O
23
I/O
SS
SS
9
I/O
8
I/O
V
V
DDQ
24
DD
DD
V
DD
V
DDQ
V
NC
NC
26
I/O
SS
SS
6
I/O
7
I/O
I/O
V
CLK
NC
V
K
L
25
I/O
27
I/O
4
1
BW
4
I/O
5
I/O
BW
DDQ
29
28
I/O
SS
SS
SS
SS
SS
SS
SS
3
I/O
DDQ
V
V
V
V
V
V
V
M
N
P
R
T
BWE
30
I/O
1
0
2
I/O
1
I/O
I/O
A
31
P4
I/O
0
I/O
P1
I/O
I/O
NC
A
5
A
DD
V
13
A
NC
LBO
(3)
10
11
A
14
NC
NC
A
A
NC
ZZ
(2)
(2)
(2)
(2)
(2,4)
NC/TDO
DDQ
V
DDQ
V
NC/TMS
NC/TDI
NC/TCK
NC/TRST
U
5280 drw 02c
Top View
Pin Configuration 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
A
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
ADSP
ADSC
3
2
9
CS1
NC
NC
CS0
NC
NC
NC
7
A
DD
V
13
A
17
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
CE
V
V
V
V
V
9
I/O
6
I/O
NC
DDQ
NC
5
I/O
DDQ
V
V
NC
OE
10
I/O
4
I/O
BW2
ADV
GW
NC
NC
G
H
J
11
I/O
SS
V
3
I/O
NC
NC
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
NC
NC
SS
12
I/O
SS
V
2
I/O
K
L
NC
CLK
NC
V
NC
SS
V
13
I/O
1
I/O
BW1
NC
NC
DDQ
14
SS
V
SS
V
DDQ
V
M
N
P
R
T
V
I/O
NC
BWE
15
I/O
SS
V
1
A
SS
V
0
I/O
NC
NC
P2
SS
V
0
A
SS
V
P1
I/O
NC
NC
NC
DDQ
I/O
NC
5
DD
V
SS
V
12
A
A
NC
LBO
ZZ(3)
10
A
15
A
14
A
11
A
NC
NC/TDO(2)
DDQ
V
NC/TMS(2) NC/TDI(2) NC/TCK(2)
NC/TRST(2,4)
U
V
5280 drw 02d
,
Top View
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
7
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
A8
11
(4)
A
B
C
D
E
F
NC
A7
NC
CE1
BW3
BW4
VSS
BW2
BW1
VSS
VSS
VSS
VSS
VSS
VSS
CS1
CLK
VSS
VSS
VSS
VSS
VSS
VSS
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
ADSC
OE
ADV
(4)
NC
A6
CS0
A9
NC
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
I/OP3
I/O17
I/O19
I/O21
I/O23
VSS(1)
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
NC
I/OP2
I/O14
I/O12
I/O10
I/O8
I/O16
I/O18
I/O20
I/O22
NC
VDD
VDD
VDD
VDD
VDD
I/O15
I/O13
I/O11
I/O9
NC
G
H
J
(3)
ZZ
I/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
I/O
6
K
L
M
N
P
I/O27
I/O29
I/O31
I/OP4
NC
I/O26
I/O28
I/O30
NC
VDDQ
VDDQ
VDDQ
VDDQ
A5
VDD
VDD
VDD
VSS
A2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VDD
VDD
VDD
VSS
A10
A11
VDDQ
VDDQ
VDDQ
VDDQ
A13
I/O5
I/O3
I/O1
NC
I/O4
I/O2
I/O0
(4)
TRST(2, 5)
NC
A1
A0
I/OP1
NC/
(4)
(2)
(2)
(4)
NC
NC/TDI
NC/TDO
A14
A15
NC
(4)
(2)
R
NC
A4
A3
NC/TMS(2)
NC/TCK
A12
A16
LBO
5280 tbl 17
Pin Configuration 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
ADSC
OE
9
10
A8
11
(4)
A
B
C
D
E
F
NC
NC
A7
NC
A10
CE1
BW2
NC
CS1
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
ADV
(4)
A6
CS0
A9
NC
BW1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
I/O8
I/O9
I/O10
I/O11
NC
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A2
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A11
NC
NC
NC
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
A15
A16
I/OP1
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
G
H
J
NC
VSS(1)
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
ZZ
(3)
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A14
NC
NC
NC
NC
NC
K
L
M
N
P
TRST(2, 5)
(4)
NC
NC/
(4)
(2)
(2)
(4)
NC
NC/TDI
A1
A0
NC/TDO
NC
(4)
(2)
R
NC
A4
A3
NC/TMS(2)
NC/TCK
A12
A13
A17
LBO
5280 tbl 17a
NOTES:
1. H1 does not have to be directly VSS as long as input voltage is < VIL
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.482
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
VDD = Max., VIN = 0V to VDD
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
5
µA
ZZ , LBO and JTAG Input Leakage Current(1)
Output Leakage Current
DD
IN
___
___
___
|ILI|
V
= Max., V = 0V to V
DD
30
5
µA
µA
V
|ILO|
VOL
VOH
VOUT = 0V to VDDQ, Device Deselected
IOL = +8mA, VDD = Min.
Output Low Voltage
0.4
___
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
V
5280 tbl 08
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ in will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature andSupplyVoltage Range(1)
7.5ns
8ns
8.5ns
Symbol
Parameter
Test Conditions
Com'l Only Com'l Ind
Com'l Ind
Unit
Operating Power Supply Current
Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
255
30
200
30
210
35
180
190
mA
IDD
(2 )
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
30
35
mA
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
90
85
95
80
90
(2,.3)
VDDQ = Max., VIN > VHD or < VLD, f = fMAX
IZZ
Full Sleep Mode Supply Current
ZZ > VHD, VDD = Max.
30
30
35
30
35
mA
5280 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
(VDDQ = 3.3V)
AC Test Load
V
DDQ/2
50Ω
Input Pulse Levels
0 to 3V
2ns
I/O
Z = 50Ω
0
Input Rise/Fall Times
,
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
5280 drw 03
1.5V
Figure 1. AC Test Load
6
5
4
3
See Figure 1
5280 tbl 10
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
,
5280 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,3)
CE
CS1
ADSP ADSC ADV
GW
BWE BWx OE(2)
Operation
Address
CS0
CLK
I/O
Used
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
DOUT
HI-Z
DOUT
DOUT
HI-Z
DIN
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Read Cycle, Begin Burst
L
L
L
H
L
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
Read Cycle, Begin Burst
L
L
L
L
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
Write Cycle, Begin Burst
L
L
L
L
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
X
X
X
X
L
Next
L
Next
L
X
L
X
L
DIN
Next
L
H
L
DIN
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
H
L
H
L
H
L
H
X
X
X
X
X
L
X
L
DIN
H
L
DIN
X
X
DIN
5280 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ - low for the table.
6.1402
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table (1, 2)
GW
H
H
L
BWE
H
L
BW1
BW2
X
BW3
X
BW4
X
Operation
Read
X
Read
H
H
H
H
Write all Bytes
Write all Bytes
X
L
X
X
X
X
H
H
H
H
H
L
L
L
L
(3)
Write Byte 1
L
L
H
H
H
(3)
Write Byte 2
L
H
L
H
H
(3)
Write Byte 3
L
H
H
L
H
(3)
Write Byte 4
L
H
H
H
L
5280 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V3579.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
5280 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table ( LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
5280 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table ( LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5280 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
7.5ns(5 )
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
Clock Parameter
____
____
____
____
____
____
tCY C
Clock Cycle Time
8.5
3
10
4
11.5
4.5
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
tCH
____
____
____
(1)
3
4
4.5
tCL
Output Parameters
____
____
____
tCD
Clock High to Valid Data
7.5
8
8.5
ns
ns
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
Output Enable Low to Output Active
2
0
2
0
2
0
(2)
____
____
____
ns
ns
ns
ns
ns
tCL Z
(2)
2
3.5
2
3.5
2
3.5
tCHZ
____
____
____
tOE
3.5
3.5
3.5
____
____
____
(2)
0
0
0
tOLZ
____
____
____
(2)
Output Enable High to Output High-Z
3.5
3.5
3.5
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSA
tSS
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
2
2
2
2
2
2
2
2
2
2
2
2
ns
ns
ns
ns
ns
ns
Address Status Setup Time
Data In Setup Time
tSD
tSW
tSAV
tSC
Write Setup Time
Address Advance Setup Time
Chip Enable/Select Setup Time
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
tHS
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Address Status Hold Time
Data In Hold Time
tHD
tHW
tHAV
tHC
Write Hold Time
Address Advance Hold Time
Chip Enable/Select Hold Time
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
____
____
____
tZZPW
ZZ Pulse Width
100
100
34
100
100
40
100
100
50
ns
ns
(3)
tZZR
ZZ Recovery Time
Configuration Set-up Time
tCFG(4)
ns
5280 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
6.1422
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Flow-Through Read Cycle (1,2)
,
6.42
13
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
,
6.1442
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 - GW Controlled (1,2,3)
,
6.42
15
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled (1,2,3)
,
6.1462
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
,
6.42
17
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
5280 drw 10
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE CS1
,
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
5280 drw 11
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.1482
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
tJCYC
tJR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
tJRSR
tJCD
3)
(
x
TRST
M5280 drw 01
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
tJCYC
tJCH
tJCL
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
Register Name
Instruction (IR)
Bit Size
____
____
ns
4
1
40
ns
Bypass (BYR)
(1 )
____
tJR
5
ns
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
(1 )
____
tJF
5
ns
Note (1)
____
____
tJRST
tJRSR
tJCD
tJDC
tJS
50
ns
I5280 tbl 03
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
20
ns
____
0
ns
____
____
25
25
ns
tJH
JTAG Hold
ns
I5280 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
19
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Revision Number (31:28)
Value
Description
0x2
0x22C, 0x22E
0x33
Reserved for version number.
IDT Device ID (27:12)
Defines IDT part number 71V3577SA and 71V3579SA, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
ID Register Indicator Bit (Bit 0)
1
I5280 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5280 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.2402
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
IDT XXX
X
S
XX
X
X
X
Power Speed
Package
Process/
Temperature
Range
Device
Type
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Restricted hazardous substance device
G
PF**
BG
BQ
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
75*
80
85
Access Time in Tenths of Nanoseconds
Standard Power
Standard Power with JTAG Interface
S
SA
First Generation or current stepping
Second Generation die step
Blank
Y
,
71V3577
71V3579
128K x 36 Flow-Through Burst Synchronous SRAM with 3.3V I/O
256K x 18 Flow-Through Burst Synchronous SRAM with 3.3V I/O
5280 drw 12
*Commercial temperature range only.
** JTAG (SA version) is not available with 100 pin TQFP package
PackageInformation
100-Pin Thin Quad Plastic Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Information available on the IDT website
6.42
21
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
7/23/99
9/17/99
Updatedtonewformat
RevisedI/Opindescription
Pg. 2
Pg. 3
Pg. 8
Revisedblockdiagramforflow-throughfunctionality
Revised ISB1 and IZZ for speeds 7.5 to 8.5ns
Pg. 18
Added119-leadBGApackagediagram
Pg. 20
AddedDatasheetDocumentHistory
12/31/99
04/03/00
Pp. 1, 4, 8, 11, 19
Pg. 18
AddedIndustrialTemperaturerangeofferings
Added100pinTQFPPackageDiagramOutline
Pg. 4
AddcapacitancetableforBGApackage;addIndustrialtemperaturetotable;Insertnoteto
AbsoluteMaxRatingsandRecommendedOperatingTemperaturetables
Addnewpackage offering, 13x15mm165fBGA
06/01/00
07/15/00
Pg. 20
Pg. 7
Correct119BGAPackageDiagramOutline
AddnotereferencetoBG119pinout
Pg. 8
AddDNUreference note toBQ165pinout
Pg. 20
UpdateBG119PackageDiagramOutlineDimensions
RemovePreliminarystatus
10/25/00
Pg.8
Pg.4
Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
Updated165BGAtableinformationfromTBDto7
04/22/03
06/30/03
Pg. 1,2,3,5-9
Pg. 5-8
UpdateddatasheetwithJTAGinformation
Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))
requiringNCorconnectiontoVss.
Pg. 19,20
Pg. 21-23
Pg. 24
AddedtwopagesofJTAGSpecification,ACElectrical,DefinitionsandInstructions
Removedoldpackageinformationfromthedatasheet
UpdatedorderinginformationwithJTAGandYsteppinginformation. Addedinformation
regardingpackages available IDTwebsite.
02/18/05
Pg. 21
Addedd"restrictedhazardoussubstancedevice"toorderinginformation.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
sramhelp@idt.com
800-544-7726, x4033
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.2422
相关型号:
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128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect
IDT
IDT71V3577YS85PFGI
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect
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