IDT71V3578150BG [IDT]
Cache SRAM, 256KX18, 3.8ns, CMOS, PBGA119, BGA-119;
| 型号： | IDT71V3578150BG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Cache SRAM, 256KX18, 3.8ns, CMOS, PBGA119, BGA-119 静态存储器 |
| 文件： | 总17页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K X 36, 256K X 18, 3.3V
SYNCHRONOUS SRAMS WITH
2.5V I/O OPTION, PIPELINED OUTPUTS,
BURST COUNTER,
PRELIMINARY
IDT71V2576
IDT71V2578
IDT71V3576
IDT71V3578
SINGLE CYCLE DESELECT
DESCRIPTION:
FEATURES:
The IDT71Vx576/578 are high-speed SRAMs organized as 128K x 36/
256K x 18. The IDT71Vx576/578 SRAMs contain write, data, address and
controlregisters. InternallogicallowstheSRAMtogenerateaself-timedwrite
basedupona decisionwhichcanbe leftuntilthe endofthe write cycle.
Theburstmodefeatureoffersthehighestlevelofperformancetothesystem
designer,astheIDT71Vx576/578canprovidefourcyclesofdataforasingle
addresspresentedtotheSRAM. Aninternalburstaddresscounteracceptsthe
firstcycleaddressfromtheprocessor,initiatingtheaccesssequence.Thefirst
cycleofoutputdatawillbepipelinedforonecyclebeforeitisavailableonthe
next rising clock edge. If burst mode operation is selected (ADV=LOW),
the subsequent three cycles of output data will be available to the user on
the next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
• 128K x 36, 256K x 18 memory configurations
• Supports high system speed:
– 200MHz 3.1ns clock access time
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
• LBO input selects interleaved or linear burst mode
• Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
• 3.3V core power supply
• Power down controlled by ZZ input
• 2.5V or 3.3V I/O option
TheIDT71Vx576/578SRAMsutilizeIDT’slatesthigh-performanceCMOS
processandarepackagedinaJEDECstandard14mmx20mm100-leadthin
plastic quad flatpack (TQFP) as well as a 119-lead ball grid array (BGA).
• Packaged in a JEDEC Standard 100-lead plastic thin quad flatpack
(TQFP) and 119-lead ball grid array (BGA)
PIN DESCRIPTION SUMMARY
A
0
-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
OE
GW
0, CS
1
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
BWE
BW , BW
(1)
1
2
, BW
3
, BW
4
CLK
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ADV
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
N/A
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
N/A
4876 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71Vx578.
APRIL 1999
1
1998 Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
PIN DEFINITIONS(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
ADSC
ADSP
ADV
used to load the address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
1
-BW . If BWE is LOW at the
4
BWE
Individual Byte
Write Enables
I
I
I
LOW
LOW
N/A
Synchronous byte write enables. BW
1
controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
BW
1
-BW
4
Any active byte write causes all outputs to be disabled.
Chip Enable
Synchronous chip enable. CE is used with CS
CE also gates ADSP.
0
and CS1 to enable the IDT71Vx576/578.
CE
CLK
Clock
This is the clock input. All timing references for the device are made with respect to this
input.
CS
0
Chip Select 0
Chip Select 1
I
I
I
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
0
is used with CE and CS
1
to enable the chip.
1
is used with CE and CS
0 to enable the chip.
CS
1
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
GW
I/O
I/OP1-I/OP4
0
-I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
OE
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
I
N/A
N/A
3.3V core power supply.
V
3.3V or 2.5V I/O Supply.
V
N/A
Ground.
NC
ZZ
No Connect
Sleep Mode
N/A
NC pins are not electrically connected to the device.
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71Vx576/78 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
4876 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
1998 Integrated Device Technology, Inc.
DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
INTERNAL
ADDRESS
CE#
128K x 36/
CLK
2
Burst
Logic
17/18
Binary
Counter
256K x 18-
ADSC
A0*
BIT
MEMORY
ARRAY
Q0
CLR#
A1*
Q1
ADSP
2
CE#
A0,A1
A2ÐA17
ADDRESS
REGISTER
A0ÐA16/17
GW
36/18
36/18
17/18
Byte 1
Write Register
BWE
Byte 1
Write Driver
BW1
9
9
Byte 2
Write Register
Byte 2
Write Driver
2
BW
Byte 3
Write Register
Byte 3
Write Driver
BW3
9
9
Byte 4
Write Register
Byte 4
Write Driver
4
BW
OUTPUT
REGISTER
CE
CS0
CS1
Q
D
Enable
Register
DATA
INPUT
REGISTER
CE#
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
36/18
I/O0 — I/O31
I/OP1 — I/OP4
4876 drw 01
3
1998 Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY
VOLTAGE
Symbol
Rating
Commercial
Unit
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Grade
Temperature
0°C to +70°C
0°C to +70°C
V
SS
V
DD
VDDQ
(3,6)
(4,6)
(5,6)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
Commercial
Commercial
0V
0V
3.3V±5%
3.3V±5%
2.5V±5%
VDD
VTERM
Terminal Voltage with
Respect to GND
4876 tbl 04
VTERM
Terminal Voltage with
Respect to GND
V
RECOMMENDED DC OPERATING
CONDITIONS WITH VDDQ AT 2.5V
oC
oC
oC
W
TA
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
2.375
0
Typ.
Max.
3.465
2.625
0
Unit
V
Operating Temperature
V
DD
DDQ
SS
IH
3.3
Temperature
Under Bias
-55 to +125
TBIAS
V
2.5
V
V
0
V
Storage
-55 to +125
TSTG
Temperature
____
V
V
1.7
Input High Voltage - Inputs
Input High Voltage -I/O
VDD +0.3
P
T
Power Dissipation
DC Output Current
1.25
50
____
____
V
V
IH
1.7
V
DDQ
IOUT
mA
+0.3(1)
4876 tbl 03
VIL
Input Low Voltage
-0.3(2)
0.7
V
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4876 tbl 05
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
RECOMMENDED DC OPERATING
6. This is a steady-state DC parameter that applies after the power supplies have ramped up.
Power supply sequencing is not necessary; however, the voltage on any input or I/O pin
cannot exceed VDDQ during power supply ramp up.
CONDITIONS WITH VDDQ AT 3.3V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
3.135
0
Typ.
Max.
3.465
3.465
0
Unit
V
V
DD
DDQ
SS
IH
3.3
V
3.3
V
V
0
V
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
____
V
V
2.0
Input High Voltage - Inputs
Input High Voltage -I/O
VDD +0.3
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
____
____
Symbol
V
V
IH
2.0
V
DDQ
+0.3(1)
CIN
V
5
7
pF
VIL
Input Low Voltage
-0.3(2)
0.8
V
CI/O
V
pF
4876 tbl 06
NOTES:
4876 tbl 07
NOTE:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
1. This parameter is guaranteed by device characterization, but not production tested.
4
1998 Integrated Device Technology, Inc.
DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
PIN CONFIGURATION 128K x 36 TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
I/OP2
I/O15
2
79
3
78
77
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
4
5
76
75
74
73
6
7
8
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDQ
I/O22
I/O23
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
(1)
VDD
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
VDDQ
I/O1
I/O0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4876 drw 02
TOP VIEW
NOTES:
1. Pins 14 does not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. Pins 38 and 39 can be either NC or connected to VSS.
5
1998 Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION 256K x 18 TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
NC
NC
A10
NC
2
79
3
NC
78
77
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
4
VDDQ
VSS
NC
5
76
75
74
73
6
7
NC
8
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
70
69
68
67
66
(1)
VDD
VSS
NC
VDD
65
64
63
62
NC
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
VDD
ZZ
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
61
60
59
58
57
56
55
NC
VSS
VDDQ
NC
NC
NC
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4876 drw 03
TOP VIEW
NOTES:
1. Pins 14 does not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. Pins 38 and 39 can be either NC or connected to VSS.
6
1998 Integrated Device Technology, Inc.
DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
PIN CONFIGURATION 128K x 36 BGA(1,2)
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
0
3
2
9
A
NC
NC
CS
NC
NC
1
CS
7
DD
12
15
A
A
V
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
CE
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
DDQ
19
I/O
12
I/O
DDQ
V
V
V
V
V
V
OE
20
I/O
21
I/O
11
I/O
10
I/O
G
H
J
2
BW
BW
3
ADV
GW
22
I/O
23
I/O
SS
SS
9
I/O
8
I/O
V
V
DDQ
24
DD
DD
DD
V
DDQ
V
NC
V
NC
26
I/O
SS
4
SS
6
I/O
7
I/O
K
L
I/O
V
CLK
NC
V
25
I/O
27
I/O
4
I/O
5
I/O
1
BW
BW
DDQ
29
28
I/O
SS
SS
SS
SS
SS
SS
3
I/O
DDQ
V
V
V
V
V
V
M
N
P
R
T
BWE
30
I/O
1
0
2
I/O
1
I/O
I/O
A
A
31
I/O
P4
I/O
0
I/O
P1
I/O
V
NC
DD
14
5
DD
13
NC
NC
A
V
A
LBO
10
11
NC
NC
A
A
A
NC
NC
ZZ
DDQ
DDQ
V
V
NC
NC
NC
U
4876 drw 04
TOP VIEW
PIN CONFIGURATION 256K x 18 BGA(1,2)
1
2
3
4
5
6
7
DDQ
6
4
8
9
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
ADSP
ADSC
3
2
NC
NC
CS0
NC
NC
NC
1
CS
7
A
DD
13
17
A
V
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
V
V
V
V
V
9
I/O
6
I/O
NC
NC
CE
OE
DDQ
5
I/O
DDQ
V
V
NC
10
I/O
4
I/O
G
H
J
NC
NC
2
BW
ADV
GW
11
I/O
SS
SS
3
I/O
NC
V
NC
DDQ
DD
DD
DD
DDQ
V
V
V
NC
V
NC
V
12
SS
SS
2
K
L
NC
I/O
V
CLK
NC
V
NC
I/O
13
I/O
SS
1
I/O
NC
V
V
V
V
NC
1
BW
DDQ
14
I/O
SS
SS
SS
SS
DDQ
V
M
N
P
R
T
V
V
V
V
NC
BWE
15
I/O
1
0
SS
SS
0
I/O
NC
A
A
NC
P2
P1
I/O
NC
I/O
NC
5
DD
12
11
NC
NC
A
V
V
DD
A
A
NC
ZZ
LBO
10
15
14
A
A
NC
NC
A
DDQ
DDQ
V
U
V
NC
NC
NC
NC
4876 drw 05
TOP VIEW
NOTES:
1. R5 does not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. L4 and U4 can be either NC or connected to VSS.
7
1998 Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1)
___
___
___
ZZ and LBO Input Leakage Current
|ILZZ
|
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VDDQ, Device Deselected
OL = +8mA, VDD = Min.
OH = -8mA, VDD = Min.
OL = +6mA, VDD = Min.
OH = -6mA, VDD = Min.
30
5
µA
µA
V
|ILO|
Output Leakage Current
V
V
OL(3.3V) Output Low Voltage
OH(3.3V) Output High Voltage
OL(2.5V) Output Low Voltage
OH(2.5V) Output High Voltage
NOTE:
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
4876 tbl 08
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
Parameter
Test Conditions
200MHz
183MHz
166MHz
150MHz
295
133MHz
250
Unit
mA
mA
mA
Operating Power Supply Current
IDD
Device Selected, Outputs Open,
DD = Max., VIN > VIH or < VIL, f = fMAX
360
340
320
(2)
V
20
CMOS Standby Power Supply Current Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD, f = 0(2,3)
20
20
20
20
20
V
130
Clock Running Power Supply Current
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
130
120
110
100
90
V
,
(2.3)
f = fMAX
20
Full Sleep Mode Supply Current
ZZ> VHD,
VDD = Max.
20
20
20
20
20
mA
NOTES:
1. All values are maximum guaranteed values.
4876 tbl 09
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC TEST CONDITIONS
AC TEST LOADS
(VDDQ = 3.3V/2.5V)
V
DDQ/2
Input Pulse Levels
0 to 3V / 0 to VDDQ
2ns
50Ω
Input Rise/Fall Times
I/O
Z0 = 50Ω
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V / (VDDQ/2)
1.5V / (VDDQ/2)
See Figure 1
4876 drw 06
Figure 1. AC Test Load
6
5
4
3
4876 tbl 10
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
4876 drw 07
Figure 2. Lumped Capacitive Load, Typical Derating
8
1998 Integrated Device Technology, Inc.
DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
SYNCHRONOUSTRUTHTABLE(1,3)
CE
CS1
ADSP ADSC ADV
GW
BWE
BWx
OE
(2)
Operation
Address
Used
CS
0
CLK
I/O
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cycle, Begin Burst
L
L
L
H
L
HI-Z
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cycle, Begin Burst
L
L
L
L
DOUT
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
HI-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
OUT
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
HI-Z
Next
L
D
IN
IN
IN
IN
OUT
Next
L
X
L
X
L
D
Next
L
H
L
D
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
X
X
X
X
HI-Z
D
IN
IN
IN
IN
4876 tbl 11
X
L
X
L
D
H
L
D
X
X
D
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
9
1998 Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
SYNCHRONOUS WRITE FUNCTION TRUTH TABLE(1, 2)
GW
H
H
L
BWE
H
L
BW
1
BW
2
BW
3
BW4
Operation
Read
X
H
X
L
X
H
X
L
X
H
X
L
X
H
X
L
Read
Write all Bytes
Write all Bytes
Write Byte 1(3)
Write Byte 2(3)
Write Byte 3(3)
Write Byte 4(3)
X
L
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
H
H
L
H
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
4876 tbl 12
2. BW3 and BW4 are not applicable for the IDT71Vx579.
3. Multiple bytes may be selected during the same cycle.
ASYNCHRONOUS TRUTH TABLE(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
4876 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
INTERLEAVED BURST SEQUENCE TABLE (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
A1 A0
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
0
0
1
1
Fourth Address(1)
1
0
0
4876 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
LINEAR BURST SEQUENCE TABLE (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
1
Second Address
Third Address
1
1
0
1
1
0
0
0
1
1
0
0
0
1
Fourth Address(1)
1
0
0
0
1
1
0
NOTE:
4876 tbl 15
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
10
1998 Integrated Device Technology, Inc.
DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
AC ELECTRICAL CHARACTERISTICS
(VDD = 3.3V ±5%, TA = 0 to 70°C)
200MHz
183MHz
166MHz
150MHz
133MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
____
____
____
____
____
____
____
____
____
____
t
CYC
Clock Cycle Time
5
2
2
5.5
2.2
2.2
6
6.7
2.6
2.6
7.5
3
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
2.4
2.4
tCH
____
____
____
____
____
(1)
3
tCL
Output Parameters
Clock High to Valid Data
____
____
____
____
____
tCD
3.1
3.3
3.5
3.8
4.2
ns
ns
ns
____
____
____
____
____
tCDC
Clock High to Data Change
1.5
0
1.5
0
1.5
0
1.5
0
1.5
0
____
____
____
____
____
(2)
CLZ
Clock High to Output Active
Clock High to Data High-Z
t
(2)
1.5
3.1
1.5
3.3
1.5
3.5
1.5
3.8
1.5
4.2
ns
ns
ns
ns
t
CHZ
____
____
____
____
____
t
OE
Output Enable Access Time
Output Enable Low to Output Active
Output Enable High to Output High-Z
3.1
3.3
3.5
3.8
4.2
____
____
____
____
____
(2)
(2)
0
0
0
0
0
tOLZ
____
____
____
____
____
3.1
3.3
3.5
3.8
4.2
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SA
SS
SD
SW
SAV
SC
Address Setup Time
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
t
Address Status Setup Time
Data In Setup Time
t
t
Write Setup Time
t
Address Advance Setup Time
Chip Enable/Select Setup Time
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HA
HS
HD
HW
HAV
HC
Address Hold Time
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Status Hold Time
Data In Hold Time
t
t
Write Hold Time
t
Address Advance Hold Time
Chip Enable/Select Hold Time
t
Sleep
____
____
____
____
____
____
____
____
____
____
t
ZZPW
ZZ Pulse Width
100
100
20
100
100
22
100
100
24
100
100
27
100
100
30
ns
ns
(3)
ZZR
ZZ Recovery Time
Configuration Set-up Time
t
____
____
____
____
____
(4)
CFG
ns
t
4876tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
11
1998 Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF PIPELINED READ CYCLE(1,2)
12
1998 Integrated Device Technology, Inc.
DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
TIMING WAVEFORM OF COMBINED PIPELINED READ AND WRITE CYCLES(1,2,3)
13
1998 Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 - GW CONTROLLED(1,2,3)
14
1998 Integrated Device Technology, Inc.
DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
TIMING WAVEFORM OF WRITE CYCLE NO. 2 - BYTE CONTROLLED(1,2,3)
15
1998 Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SLEEP (ZZ) AND POWER-DOWN MODES(1,2,3)
16
1998 Integrated Device Technology, Inc.
DSC-4876/2
ORDERING INFORMATION
IDT
XXX
S
X
XX
Device
Type
Power Speed
Package
PF
BG
100-lead Plastic Thin Quad Flatpack (TQFP)
119-lead Ball Grid Array (BGA)
200
183
166
150
133
Frequency in Megahertz
128K x 36 Pipelined Burst Synchronous SRAM with 2.5V I/O
256K x 18 Pipelined Burst Synchronous SRAM with 2.5V I/O
128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O
256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O
71V2576
71V2578
71V3576
71V3578
4876 drw 13
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible products.
2975StenderWay
Santa Clara, CA 95054
800-544-SRAM
SRAMHELP@IDT.COM
fax: 831-754-4547
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
17
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