IDT71V428L15YGI [IDT]
Standard SRAM, 1MX4, 15ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32;
| 型号： | IDT71V428L15YGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 1MX4, 15ns, CMOS, PDSO32, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-32 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
IDT71V428S
IDT71V428L
Features
Description
◆
1M x 4 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
The IDT71V428 is a 4,194,304-bit high-speed Static RAM orga-
nized as 1M x 4. It is fabricated using IDT’s high-perfomance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs.
◆
◆
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
◆
◆
◆
TheIDT71V428has anoutputenablepinwhichoperates as fastas
5ns, withaddress access times as fastas 10ns. Allbidirectionalinputs
andoutputs ofthe IDT71V428are LVTTL-compatible andoperationis
from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiringnoclocks orrefreshforoperation.
◆
◆
Low power consumption via chip deselect
Available in 32-pin, 400 mil plastic SOJ package.
The IDT71V428 is packaged in a 32-pin, 400 mil Plastic SOJ.
Functional Block Diagram
A0
•
•
•
•
•
•
4,194,304-BIT
MEMORY ARRAY
ADDRESS
DECODER
A19
4
4
I/O0 – I/O3
•
I/O CONTROL
4
WE
OE
CS
CONTROL
LOGIC
3623 drw 01
SEPTEMBER 2004
1
©2004 IntegratedDeviceTechnology,Inc.
DSC-3623/06
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
Pin Description
A0
– A19
Address Inputs
Input
Input
Input
Input
I/O
A
A
A
A
A
0
1
2
3
4
A
A
A
A
A
19
18
17
16
15
Chip Select
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CS
Write Enable
Output Enable
Data Input/Output
3.3V Power
Ground
WE
OE
I/O0 - I/O3
CS
OE
I/O
I/O
0
3
VDD
Power
Gnd
V
DD
VSS
SO32-3
VSS
VSS
V
I/O
DD
I/O
1
3623 tbl 02
2
WE
A14
A13
A12
A11
A10
A5
A6
A7
A8
A9
Capacitance
NC
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
3623 drw 02
SOJ
Top View
CIN
V
7
8
pF
CI/O
V
pF
3623 tbl 03
NOTE:
1. This parameteris guaranteedbydevice characterization, butnotproductiontested.
Truth Table(1,2)
CS
OE
WE
I/O
Function
L
L
H
DATAOUT Read Data
DATAIN Write Data
High-Z Output Disabled
L
X
H
X
X
L
L
H
H
X
High-Z Deselected - Standby (ISB
)
(3)
HC
X
High-Z Deselected - Standby (ISB1
)
V
3623 tbl 01
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs ≥VHC or ≤VLC.
6.42
2
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended Operating
Temperature and Supply Voltage
Symbol
Rating
Value
Unit
Grade
Temperature
0°C to +70°C
–40°C to +85°C
V
SS
VDD
V
DD
Supply Voltage Relative to
VSS
-0.5 to +4.6
V
Commercial
Industrial
0V
0V
See Below
VIN, VOUT
Terminal Voltage Relative
to VSS
-0.5 to VDD+0.5
V
See Below
3623 tbl 05
T
BIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
oC
oC
W
TSTG
-55 to +125
Recommended DC Operating
Conditions
P
T
1
I
OUT
DC Output Current
50
mA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
3623 tbl 04
NOTE:
V
DD
SS
IH
IL
Supply Voltage
3.0
3.3
3.6
0
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operationofthe device atthese oranyotherconditions above those indicatedinthe
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
V
Ground
0
0
V
____
V
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3(1)
V
-0.3(2)
0.8
V
____
V
3623 tbl 06
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V428
Symbol
Parameter
Input Leakage Current
Test Condition
DD = Max., VIN = VSS to VDD
DD = Max., CS = VIH, VOUT = VSS to VDD
OL = 8mA, VDD = Min.
OH = -4mA, VDD = Min.
Min.
Max.
Unit
µA
µA
V
___
___
___
|ILI|
V
5
5
|ILO
|
Output Leakage Current
Output Low Voltage
Output High Voltage
V
VOL
I
0.4
___
VOH
I
2.4
V
3623 tbl 07
DC Electrical Characteristics(1,2,3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71V428S/L10
71V428S/L12
71V428S/L15
Ind.(5)
Symbol
Parameter
Dynamic Operating Current
Com'l.
Com'l.
Ind.
Com'l.
Ind.
Unit
S
L
S
L
S
L
150
140
60
150
—
60
140
130
50
140
130
50
130
120
40
130
120
40
mA
mA
mA
mA
mA
ICC
(4)
CS ≤ VLC, Outputs Open, VDD = Max., f = fMAX
Dynamic Standby Power Supply Current
ISB
(4)
CS ≥ VHC, Outputs Open, VDD = Max., f = fMAX
40
—
20
35
35
30
30
20
20
20
20
20
Full Standby Power Supply Current (static)
CS ≥ VHC, Outputs Open, VDD = Max., f = 0(4)
ISB1
10
—
10
10
10
10
mA
3623 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
6.42
3
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3623 tbl 09
AC Test Loads
3.3V
+1.5V
320Ω
OUT
DATA
50Ω
I/O
Z0 = 50Ω
5pF*
350Ω
30pF
3623 drw 03
3623 drw 04
Figure 1. AC Test Load
* Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
6
•
∆tAA,
t
ACS
5
4
3
(Typical, ns)
•
•
2
1
•
•
•
•
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
3623 drw 05
Figure 3. Output Capacitive Derating
6.42
4
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
71V428S/L10(2)
71V428S/L12
71V428S/L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACS
Read Cycle Time
10
12
15
ns
ns
ns
ns
____
____
____
t
Address Access Time
10
12
15
____
____
____
t
Chip Select Access Time
Chip Select to Output in Low-Z
10
12
15
____
____
____
(1)
4
4
4
tCLZ
____
____
____
(1)
Chip Deselect to Output in High-Z
Output Enable to Output Valid
5
6
7
ns
ns
ns
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
5
6
7
(1)
____
____
____
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
0
0
0
tOLZ
____
____
____
(1)
OHZ
5
6
7
t
____
____
____
tOH
4
4
4
(1)
PU
____
____
____
0
0
0
t
____
____
____
(1)
PD
10
12
15
t
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
AS
WP
WR
DW
DH
Write Cycle Time
10
8
12
8
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
t
8
8
t
0
0
t
8
8
10
0
t
Write Recovery Time
Data Valid to End of Write
Data Hold Time
0
0
t
6
6
7
t
0
0
0
____
____
____
(1)
OW
Output Active from End of Write
3
3
3
t
____
____
____
(1)
WHZ
Write Enable to Output in High-Z
6
7
7
ns
t
3623 tbl 10
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2. 0°C to +70°C temperature range only for low power 10ns (L10) speed grade.
6.42
5
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
tAA
OE
tOE
(5)
tOLZ
CS
(3)
tACS
(5)
(5)
tOHZ
t
CLZ
(5)
tCHZ
HIGH IMPEDANCE
DATAOUT
DATAOUT VALID
t
PD
tPU
I
I
CC
SB
V
DD SUPPLY
CURRENT
3623 drw 06
Timing Waveform of Read Cycle No. 2(1,2,4)
t
RC
ADDRESS
DATAOUT
tAA
t
OH
tOH
PREVIOUS DATAOUT VALID
DATAOUT VALID
3623 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
6
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No.1 (WE Controlled Timing)(1,2,4)
t
WC
ADDRESS
CS
tAW
(2)
tWR
tAS
t
WP
WE
(5)
(5)
t
CHZ
(5)
tWHZ
tOW
HIGH IMPEDANCE
(3)
(3)
DATAOUT
DATAIN
tDH
t
DW
DATAIN VALID
3623 drw 08
Timing Waveform of Write Cycle No.2 (CS Controlled Timing)(1,4)
t
WC
ADDRESS
CS
t
AW
tWR
t
CW
t
AS
WE
t
DW
tDH
DATAIN
DATAIN VALID
3623 drw 09
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to
be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as
the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6.42
7
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
IDT
X
X
71V428
X
XX
XXX
X
Die
Revision
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
I
Industrial (–40°C to +85°C)
G
Restricted hazardous substance device
Y
32-pin 400-mil SOJ (S032-
3)
10*
12
Speed in nanoseconds
15
Standard Power
Low Power
S
L
Blank
Y
First Generation or current stepping being shipped
Second Generation die step
* Commercial only for low power (L10) speed grade.
3623 drw 10
6.42
8
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
8/31/99
Updated to new format
Added footnote for VHC in Truth Table
Added footnote on jig and scope capacitance in Figure 2
Revised footnote on Write Cycle No. 1 diagram
Added Datasheet Document History
AddedIndustrialtemperaturerangeofferings
Updatedorderinginformationfordierevision
Updatednote,L10speedgradecommercialtemperatureonlyandupdateddiesteppingfromYFtoY.
Added"Restrictedhazardoussubstancedevice"toorderinginformation.
Pg. 2
Pg. 4
Pg. 7
Pg. 9
Pg. 1–9
Pg. 8
Pg. 8
Pg. 8
9/29/99
11/26/02
07/31/03
09/30/04
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for SALES:
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800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
9
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