IDT71V546XS117PFGI [IDT]
ZBT SRAM, 128KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100;
| 型号： | IDT71V546XS117PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 128KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总21页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K x 36, 3.3V Synchronous IDT71V546S/XS
SRAM with ZBT™ Feature,
Burst Counter and Pipelined Outputs
Features
◆
128K x 36 memory configuration, pipelined outputs
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
clockcycle,andtwocycles laterits associateddatacycleoccurs,beit
read or write.
TheIDT71V546containsdataI/O,addressandcontrolsignalregis-
ters. Outputenableistheonlyasynchronoussignalandcanbeusedto
disabletheoutputsatanygiventime.
AClockEnable (CEN)pinallows operationofthe IDT71V546tobe
suspended as long as necessary. All synchronous inputs are ignored
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany
burst that was in progress is stopped. However, any pending data
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo
cyclesafterthechipisdeselectedorawriteinitiated.
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized registered outputs eliminate the
need to control OE
◆
◆
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin TQFP package
TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the
IDT71V546canprovidefourcyclesofdataforasingleaddresspresented
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LD signalis usedtoloada newexternaladdress (ADV/LD =
LOW) orincrementtheinternalburstcounter(ADV/LD =HIGH).
TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminatedeadbuscycleswhenturningthebusaroundbetweenreads
TM
andwrites,orwritesandreads. ThusithasbeengiventhenameZBT ,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
PinDescriptionSummary
A0
- A16
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Three Chip Enables
Output Enable
CE1
, CE
2
, CE
2
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
Synchronous
Static
LBO
I/O0
- I/O31, I/OP1 - I/OP4
Synchronous
Static
VDD
3.3V Power
Supply
Supply
VSS
Ground
Static
3821 tbl 01
FEBRUARY 2007
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
1
DSC-3821/05
©2007IntegratedDeviceTechnology,Inc.
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a
combination of the rising edge of CLK and ADV/LD Low, CEN Low and true
chip enables.
A0 - A16
Address/Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with
new address and control when it is sampled low at the rising edge of clock with
the chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
ADV/LD
Read/Write
I
I
N/A
R/W signal is a synchronous input that identified whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place two clock cycles later.
R/W
Clock Enable
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other
synchronous inputs, including clock are ignored and outputs remain unchanged.
The effect of CEN sampled high on the device outputs is as if the low to high
clock transition did not occur. For normal operation, CEN must be sampled low
at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. Enable 9-bit byte has its own active low byte
BW
1
- BW
4
write enable. On load write cycles (When R/W and ADV/LD are sampled low)
the appropriate byte write signal (BW
1
- BW4) must be valid. The byte write
signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written
into the device two cycles later. BW
1
- BW4 can all be tied low if always doing
write to the entire 36-bit word.
Chip Enables
Synchronous active low chip enable. CE
1
and CE
2
are used with CE
2 to
CE
1
, CE
2
enable the IDT71V546. (CE or CE sampled high or CE
1
2
2
sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT™
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after
deselect is initiated.
CE2
CLK
Chip Enable
Clock
I
I
HIGH
N/A
Synchronout active high chip enable. CE
2
is used with CE
1
and CE
2 to enable
the chip. CE has inverted polarity but otherwise identical to CE
2
1
and CE2.
This is the clock input to the IDT71V546. Except for OE, all timing references for
the device are made with respect to the rising edge of CLK.
I/O
I/OP1 - I/OP4
0
- I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
Linear Burst
Order
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is
selected. When LBO is low the Linear burst sequence is selected. LBO is a
static DC input.
LBO
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V546.
When OE is high the I/O pins are in a high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE can
be tied low.
OE
V
DD
Power Supply
Ground
N/A
N/A
N/A
N/A
3.3V power supply input.
VSS
Ground pin.
3821 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
128K x 36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
Control
CEN
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
3821 drw 01
.
Data I/O [0:31], I/O P[1:4]
3
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 128K X 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
79
.
3
78
4
77
V
DD
V
DD
5
VSS
76
75
74
73
V
SS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
V
V
SS
70
69
68
67
66
V
DD
DD
I/O22
I/O
I/O
9
8
I/O23
(1)
V
DD
V
SS
V
V
V
DD
DD
SS
V
DD
PK100-1
65
64
V
DD
VSS
63
62
I/O24
I/O25
I/O
I/O
7
6
61
60
59
V
DD
V
DD
VSS
V
SS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
58
57
56
55
VSS
V
V
SS
DD
54
53
V
DD
I/O30
I/O31
I/OP4
I/O
I/O
1
0
.
52
51
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3821 drw 02
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be connected directly to VDD as long as the input voltage is > VIH.
2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively.
4
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedDCOperating
Conditions
Commercial &
Symbol
Rating
Unit
Industrial Values
Symbol
Parameter
Min. Typ.
Max.
3.465
0
Unit
V
(2)
V
TERM
Terminal Voltage
with Respect to GND
-0.5 to +4.6
V
(3)
V
DD
Supply Voltage
3.135 3.3
V
SS
IH
IH
IL
Ground
0
0
V
(3)
TERM
V
Terminal Voltage
-0.5 to VDD+0.5
0 to +70
V
with Respect to GND
____
V
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
4.6
V
Commercial
Operating Ambient
Temperature
V
2.0
V
DD+0.3(2)
V
____
____
oC
oC
V
-0.5(1)
0.8
V
T (4)
A
Industrial
Operating Ambient
Temperature
3821 tbl 04
NOTES:
-40 to +85
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
3. VDD needs to be ramped up smoothly to the operating level. If there are any
glitches on VDD that cause the voltage level to drop below 2.0 volts then the
device needs to be reset by holding VDD to 0.0 volts for a minimum of 100 ms.
T
BIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
2.0
oC
oC
W
TSTG
PT
I
OUT
DC Output Current
50
mA
RecommendedOperating
TemperatureandSupplyVoltage
Ambient
3821 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VDD and Input terminals only.
3. I/O terminals.
4. During production testing, the case temperature equals the ambient temperature.
Grade
Temperature(1)
0OC to +70OC
-40OC to +85OC
VSS
VDD
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
3821 tbl 03
NOTES:
1. During production testing, the case temperature equals the ambient temperature.
100TQFPCapacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
5
7
pF
CI/O
V
pF
3821 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
5
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
Chip(5)
ADV/LD
ADDRESS
USED
PREVIOUIS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
R/W
Enable
(2 cycles later)
(7)
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D
(7)
Q
(7)
Valid
LOAD WRITE/
BURST WRITE
BURST WRITE
D
(Advance Burst Counter)(2)
(7)
L
X
X
H
X
Internal
LOAD READ/
BURST READ
BURST READ
Q
(Advance Burst Counter)(2)
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3)
HiZ
HiZ
X
X
DESELECT / NOOP
X
NOOP
(4)
SUSPEND
Previous Value
3821 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if either one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
BW
1
BW
X
L
2
BW
3
BW
X
L
4
Operation
R/W
H
L
READ
X
L
X
L
WRITE ALL BYTES
(2)
WRITE BYTE 1 (I/O [0:7], I/OP1
)
L
L
H
L
H
H
L
H
H
H
L
(2)
WRITE BYTE 2 (I/O [8:15], I/OP2
)
L
H
H
H
H
(2)
(2)
WRITE BYTE 3 (I/O [16:23], I/OP3
)
L
H
H
H
WRITE BYTE 4 (I/O [24:31], I/OP4
)
L
H
H
NO WRITE
L
H
3821 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
6
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
1
0
0
1
0
0
3821 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
3821 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
n+37
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
CLOCK
(2)
ADDRESS
(A0 - A16)
A37
A37
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
(2)
CONTROL
C37
C37
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q35
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q31
I/O [0:31], I/O P[1:4]
,
NOTE:
3821 drw 03
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
7
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load,
Burst, Deselect and NOOP Cycles(2)
(1)
CE
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWx
X
X
X
X
X
X
X
X
L
OE
X
X
L
Cycle
Address
A0
X
R/W
H
X
H
X
X
H
X
X
L
ADV/LD
I/O
X
Comments
n
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
Load read
Burst read
n+1
X
L
X
n+2
A1
X
Q0 Load read
0+1 Deselect or STOP
Q1 NOOP
n+3
H
X
L
L
Q
n+4
X
L
n+5
A2
X
X
X
L
Z
Z
Load read
Burst read
n+6
X
H
L
n+7
X
Q2 Deselect or STOP
Q2+1 Load write
n+8
A3
X
L
n+9
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
Load write
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A4
X
L
D3
X
X
L
H
X
L
X
X
L
D3+1 Deselect or STOP
X
D4
Z
NOOP
A5
A6
A7
X
Load write
Load read
Load write
H
L
L
X
L
Z
L
D5
X
H
X
L
X
L
L
Q6 Burst write
D7 Load read
7+1 Burst read
Q8 Load write
A8
X
X
X
L
X
X
L
X
L
D
A9
3821 tbl 11
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
8
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
ReadOperation(1)
(2)
CE
CEN
L
BWx
X
OE
X
Cycle
Address
R/W
H
ADV/LD
I/O
X
Comments
Address and Control meet setup
Clock Setup Valid
n
A0
X
L
X
X
L
n+1
n+2
X
X
L
X
X
X
X
X
X
X
X
L
Q0 Contents of Address A0 Read Out
3821 tbl 12
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
BurstReadOperation(1)
(2)
CE
CEN
L
BWx
X
OE
X
X
L
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
n
A0
X
H
L
H
H
H
H
L
L
Address and Control meet setup
Clock Setup Valid, Advance Counter
Address A0 Read Out, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
L
L
X
X
X
X
L
X
Q0
X
X
L
X
L
Q
0+1 Address A0+1 Read Out, Inc. Count
0+2 Address A0+2 Read Out, Inc. Count
0+3 Address A0+3 Read Out, Load A1
Q0 Address A0 Read Out, Inc. Count
Q1 Address A1 Read Out, Inc. Count
Q1+1 Address A1+1 Read Out, Load A2
X
X
L
X
L
Q
A1
X
H
L
X
L
Q
X
H
H
L
X
X
L
L
X
L
X
X
L
X
L
A2
H
L
X
L
3821 tbl 13
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
9
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
WriteOperation(1)
(2)
CE
CEN
L
BWx
L
OE
X
Cycle
Address
R/W
L
ADV/LD
I/O
X
Comments
Address and Control meet setup
Clock Setup Valid
n
A0
X
L
X
X
L
n+1
n+2
X
X
L
X
X
X
X
X
X
L
X
X
D0
Write to Address A0
3821 tbl 14
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
(2)
CE
CEN
L
BWx
L
OE
X
X
X
X
X
X
X
X
X
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
Address and Control meet setup
Clock Setup Valid, Inc. Count
Address A0 Write, Inc. Count
n
A0
X
L
L
H
H
H
H
L
L
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
L
X
X
X
X
L
L
L
X
X
L
L
D0
X
L
L
D
0+1 Address A0+1 Write, Inc. Count
0+2 Address A0+2 Write, Inc. Count
0+3 Address A0+3 Write, Load A1
D0 Address A0 Write, Inc. Count
D1 Address A1 Write, Inc. Count
D1+1 Address A1+1 Write, Load A2
X
L
L
D
A1
X
L
L
D
X
X
L
H
H
L
X
X
L
L
L
X
L
L
A2
L
L
3821 tbl 15
NOTE:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
10
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation With Clock Enable Used(1)
(2)
CE
CEN
BWx
OE
X
X
X
L
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
Address and Control meet setup
Clock n+1 Ignored
n
A0
H
L
X
L
X
X
L
L
L
L
L
X
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
X
L
H
L
X
X
A1
H
X
X
Clock Valid
X
X
X
X
L
H
H
L
X
Q0 Clock Ignored. Data Q0 is on the bus
Q0 Clock Ignored. Data Q0 is on the bus
X
X
X
L
A2
H
X
L
Q0
Address A0 Read out (but trans.)
A3
H
L
L
X
L
Q1 Address A1 Read out (bus trans.)
A4
H
L
L
X
L
Q2
Address A2 Read out (bus trans.)
3821 tbl 16
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
(2)
CE
CEN
BWx
OE
X
X
X
X
X
X
X
X
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
Address and Control meet setup
Clock n+1 Ignored
Clock Valid
n
A0
L
L
X
L
X
X
L
L
L
L
L
L
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
X
L
H
L
X
L
X
A1
X
X
X
X
L
X
X
L
H
H
L
X
X
L
X
Clock Ignored
X
X
Clock Ignored
A2
D0
Write data D0
A3
L
L
L
L
D1 Write data D1
D2 Write data D2
A4
L
L
L
L
3821 tbl 17
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
11
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation With Chip Enable Used(1)
(1)
CE
CEN
BWx
OE
X
X
X
X
L
Cycle
Address
R/W
ADV/LD
I/O
?
Comments
n
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
X
Deselected
Deselected
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
X
H
L
L
X
?
A0
X
H
L
X
Z
Address and Control meet setup
Deselected or STOP
X
H
L
L
X
Z
A1
X
H
L
X
Q0
Z
Address A0 read out. Load A1
Deselected or STOP
X
H
H
L
L
X
X
L
X
X
L
X
Q1 Address A1 Read out. Deselected
A2
X
H
L
X
X
X
L
Z
Z
Address and Control meet setup
Deselected or STOP
X
H
H
L
X
X
X
L
X
Q2
Address A2 read out. Deselected
3821 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation With Chip Enable Used(1)
(1)
CE
CEN
BWx
X
X
L
OE
X
X
X
X
X
X
X
X
X
X
Cycle
Address
R/W
X
X
L
ADV/LD
I/O
?
Comments
Deselected
n
X
X
L
L
L
L
L
L
L
L
L
L
H
L
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
H
L
L
?
Deselected
A0
X
L
Z
Address and Control meet setup
Deselected or STOP
X
L
H
L
L
X
L
Z
A1
X
L
D0
Z
Address D0 Write In. Load A1
Deselected or STOP
X
X
L
H
H
L
L
X
X
L
X
L
D1
Z
Address D1 Write In. Deselected
Address and Control meet setup
Deselected or STOP
A2
X
L
X
X
H
H
L
X
X
Z
X
L
D2
Address D2 Write In. Deselected
3821 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
12
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
|ILI
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
5
Unit
µA
µA
µA
V
___
|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
(1)
___
___
___
|
VDD = Max., VIN = 0V to VDD
30
5
LBO Input Leakage Current
Output Leakage Current
Output Low Voltage
|
CE > VIH or OE > VIH, VOUT = 0V toVDD, VDD = Max.
OL = 5mA, VDD = Min.
OH = -5mA, VDD = Min.
VOL
I
0.4
___
VOH
Output High Voltage
I
2.4
V
3821 tbl 20
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application.
DC Electrical Characteristics Over the Opearting Temperature
and Supply Voltage Range(1) (VDD = 3.3V +/-5%, VHD = VDD–0.2V, VLD = 0.2V)
S133
Com'l
S117
Com'l
S100
Com'l
Symbol
Parameter
Test Conditions
Device Selected, Outputs Open,
Ind
310
45
Ind
285
45
Ind
260
45
Unit
Operating Power
Supply Current
mA
IDD
300
40
275
40
250
40
(2)
ADV/LD = X, VDD = Max., VIN > VIH or < VIL, f = fMAX
CMOS Standby Power Device Deselected, Outputs Open, VDD = Max., VIN >
Supply Current
VHD or < VLD, f = 0(2)
mA
mA
ISB1
ISB2
ISB3
Clock Running Power Device Deselected, Outputs Open, VDD = Max., VIN >
Supply Current
110
40
120
45
105
40
115
45
100
40
110
45
(2)
VHD or < VLD, f = fMAX
Idle Power
Supply Current
Device Selected, Outputs Open, CEN > VIH VDD = Max.,
mA
(2)
VIN > VHD or < VLD, f = fMAX
3821 tbl 21
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
AC Test Conditions
Input Pulse Levels
AC Test Loads
+
1.5V
0 to 3V
2ns
Input Rise/Fall Times
50Ω
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
1.5V
I/O
Z = 50Ω
0
3821 drw 04
See Figures 1
,
3821 tbl 22
Figure 1. AC Test Load
6
5
4
3
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
3821 drw 05
,
Figure 2. Lumped Capacitive Load, Typical Derating
13
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
71V546S133
71V546S117
71V546S100
Min.
Max.
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
Clock Parameters
____
____
____
t
CYC
Clock Cycle Time
7.5
8.5
10
ns
MHz
ns
t (1)
F
Clock Frequency
133
117
100
____
____
____
(2)
CH
____
____
____
t
Clock High Pulse Width
Clock Low Pulse Width
2.5
2.5
3
3
3.5
3.6
(2)
CL
____
____
____
t
ns
Output Parameters
____
____
____
t
CD
Clock High to Valid Data
4.2
4.5
5
ns
ns
ns
ns
ns
ns
ns
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
1.5
1.5
1.5
1.5
1.5
1.5
(3,4,5)
CLZ
____
____
____
t
(3,4,5)
tCHZ
1.5
3.5
1.5
3.5
1.5
3.5
____
____
____
tOE
4.2
4.5
5
(3,4)
(3.4)
____
____
____
tOLZ
0
0
0
____
____
____
tOHZ
3.5
3.5
3.5
Setup Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
SADV
SC
SB
Clock Enable Setup Time
2.0
2.0
1.7
2.0
2.0
2.0
2.0
2.0
2.0
1.7
2.0
2.0
2.0
2.0
2.2
2.2
2.0
2.2
2.2
2.2
2.2
ns
ns
ns
ns
ns
ns
ns
t
Address Setup Time
t
Data in Setup Time
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
t
t
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data in Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
ns
3821 tbl 23
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 2.0V and LOW below 0.8V.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
14
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
15
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
.
16
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
.
17
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
.
18
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
19
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATA Out
Valid
NOTE:
3821 drw 11
1. A read operation is assumed to be in progress.
OrderingInformation
X
IDT
71V546
S
XX
PF
X
X
Process/
Temperature
Range
Device
Type
Power Speed
Package
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Restricted hazardous substance device
100 pin Plastic Thin Quad Flatpack (PK100-1)
PF
133
117
100
Clock Frequency in Megahertz
First or current generation die step
Current generation die step optional
Blank
X
100 Thin Quad Flatpack Packaging
PART NUMBER
tCD PARAMETER SPEED IN MEGAHERTZ CLOCK CYCLE TIME
3821 drw 12
7.5 ns
8.5 ns
10 ns
4.2 ns
4.5 ns
5 ns
133 MHz
117 MHz
100 MHz
71V546S133PF
71V546S117PF
71V546S100PF
20
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
6/15/99
9/13/99
Updatedtonewformat
CorrectedISB3conditions
Pg. 12
Pg. 20
Pg. 3, 12, 13, 19
Pg. 3,4
AddedDatasheetDocumentHistory
AddedIndustrialTemperaturerangeofferings
Moved Operating temperature & DC operating tables from page 3 to new page 5. Moved Absolute
rating&Capacitancetablesfrompage4tonewpage5.AddclarificationnotetoRecommended
OperatingTemperatureandAbsoluteMaxRatingstables.
12/31/99
11/22/05
Pg. 20
Pg. 20
Updatedorderinformationwith"Restrictedhazardoussubstancedevice"
AddedXgenerationdiesteptodatasheetorderinginformation.
02/23/07
CORPORATE HEADQUARTERS
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for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
21
6.42
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