IDT71V547XS80PF [IDT]
ZBT SRAM, 128KX36, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100;
| 型号： | IDT71V547XS80PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 128KX36, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：1363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K X 36, 3.3V Synchronous IDT71V547S/XS
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
Features
◆
128K x 36 memory configuration, flow-through outputs
Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
TheIDT71V547containsaddress,data-inandcontrolsignalregisters.
Theoutputsareflow-through(nooutputdataregister).Outputenableis
theonlyasynchronoussignalandcanbeusedtodisabletheoutputsat
anygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold
their previous values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany
burstinprogressisstopped.However,anypendingdatatransfers(reads
orwrites)willbecompleted.Thedatabuswilltri-stateonecycleafterthe
chipwasdeselectedorwriteinitiated.
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized signal eliminates the need to
control OE
◆
◆
◆
◆
◆
◆
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
TheIDT71V547hasanon-chipburstcounter. Intheburstmode,the
IDT71V547canprovidefourcyclesofdataforasingleaddresspresented
totheSRAM.TheorderoftheburstsequenceisdefinedbytheLBOinput
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW)orincrementtheinternalburstcounter(ADV/LD=HIGH).
TheIDT71V547SRAMutilizesIDT'shigh-performance,high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.
Description
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronousSRAMorganizedas128Kx36bits. Itisdesignedtoeliminate
deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,
orwritesandreads.ThusithasbeengiventhenameZBTTM,orZeroBus
Turn-around.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andonthenextclockcycle,itsassociateddatacycleoccurs,beit
read or write.
PinDescriptionSummary
A
0
- A16
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Three Chip Enables
Output Enable
CE
1
, CE
2, CE
2
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
3.3V Power
Synchronous
Static
LBO
- I/O31, I/OP1
I/OP4
I/O
0
-
Synchronous
Static
V
DD
Supply
Supply
VSS
Ground
Static
3822 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
OCTOBER 2008
1
DSC-3822/04
©2007IntegratedDeviceTechnology,Inc.
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
Address Inputs
I
N/A
A0 - A16
Synchronous Address inputs. The address register is triggered by a combination
of the rising edge of CLK, ADV/LD Low, CEN Low and true chip enables.
Address/Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new
address and control when it is sampled low at the rising edge of clock with the
chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
ADV/LD
Read/Write
I
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place one clock cycle later.
R/W
Clock Enable
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other
synchronous inputs, including clock are ignored and outputs remain unchanged.
The effect of CEN sampled high on the device outputs is as if the low to high
clock transition did not occur. For normal operation, CEN must be sampled low at
rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. Enable 9-bit byte has its own active low byte
BW
1
- BW
4
write enable. On load write cycles (When R/W and ADV/LD are sampled low) the
appropriate byte write signal (BW
1
- BW4) must be valid. The byte write signal
must also be valid on each cycle of a burst write. Byte Write signals are ignored
when R/W is sampled high. The appropriate byte(s) of data are written into the
device one cycle later. BW
1
- BW4 can all be tied low if always doing write to the
entire 36-bit word.
Chip Enables
Synchronous active low chip enable. CE
1
and CE
2
are used with CE
2 to
CE
1
, CE
2
enable the IDT71V547. (CE or CE sampled high or CE
1
2
2
sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. This device has
a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect
is initiated.
CE2
CLK
Chip Enable
Clock
I
HIGH
N/A
Synchronout active high chip enable. CE
2
is used with CE
1
and CE
2 to enable
the chip. CE has inverted polarity but otherwise identical to CE
2
1
and CE2.
I
I/O
I
This is the clock input to the IDT71V547. Except for OE, all timing references for
the device are made with respect to the rising edge of CLK.
I/O
0
- I/O31
Data Input/Output
N/A
Data input/output (I/O) pins. The data input path is registered, triggered by the
rising edge of CLK. The data output path is flow-through (no output register).
I/OP1 - I/OP4
Linear Burst
Order
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is
selected. When LBO is low the Linear burst sequence is selected. LBO is a static
DC input.
LBO
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V547.
When OE is high the I/O pins are in a high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE can be
tied low.
OE
V
DD
SS
Power Supply
Ground
N/A
N/A
N/A
N/A
3.3V power supply input.
V
Ground pin.
3822 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
128K x 36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
CE , CE2 CE
D
D
Q
Q
Address
1
2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
Clock
Gate
OE
,
Data I/O [0:31], I/O P[1:4]
3822 drw 01
RecommendedDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Parameter
Min. Typ.
Max.
3.465
0
Unit
V
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
V
SS
VDD
V
V
DD
SS
Supply Voltage
3.135 3.3
0V
0V
3.3V±5%
3.3V±5%
Ground
0
0
V
____
3822 tbl 03
V
IH
IH
IL
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
4.6
V
____
____
V
2.0
V
DD+0.3(2)
0.8
V
V
-0.5(1)
V
3822 tbl 04
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
3
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
PinConfiguration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
1
I/OP2
I/O15
I/O14
80
79
78
77
2
3
4
VDD
VDD
5
VSS
76
75
74
73
VSS
I/O18
I/O19
I/O20
I/O21
6
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
V
V
SS
DD
VDD
I/O22
69
68
67
66
65
64
63
62
61
60
59
I/O9
I/O8
I/O23
(1)
SS
V
V
V
SS
SS
V
V
V
DD
DD
SS
PK100-1
VDD
VSS
I/O24
I/O25
I/O7
I/O6
VDD
V
V
DD
SS
VSS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
58
57
56
55
4
3
2
VSS
VSS
54
53
52
51
VDD
VDD
I/O
I/O
I/OP1
1
I/O30
I/O31
I/OP4
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3822 drw 02
Top View
TQFP
NOTES:
1. Pin 14 does not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively.
AbsoluteMaximumRatings(1)
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Symbol
Rating
Value
Unit
(2)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
V
TERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +3.6
V
(3)
(4)
DC Input Voltage(5)
C
IN
V
5
7
pF
V
V
TERM
–0.5 to VDDQ+0.5
V
V
TERM
DC Voltage Applied to Outputs in –0.5 to VDDQ+0.5
High-Z State(5)
C
I/O
V
pF
3822 tbl 06
T
A
Operating Temperature
0°C to 70°C
–55 to +125
°C
°C
NOTE:
1. Thisparameterisguaranteedbydevicecharacterization,butnotproductiontested.
TBIAS
Ambient Temperature with Power
Applied (Temperature Under
Bias)
T
STG
OUT
ESD
Storage Temperature
–65 to +150
20
°C
mA
V
I
Current into Outputs (Low)
V
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
>2001
ILU
Latch-Up Current
>200
mA
NOTES:
5284 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDD and Input terminals only.
3. I/O terminals.
4
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
CEN
R/W
Chip(5)
Enable
ADV/LD
BWx
ADDRESS
USED
PREVIOUIS CYCLE
CURRENT CYCLE
I/O
(1 cycle later)
L
L
L
L
H
X
Select
Select
X
L
L
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D(7)
Q(7)
D(7)
H
Valid
LOAD WRITE/
BURST WRITE
BURST WRITE
(Advance Burst Counter)(2)
L
X
X
H
X
Internal
LOAD READ/
BURST READ
BURST READ
Q(7)
(Advance Burst Counter)(2)
L
L
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3)
NOOP
HiZ
HiZ
X
X
DESELECT / NOOP
X
H
SUSPEND(4)
Previous Value
3822 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature
of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus
willtri-stateonecycleafterdeselectisinitiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if either one of thechip enable is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
BW
1
BW
2
BW
3
BW
4
Operation
R/W
H
L
READ
X
X
X
X
WRITE ALL BYTES
L
L
L
L
(2)
WRITE BYTE 1 (I/O [0:7], I/OP1
)
L
L
H
L
H
H
L
H
H
H
L
(2)
WRITE BYTE 2 (I/O [8:15], I/OP2
)
L
H
H
H
H
(2)
WRITE BYTE 3 (I/O [16:23], I/OP3
)
L
H
H
H
(2)
WRITE BYTE 4 (I/O [24:31], I/OP4
)
L
H
H
NO WRITE
L
H
3822 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
5
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
1
0
0
1
0
0
3822 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
3822 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
n+37
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
CLOCK
(2)
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A16)
CONTROL
(R/W, ADV/LD, BWx)
(2)
.,
DATA
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
I/O [0:31], I/O P[1:4]
3822 drw 03
NOTE:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
DeselectandNOOPCycles(2)
(1)
CE
L
CEN
L
BWx
X
X
X
X
X
X
X
X
L
OE
X
L
Cycle
Address
A0
X
R/W
H
X
H
X
X
H
X
X
L
ADV/LD
I/O
Comments
n
L
H
L
D1 Load read
n+1
X
L
L
Q0
0+1 Load read
Q1 Deselect or STOP
Burst read
n+2
A1
X
L
L
Q
n+3
L
H
X
L
L
L
n+4
X
H
L
L
X
X
L
Z
Z
NOOP
n+5
A2
X
L
Load read
Burst read
n+6
H
L
X
H
L
L
Q2
n+7
X
L
L
Q2+1 Deselect or STOP
n+8
A3
X
L
L
X
X
X
X
X
X
X
L
Z
Load write
Burst write
n+9
X
L
H
L
X
L
L
L
D3
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A4
X
L
L
D
3+1 Load write
D4 Deselect or STOP
NOOP
X
X
L
L
H
X
L
L
X
X
L
X
H
L
L
Z
A5
A6
A7
X
L
Z
Load write
Load read
Load write
Burst write
H
L
L
L
L
X
L
D5
Q6
D7
L
L
L
X
H
X
L
H
L
X
L
L
L
X
X
L
A8
X
L
X
X
L
D
7+1 Load read
Q8 Burst read
Q8+1 Load write
H
L
X
L
L
A9
L
L
3822 tbl 11
NOTE:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
7
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
ReadOperation(1)
(2)
CE
L
CEN
L
BWx
X
OE
X
Cycle
Address
R/W
H
ADV/LD
I/O
X
Comments
n
A0
X
L
Address and Control meet setup
Contents of Address A0 Read Out
n+1
X
X
X
X
X
L
Q0
3822 tbl 12
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
BurstReadOperation(1)
Cycle
Address
R/W
ADV/LD
CE(2)
L
CEN
BWx
X
OE
X
L
I/O
X
Comments
n
A0
X
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
Address and Control meet setup
Address A0 Read Out, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
X
Q0
X
X
X
X
L
Q0+1 Address A0+1 Read Out, Inc. Count
Q0+2 Address A0+2 Read Out, Inc. Count
Q0+3 Address A0+3 Read Out, Load A1
X
X
X
X
L
X
X
X
X
L
A1
X
H
L
X
L
Q0
Q1
Address A0 Read Out, Inc. Count
Address A1 Read Out, Inc. Count
X
H
L
X
X
L
A2
H
L
X
L
Q
1+1 Address A1+1 Read Out, Load A2
3822 tbl 13
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
WriteOperation(1)
(2)
CE
L
CEN
BWx
OE
X
Cycle
Address
R/W
L
ADV/LD
I/O
X
Comments
Address and Control meet setup
Write to Address A0
n
A0
X
L
L
L
L
n+1
X
X
X
X
X
D0
3822 tbl 14
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Write Operation(1)
(2)
CE
L
CEN
BWx
OE
X
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
Address and Control meet setup
Address A0 Write, Inc. Count
n
A0
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
H
H
H
H
L
X
X
X
X
L
X
D0
X
X
X
D0+1 Address A0+1 Write, Inc. Count
X
X
X
D
0+2 Address A0+2 Write, Inc. Count
0+3 Address A0+3 Write, Load A1
X
X
X
D
A1
X
L
X
D0
D1
Address A0 Write, Inc. Count
Address A1 Write, Inc. Count
X
H
L
X
L
X
A2
L
X
D1+1 Address A1+1 Write, Load A2
3822 tbl 15
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
8
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation With Clock Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE(2)
L
CEN
BWx
OE
X
X
L
I/O
X
Comments
Address and Control meet setup
Clock n+1 Ignored
n
A0
X
H
L
X
L
L
X
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
H
L
X
X
A1
X
H
L
X
Q0
Q0
Q0
Q1
Q2
Q3
Address A0 Read out, Load A1
Clock Ignored. Data Q0 is on the bus
Clock Ignored. Data Q0 is on the bus
Address A1 Read out, Load A2
Address A2 Read out, Load A3
Address A3 Read out, Load A4
X
X
X
L
X
H
H
L
X
L
X
X
X
X
L
A2
A3
A4
H
L
X
L
H
L
L
L
X
L
H
L
L
L
X
L
3822 tbl 16
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation With Clock Enable Used(1)
(2)
CE
CEN
BWx
OE
X
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
Address and Control meet setup
Clock n+1 Ignored
n
A0
X
L
L
X
L
X
X
L
L
L
L
L
L
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
H
L
X
X
X
A1
X
L
L
X
D0
X
Write data D0, Load A1
Clock Ignored
X
X
X
L
H
H
L
X
X
X
X
X
X
X
Clock Ignored
A2
A3
A4
L
L
X
D1
D2
D3
Write data D1, Load A2
Write data D2, Load A3
Write data D3, Load A4
L
L
L
L
X
L
L
L
L
X
3822 tbl 17
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
9
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
(1)
CE
H
H
L
CEN
BWx
OE
X
X
X
L
Cycle
Address
R/W
ADV/LD
I/O(3)
?
Comments
n
X
X
X
L
L
L
L
L
L
L
L
L
L
L
X
Deselected
Deselected
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
X
L
X
Z
A0
X
H
L
X
Z
Address A0 and Control meet setup
Address A0 read out. Deselected
Address A1 and Control meet setup
Address A1 Read out. Deselected
Deselected
X
H
L
L
X
Q0
Z
A1
X
H
L
X
X
L
X
H
H
L
L
X
Q1
Z
X
X
L
X
X
X
L
A2
X
H
L
X
Z
Address A2 and Control meet setup
Address A2 read out. Deselected
Deselected
X
H
H
L
X
Q2
Z
X
X
L
X
X
3822 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Write Operation with Chip Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE(1)
H
CEN
BWx
OE
X
X
X
X
X
X
X
X
X
X
I/O
?
Comments
n
X
X
X
L
L
L
L
L
L
L
L
L
L
L
X
Deselected
Deselected
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
X
H
L
X
Z
A0
X
L
L
L
L
Z
Address A0 and Control meet setup
Address D0 Write In. Deselected
Address A1 and Control meet setup
Address D1 Write In. Deselected
Deselected
X
H
L
X
D0
Z
A1
X
L
L
L
L
X
H
L
X
D1
Z
X
X
H
L
X
A2
X
L
L
L
L
Z
Address A2 and Control meet setup
Address D2 Write In. Deselected
Deselected
X
H
L
X
D2
Z
X
X
H
L
X
3822 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
10
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
|ILI
|ILI
|ILO
Parameter
Input Leakage Current
LBO Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
Max.
Unit
µA
µA
µA
V
___
|
V
V
DD = Max., VIN = 0V to VDD
5
___
___
___
|
DD = Max., VIN = 0V to VDD
30
5
|
CE > VIH or OE > VIH, VOUT = 0V toVDD, VDD = Max.
OL = 5mA, VDD = Min.
OH = -5mA, VDD = Min.
V
OL
OH
I
0.4
___
V
Output High Voltage
I
2.4
V
3822 tbl 20
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application.
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range(1) (VDD = 3.3V +/-5%, VHD = VDD–0.2V, VLD = 0.2V)
S80
S85
S90
S100
Symbol
Parameter
Test Conditions
Com'l Ind Com'l Ind Com'l Ind Com'l Ind Unit
210
45
Operating Power
Supply Current
Device Selected, Outputs Open, ADV/LD = X, 250
260
45
225
40
235
45
225
40
235
45
200
40
mA
mA
I
DD
(2)
V
DD = Max., VIN > VIH or < VIL, f = fMAX
CMOS Standby Power Device Deselected, Outputs Open,
Supply Current
DD = Max., VIN > VHD or < VLD, f = 0(2)
40
100
40
ISB1
V
Clock Running Power Device Deselected, Outputs Open,
Supply Current
110
45
95
105
45
95
105
45
90
100 mA
ISB2
(2)
V
DD = Max., VIN > VHD or < VLD, f = fMAX
Idle Power
Supply Current
Device Selected, Outputs Open, CEN > VIH
40
40
40
45
mA
ISB3
(2)
VDD = Max., VIN > VHD or < VLD, f = fMAX
3822 tbl 21
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
AC Test Loads
AC Test Conditions
Input Pulse Levels
+
1.5V
0 to 3V
50Ω
Input Rise/Fall Times
2ns
1.5V
1.5V
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
I/O
Z0 = 50Ω
,
3822 drw 04
See Figure 1
Figure 1. AC Test Load
3822 tbl 22
6
5
4
3
ΔtCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
.
3822 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
11
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
71V547S80
71V547S85
71V547S90
71V547S100
Min. Max.
Min.
Max.
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
Clock Parameters
____
____
____
____
____
____
____
____
____
____
____
____
t
CYC
Clock Cycle Time
10.5
3
11
3.9
3.9
12
4
15
5
ns
ns
ns
(2)
CH
t
Clock High Pulse Width
Clock Low Pulse Width
(2)
CL
t
3
4
5
Output Parameters
Clock High to Valid Data
____
____
____
____
tCD
8
8.5
9
10
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
t
CDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
2
2
2
2
(3, 4,5)
(3, 4,5)
____
____
____
____
tCL Z
4
4
4
4
____
____
____
____
tCHZ
5
5
5
5
____
____
____
____
t
OE
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
5
5
5
5
(3,4)
____
____
____
____
tOLZ
0
0
0
0
(3.4)
OHZ
____
____
____
____
t
5
5
5
5
Setup Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
SADV
SC
SB
Clock Enable Setup Time
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
t
Address Setup Time
t
Data in Setup Time
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
t
t
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data in Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
ns
3822 tbl 23
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
.
12
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1, 2, 3, 4)
,
13
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
.
14
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
15
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
,
16
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
.
17
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATA Out
Q
Q
.
3822 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
X
71V5477
S
XX
PF
X
Process/
Temperature
Range
Device
Type
Power Speed
Package
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
PF
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
Access time (tCD) in tenths of nanoseconds
80
85
90
100
Blank First generation or current die step
Current generation die step optional
X
PART NUMBER
tCD PARAMETER SPEED IN MEGAHERTZ CLOCK CYCLE TIME
71V547S80PF
71V547S85PF
71V547S90PF
71V547S100PF
8 ns
8.5 ns
9 ns
95 MHz
10.5 ns
11 ns
90 MHz
83 MHz
66 MHz
3822 drw 12
1
2 ns
10 ns
15 ns
18
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
6/15/99
9/13/99
Updatedtonewformat
CorrectedISB3conditions
Pg. 11
Pg. 19
Pp. 3, 11, 12, 18
Pg.18
AddedDatasheetDocumentHistory
AddedIndustrialTemperaturerangeofferings
Added X generation die step to data sheet ordering information
Removed "IDT" from orderable part number
12/31/99
02/27/07
10/16/08
Pg.18
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Rd
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
800-345-7015 or
408/284-4555
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
19
6.42
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