IDT71V65602S100B [IDT]
ZBT SRAM, 256KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119;
| 型号： | IDT71V65602S100B |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 256KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 静态存储器 内存集成电路 |
| 文件： | 总26页 (文件大小：970K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K x 36, 512K x 18
IDT71V65602
IDT71V65802
3.3VSynchronousZBT™SRAMs
2.5V I/O, Burst Counter
PipelinedOutputs
Features
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
The IDT71V65602/5802 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeusedto
disabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
usertodeselectthedevicewhendesired. Ifanyoneofthesethreearenot
assertedwhenADV/LDislow, nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.The
databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.
The IDT71V65602/5802 have an on-chip burst counter. In the burst
mode, the IDT71V65602/5802 can provide four cycles of data for a single
addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined
bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/
LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance
◆
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
ZBT Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
◆
◆
TM
need to control OE
Single R/W (READ/WRITE) control pin
◆
◆
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
2.5V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad and
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
◆
◆
◆
◆
◆
◆
◆
Description
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)
bus cycles when turning the bus around between reads and writes, or and a 165 fine pitch ball grid array (fBGA).
TM
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero
Bus Turnaround.
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE2, CE2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW1, BW2, BW3, BW4
CLK
ADV/LD
Advance burstaddress / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
LBO
ZZ
Asynchronous
Synchronous
Static
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Ground
Supply
Supply
VSS
Static
5303 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
OCTOBER 2004
1
©2004IntegratedDeviceTechnology,Inc.
DSC-5303/05
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge ofclock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD
is sampled high then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is sampled high.
R/W
Read / Write
Clock Enable
I
I
R/W signal is a synchronous input that identifies whether the currentload cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs remain unchanged. The effect of CEN
sampled high on the device outputs is as if the low to high clock transition did not occur.
For normal operation, CEN must be sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if
always doing write to the entire 36-bit word.
BW1-BW4
Chip Enables
LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the
IDT71V65602/5802. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the
rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
CE1, CE2
CE2
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip.
CE2 has inverted polarity but otherwise identical to CE1 and CE2.
CLK
N/A
This is the clock inputto the IDT71V65602/5802. Except for OE, all timing references for the
device are made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
Linear Burst Order
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Linear burst sequence is selected. LBO is a static input and it must
not change during device operation.
LBO
OE
ZZ
Output Enable
Sleep Mode
I
I
LOW Asynchronous output enable. OE must be low to read data from the IDT71V65602/5802.
When OE is high the I/O pins are in a high-impedance state. OE does not need to be
actively controlled for read and write cycles. In normal operation, OE can be tied low.
HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down
71V65602/5802 to the lowestpower consumption level. Data retention is guaranteed in
Sleep Mode.
VDD
VDDQ
VSS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
2.5V I/O Supply.
Ground.
5303 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.422
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
256Kx36 BIT
LBO
MEMORY ARRAY
Address A [0:17]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5303 drw 01a
,
Data I/O [0:31],
I/O P[1:4]
6.42
3
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
512x18 BIT
LBO
MEMORY ARRAY
Address A [0:18]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5303 drw 01
,
Data I/O [0:15],
I/O P[1:2]
RecommendedDCOperating
Conditions
Symbol
VDD
VDDQ
VSS
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
2.375
0
Typ.
Max.
3.465
2.625
0
Unit
V
3.3
2.5
V
0
V
____
VIH
InputHigh Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
1.7
VDD+0.3
VDDQ+0.3
0.7
V
____
____
VIH
1.7
V
(1)
VIL
-0.3
V
5303 tbl 03
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
6.442
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Grade
Ambient
VSS
VDD
VDDQ
Temperature(1)
Commercial
Industrial
0° C to +70° C
0V
0V
3.3V±5%
3.3V±5%
2.5V±5%
-40° C to +85° C
2.5V±5%
5303tbl 05
NOTES:
1. During production testing, the case temperature equals the ambient temperature.
Pin Configuration - 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
79
78
77
3
4
V
DDQ
V
DDQ
5
V
SS
76
75
74
73
V
SS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
SS
V
DDQ
V
DDQ
I/O22
69
68
67
66
65
64
I/O
9
I/O
8
I/O23
(1)
V
DD
V
SS
(1)
V
DD
V
DD
(1)
V
DD
V
DD
V
SS
ZZ
I/O
I/O
63
62
I/O24
I/O25
V
DDQ
7
6
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
V
SS
V
SS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
V
SS
V
SS
V
DDQ
V
DDQ
I/O30
I/O31
I/OP4
I/O
I/O
I/OP1
1
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5303 drw 02
,
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied Low (VSS) or tied High (VDD).
6.42
5
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
Pin Configuration - 512K x 18
Commercial &
Industrial
Symbol
Rating
Unit
(2)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
1
80
79
78
77
NC
NC
NC
DDQ
A10
NC
NC
2
(3,6)
3
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
V
V
4
V
V
DDQ
V
5
SS
76
75
74
73
SS
V
6
NC
NC
NC
I/OP1
(4,6)
7
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
8
8
I/O
I/O
7
I/O
I/O6
SS
9
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
V
V
(5,6)
70
69
68
67
66
65
64
63
62
61
60
59
VTERM
DDQ
Terminal Voltage with
Respect to GND
VDDQ
10
I/O
5
I/O
11
(1)
I/O
DD
4
I/O
V
SS
V
oC
oC
(1)
DD
DD
V
V
Commercial
Industrial
-0 to +70
(7)
(1)
DD
DD
V
V
TA
VSS
I/O12
I/O13
ZZ
I/O3
I/O2
-40 to +85
Te mp e rature
Under Bias
DDQ
DDQ
V
V
TBIAS
TSTG
-55 to +125
-55 to +125
oC
SS
V
SS
V
14
1
I/O
I/O
58
57
56
55
I/O15
I/OP2
NC
0
I/O
Storage
Te mp e rature
NC
NC
VSS
VDDQ
NC
NC
NC
oC
W
SS
V
54
53
52
51
DDQ
NC
NC
NC
V
PT
Power Dissipation
DC Output Current
2.0
50
IOUT
mA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
5303 drw 02a
5303 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied Low (VSS) or tied High (VDD).
7. During production testing, the case temperature equals TA.
100TQFPCapacitance(1)
(TA = +25° C, f = 1.0MHz)
119BGACapacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
5
7
pF
Symbol
CIN
CI/O
pF
7
7
pF
5303 tbl 07
CI/O
pF
165 fBGA Capacitance(1)
5303 tbl 07a
(TA = +25° C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
TBD pF
CI/O
TBD pF
5303 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.462
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K X 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
2
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
B
C
D
E
F
NC(2)
ADV/LD
3
2
9
A
NC
NC
CE
NC
NC
CE2
2
7
A
DD
V
12
A
15
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
19
I/O
12
I/O
DDQ
V
V
V
V
OE
20
I/O
21
I/O
11
I/O
10
I/O
A17
G
H
J
BW
2
3
BW
22
I/O
23
I/O
SS
SS
V
9
I/O
8
I/O
V
V
V
W
R/
DDQ
24
DD
DD
DD
6
DDQ
7
DD(1)
SS
DD(1)
V
V
V
V
V
26
I/O
SS
K
L
I/O
CLK
NC
CEN
V
I/O
I/O
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
BW1
DDQ
29
28
I/O
SS
V
SS
V
3
I/O
DDQ
V
M
N
P
R
T
30
I/O
SS
V
1
A
SS
V
2
I/O
1
I/O
I/O
0
I/O
P1
I/O
31
P4
I/O
SS
V
0
A
SS
V
I/O
NC
5
A
DD
VDD(1)
14
13
V
A
A
NC
ZZ
LBO
10
11
NC
NC
A
A
NC
DNU
(3)
(3)
(3)
(3)
(3)
DDQ
DDQ
V
DNU
DNU
DNU
DNU
U
V
,
5303 drw 13A
Top View
Pin Configuration - 512K X 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(2)
3
2
9
NC
NC
CE
NC
NC
NC
2
CE
ADV/
LD
2
7
A
DD
V
13
17
A
A
8
SS
SS
SS
SS
SS
SS
SS
P1
I/O
I/O
NC
NC
V
V
V
NC
V
V
V
V
9
7
I/O
I/O
NC
NC
CE1
DDQ
V
6
I/O
DDQ
V
OE
10
5
I/O
NC
I/O
NC
NC
G
H
J
A18
BW2
11
I/O
SS
SS
4
I/O
V
V
V
V
NC
R/
W
DD(1)
DD(1)
DDQ
V
DD
DD
V
DD
DDQ
V
V
V
V
V
12
SS
SS
3
I/O
NC
I/O
NC
CLK
NC
NC
K
L
13
I/O
SS
2
I/O
V
V
V
V
NC
BW1
DDQ
V
14
I/O
SS
SS
SS
SS
SS
SS
DDQ
V
V
V
V
NC
M
N
P
R
T
CEN
15
1
0
1
I/O
I/O
NC
NC
A
NC
P2
I/O
0
I/O
A
NC
5
A
DD
V
12
11
NC
NC
V
A
NC
ZZ
DD(1)
LBO
10
15
14
A
A
NC
A
A
(3)
(3)
(3)
(3)
(3)
DDQ
V
DDQ
V
DNU
DNU
DNU
DNU
DNU
U
5303 drw 13B
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A4 is reserved for future 16M.
3. DNU = Do not use. Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. The current die revision allows
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
7
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K X 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(2)
A
B
C
D
E
F
NC
A
ADV/LD
OE
A
A
8
NC
7
17
CE
BW
BW
CE
2
CEN
R/W
1
3
2
(2)
NC
A
6
CE
2
CLK
NC(2)
A
9
NC
BW
BW
1
4
I/O
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
I/O
I/O
P2
P3
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
14
17
16
15
I/O
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
19
I/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
11
I/O
10
G
H
J
I/O23
I/O
V
V
V
V
V
V
V
I/O
I/O
8
22
DDQ
DD
SS
SS
SS
DD
DDQ
9
(1)
(1)
V
V
DD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
I/O
ZZ
I/O
DD
I/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
7
6
K
L
M
N
P
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
4
27
26
DDQ
DD
SS
SS
SS
DD
DDQ
5
I/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
I/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
(3)
(1)
I/O
P4
NC
V
DDQ
V
SS
DNU
NC
V
DD
V
SS
V
DDQ
NC
I/O
P1
(3)
(3)
NC
LBO
NC(2)
NC(2)
A
5
A
DNU
A
1
DNU
A
10
A
A
14
NC
2
13
(3)
(3)
R
A
4
A
DNU
A
0
DNU
A
A
A
15
A
16
3
11
12
5303 tbl 25a
Pin Configuration - 512K X 18, 165 fBGA
1
2
3
4
5
6
7
CEN
R/W
8
9
10
11
(2)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
7
NC
ADV/LD
OE
A
18
A
8
A
10
CE
BW
CE
2
1
2
(2)
(2)
A
6
CE
NC
CLK
NC
A
9
NC
2
BW
1
NC
I/O
V
V
SS
V
SS
V
SS
V
SS
V
SS
V
NC
NC
NC
NC
NC
NC
I/O
P1
DDQ
DDQ
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
7
8
DDQ
DDQ
I/O
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
6
9
DDQ
DDQ
I/O
10
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
5
DDQ
DDQ
G
H
J
I/O
11
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
4
DDQ
DDQ
(1)
(1)
V
V
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZZ
NC
NC
NC
NC
NC
NC
DD
DD
I/O
12
NC
NC
NC
NC
NC
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
3
DDQ
DDQ
K
L
M
N
P
I/O
13
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
2
DDQ
DDQ
I/O
14
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
1
DDQ
DDQ
I/O
15
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
0
DDQ
DDQ
(3)
(1)
I/O
P2
V
V
SS
DNU
NC
V
V
SS
V
DDQ
NC
DDQ
DD
(2)
(3)
(3)
NC
LBO
NC
A
5
A
2
DNU
A
1
DNU
A
11
A
14
A
15
(2)
(3)
(3)
R
NC
A
4
A
3
DNU
A
0
DNU
A12
A
13
A
16
A
17
5303 tbl25b
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. B9, B11, A1, R2 and P2 is reserved for future 18M, 36M, 72M, 144M and 288M, respectively.
3. DNU=Do not use. Pins P5, R5, P7, R7 and N5 are reserved for respective JTAG pins: TDI, TMS, TDO, TCK and TRST on future revisions. The current die
revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.482
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
R/W
Chip(5 )
Enable
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
(2 cycles later)
(7 )
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D
(7 )
Q
(7 )
Valid
LOAD WRITE /
BURST WRITE
BURST WRITE
D
(Advance burst counter)(2 )
(7 )
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(Advance burst counter)(2 )
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3 )
NOOP
HiZ
HiZ
X
X
DESELECT / NOOP
X
(4 )
SUSPEND
Previous Value
5303 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3)
OPERATION
R/W
H
L
BW1
X
BW2
X
BW3
BW4
READ
X
L
X
L
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/OP1)
L
L
(2)
L
L
H
H
H
L
H
H
H
L
(2)
P2
WRITE BYTE 2 (I/O[8:15], I/O )
L
H
L
(2,3)
WRITE BYTE 3 (I/O[16:23], I/OP3)
L
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)
NO WRITE
L
H
H
H
H
L
H
H
H
5303 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
9
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5303 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5303 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A17)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:31], I/O P[1:4]
5303 drw 03
,
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.1402
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
CE(1 )
Cycle
Address
R/W
ADV/LD
I/O
Comments
Load read
Burst read
Load read
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWx
X
X
X
X
X
X
X
X
L
OE
X
X
L
n
A0
X
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
X
n+1
X
L
X
n+2
A1
X
Q0
n+3
H
X
L
L
Q0+1 Deselect or STOP
n+4
X
L
Q1
Z
NOOP
n+5
A2
X
X
X
L
Load read
Burst read
Deselect or STOP
n+6
X
H
L
Z
n+7
X
Q2
n+8
A3
X
L
Q2+1 Load write
n+9
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
Load write
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A4
X
L
D3
X
X
L
H
X
L
X
X
L
D3+1 Deselect or STOP
X
D4
Z
NOOP
A5
A6
A7
X
Load write
Load read
Load write
Burst write
Load read
Burst read
Load write
H
L
L
X
L
Z
L
D5
Q6
D7
X
H
X
L
X
L
L
A8
X
X
X
L
X
X
L
X
L
D
7+1
A9
Q8
5303 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
ReadOperation(1)
CE(2 )
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
n
A0
X
X
H
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
L
X
X
X
X
X
L
Q0
Contents of Address A0 Read Out
5303 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation(1)
CE(2 )
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
X
L
n
A0
X
X
X
X
A1
X
X
A2
H
X
X
X
X
H
X
X
H
L
H
H
H
H
L
X
X
Address and Control meet setup
Clock Setup Valid, Advance Counter
Address A0 Read Out, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
L
X
X
L
X
Q0
X
L
X
L
Q0+1 Address A0+1 Read Out, Inc. Count
X
L
X
L
Q0+2
Q0+3
Q0
Address A0+2 Read Out, Inc. Count
Address A0+3 Read Out, Load A1
Address A0 Read Out, Inc. Count
Address A1 Read Out, Inc. Count
L
L
X
L
H
H
L
X
L
X
L
X
L
X
L
Q1
L
L
X
L
Q1+1 Address A1+1 Read Out, Load A2
5303 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
CE(2 )
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
n
A0
X
X
L
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
L
X
X
X
L
X
X
D0
Write to Address A0
5303 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
CE(2 )
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
X
X
X
X
X
X
X
X
n
A0
X
L
X
X
X
X
L
L
H
H
H
H
L
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
Address A0 Write, Inc. Count
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
Address A0+3 Write, Load A1
Address A0 Write, Inc. Count
Address A1 Write, Inc. Count
Address A1+1 Write, Load A2
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
L
L
X
X
L
L
D0
X
X
L
L
D0+1
D0+2
D0+3
D0
X
X
L
L
A1
X
L
L
L
X
X
L
H
H
L
X
L
L
X
X
L
L
D1
A2
L
L
L
D1+1
5303 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1422
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
CE(2 )
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
L
n
A0
X
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
L
H
L
X
A1
X
X
X
Clock Valid
X
X
L
H
H
L
X
Q0
Q0
Q0
Q1
Q2
Clock Ignored, Data Q0 is on the bus.
Clock Ignored, Data Q0 is on the bus.
Address A0 Read out (bus trans.)
Address A1 Read out (bus trans.)
X
X
L
A2
A3
A4
X
L
L
L
X
L
L
L
X
L
Address A2 Read out (bus trans.)
5303 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
CE(2 )
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
X
X
X
X
X
n
A0
X
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
L
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
L
H
L
X
L
A1
X
X
X
X
L
H
H
L
X
X
L
X
Clock Ignored.
X
X
Clock Ignored.
A2
A3
A4
D0
D1
D2
Write Data D0
L
L
L
Write Data D1
L
L
L
Write Data D2
5303 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
(3 )
CE(2 )
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
X
X
X
X
L
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
X
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
L
X
?
Deselected.
A0
X
L
X
Z
Z
Address and Control meet setup
Deselected or STOP.
H
L
L
X
A1
X
L
X
Q0
Z
Address A0 Read out. Load A1.
Deselected or STOP.
H
H
L
L
X
X
L
X
L
X
Q1
Z
Address A1 Read out. Deselected.
Address and control meet setup.
Deselected or STOP.
A2
X
L
X
X
X
L
H
H
L
X
Z
X
L
X
Q2
Address A2 Read out. Deselected.
5303 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
(3 )
CE(2 )
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
Deselected.
A0
X
Z
Address and Control meet setup
Deselected or STOP.
Address D0 Write in. Load A1.
Deselected or STOP.
X
L
H
L
X
L
Z
A1
X
D0
Z
X
X
L
H
H
L
X
X
L
X
D
1
Address D Write in. Deselected.
1
A2
X
Z
Z
Address and control meet setup.
Deselected or STOP.
X
X
H
H
X
X
X
D2
Address D2 Write in. Deselected.
5303 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1442
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1 )
___
___
___
LBO Input Leakage Current
|ILI|
VDD = Max., VIN = 0V to VDD
VOUT = 0V to VDDQ, Device Deselected
IOL = +6mA, VDD = Min.
30
5
µA
µA
V
|ILO|
VOL
VOH
Output Leakage Current
Output Low Voltage
Output High Voltage
0.4
___
IOH = -6mA, VDD = Min.
2.0
V
NOTE:
5303 tbl 21
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to Vss if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V +/-5%)
150MHz
133MHz
100MHz
Unit
Symbol
Parameter
Test Conditions
Com'l
Ind
Com'l
Ind
Com'l
Ind
I
DD
De vice Se le cte d, Outputs Ope n,
Ope rating Powe r
Supply Current
ADV/LD = X, VDD = Max.,
325
40
345
300
40
320
250
40
270
mA
mA
mA
mA
(2 )
IN
V
IH
IL
MAX
> V or < V , f = f
De vice De se le cte d, Outputs Open,
DD = Max., VIN > VHD or < VLD
f = 0(2,3)
I
S B1
CMOS Standby Powe r
Supply Current
V
,
60
60
60
I
S B2
De vice De se le cte d, Outputs Open,
Clock Running Powe r
Supply Current
V
DD = Max., VIN > VHD or < VLD,
120
40
140
60
110
40
130
60
100
40
120
60
(2.3)
f = fMAX
I
S B3
De vice Se le cte d, Outputs Ope n,
Idle Powe r
Supply Current
CEN > VIH , VDD = Max.,
(2,3)
V IN > VHD or < VLD, f = fMAX
De vice Se le cte d, Outputs Ope n,
Full Sle e p Mode
Supply Current
Izz
CEN
≤
V
IL, VDD = Max., ZZ
≥
V
HD
40
60
40
60
40
60
mA
V
IN
≥
VHD or
≤
V
LD, f = fMAX(2, 3)
5303 tb l 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Conditions
(VDDQ = 2.5V)
AC Test Load
VDDQ/2
50Ω
Input Pulse Levels
0
2.5V
to
I/O
Z0 = 50Ω
,
6
5
4
3
5303 drw 04
Input Rise/Fall Times
2ns
Figure 1. AC Test Load
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
V
/2
DDQ
•
V
/2
DDQ
tCD
∆
See Figure 1
(Typical, ns)
2
•
5303 tbl 23
•
1
•
•
20 30 50
80 100
Capacitance (pF)
200
5303 drw 05
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
150MHz
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
tCY C
Clock Cycle Time
6.7
7.5
10
ns
MHz
ns
(1)
____
____
____
Clock Frequency
150
133
100
tF
(2)
____
____
____
Clock High Pulse Width
Clock Low Pulse Width
2.0
2.0
2.2
2.2
3.2
3.2
tCH
(2)
____
____
____
ns
tCL
Output Parameters
____
____
____
tCD
Clock High to Valid Data
3.8
4.2
5
ns
ns
ns
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
1.5
1.5
1.5
1.5
1.5
1.5
____
____
____
(3,4,5)
tCL Z
(3,4,5)
1.5
3
1.5
3
1.5
3.3
ns
ns
ns
ns
tCHZ
____
____
____
tOE
3.8
4.2
5
____
____
____
(3,4)
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
0
tOLZ
____
____
____
(3,4)
3.8
4.2
5
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSE
Clock Enable Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
tSA
Address Setup Time
tSD
Data In Setup Time
tSW
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
tSADV
tSC
tSB
Hold Times
tHE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tHA
Address Hold Time
tHD
Data In Hold Time
tHW
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
tHADV
tHC
tHB
ns
NOTES:
5303 tbl 24
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.1462
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
6.42
17
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
.
6.1482
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
,
6.42
19
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
6.2402
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
6.42
21
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.2422
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
23
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.2442
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
,
5303 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
IDT
XXXX
S
XX
XX
X
Process/
Temperature Range
Device
Type
Power Speed
Package
Blank
I
Commercial (0° C to +70° C)
Industrial (-40° C to +85° C)
PF
BG
BQ
100 pin Plastic Thin Quad Flatpack, 100 pin
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
150
133
100
Clock Frequency in Megahertz
256Kx36 Pipelined ZBT SRAM
IDT71V65602
IDT71V65802 512Kx18 Pipelined ZBT SRAM
5303 drw 12
6.42
25
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
03/04/00
04/20/00
Creatednewdatasheetfromobsoletedevices IDT71V656andIDT71V658
Pg.1,14,15 Removed166MHzspeedgrade offering;Added150MHzspeedgrade offering
Pg. 5,6
AddJTAGtestpinstoTQFPpinconfiguration;removedfootnote
AddclarificationnotetoRecommendedOperatingTemperatureandAbsoluteMaxRatingstables
AddnotetoBGAPinconfiguration;correctedtypoinpinout
InsertTQFPPackageDiagramOutline
Pg. 7
Pg. 21
05/16/00
07/28/00
Addnewpackageoffering,13x15mm165fBGA
Pg. 23
Pg. 5-8
Correcterrorinthe 119BGAPackage DiagramOutline
Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and IDT71V658xx
device errata
Pg. 7,8
Pg. 23
Pg. 15
Pg. 8
Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout
UpdateBG119PackageDiagramDimensions
AddIzzparametertoDCElectricalCharacteristics
Add note to pin N5 on the BQ165 pinout, reserved for JTAG TRST
ChangeddatasheetfromPreliminarytoFinalRelease.
11/04/00
12/04/02
Pg. 1-26
Pg. 5,6,15, AddedItemptodatasheet.
16,25
12/19/02
10/15/04
Pg. 1,2,5,6, RemovedJTAGfunctionalityforcurrentdierevision.
7,8
Pg. 7
Pg. 5,6
Pg. 7
Correctedx36,119BGApinconfiguration. SwitchedpinsI/O0andI/OP1.
UpdatedtemperatureTanote.
Updated pin configuration 512K x 18 for the 119 BGA - reordered I/O signals on P7, N6, L6, K7, H6, G7,
F6, E7, D6.
.
CORPORATE HEADQUARTERS
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San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
sramhelp@idt.com
800-345-7015 or
408/284-4555
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.2462
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