IDT71V65602S166PF [IDT]
ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100;
| 型号： | IDT71V65602S166PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K x 36, 512K x 18
Preliminary
IDT71V65602
IDT71V65802
3.3VSynchronousZBT™SRAMs
2.5V I/O, Burst Counter
PipelinedOutputs
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
TheIDT71V65602/5802containdataI/O,addressandcontrolsignal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
AClockEnable(CEN)pinallowsoperationoftheIDT71V65602/5802
to be suspended as long as necessary. All synchronous inputs are
ignoredwhen(CEN)ishighandtheinternaldeviceregisterswillholdtheir
previous values.
Features
◆
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 166MHz(3.5ns
Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
◆
◆
Internally synchronized output buffer enable eliminates
the need to control OE
◆
Single R/W (READ/WRITE) control pin
◆
Positive clock-edge triggered address, data, and control
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three are
not asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselectedor
awriteisinitiated.
TheIDT71V65602/5802haveanon-chipburstcounter.Intheburst
mode,theIDT71V65602/5802canprovidefourcyclesofdataforasingle
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter
(ADV/LD = HIGH).
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-
leadthinplasticquadflatpack(TQFP)aswellasa119-leadballgridarray(BGA).
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
2.5V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-lead plastic thin quad
◆
◆
◆
◆
◆
◆
◆
Description
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead
bus cycles when turning the bus around between reads and writes, or
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero
Bus Turnaround.
TM
PinDescriptionSummary
A
0
-A18
Addres s Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
I/O
Synchronous
Synchronous
As ynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE
1
, CE
2
,
CE
2
Output Enable
OE
R/
W
Re ad/Write Signal
Clock Enable
CEN
BW
Individual Byte Write Se le cts
Clock
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
TMS
TDI
Advance burst addres s / Load new addre ss
Line ar / Inte rle ave d Burs t Orde r
Te st Mode Se lect
Te st Data Input
Synchronous
Static
N/A
N/A
TCK
TDO
ZZ
Te s t Clo c k
N/A
Te s t Data O utp ut
Slee p Mode
N/A
As ynchronous
Synchronous
Static
I/O
0
-I/O31, I/OP1-I/OP4
Data Input / Outp ut
Core Powe r, I/O Powe r
Ground
VDD, VDDQ
Supply
Supply
V
SS
Static
5303 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
DECEMBER 1999
1
©1999IntegratedDeviceTechnology,Inc.
DSC-5303/00
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD
is sampled high then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is sampled high.
R/W
Read / Write
Clock Enable
I
I
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs remain unchanged. The effect of CEN
sampled high on the device outputs is as if the low to high clock transition did not occur.
For normal operation, CEN must be sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.
BW1-BW
4
On load write cycles (When R/
signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/ is sampled high. The appropriate
W and ADV/LD are sampled low) the appropriate byte write
W
byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if
always doing write to the entire 36-bit word.
Chip Enables
LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the
IDT71V65602/5802. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the
rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
CE1, CE
2
CE2
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip.
CE2 has inverted polarity but otherwise identical to CE1 and CE2.
CLK
N/A
This is the clock input to the IDT71V65602/5802. Except for OE, all timing references for the
device are made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
Linear Burst Order
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Linear burst sequence is selected. LBO is a static input and it must
not change during device operation.
LBO
OE
Output Enable
I
LOW Asynchronous output enable. OE must be low to read data from the IDT71V65602/5802.
When OE is high the I/O pins are in a high-impedance state. OE does not need to be
actively controlled for read and write cycles. In normal operation, OE can be tied low.
TMS
TDI
Test Mode Select
Test Data Input
Test Clock
I
I
N/A
N/A
N/A
Gives input command for TAP controller; sampled on rising edge of TCK.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK.
TCK
O
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising
edge of TCK, while test outputs are driven from falling edge of TCK.
TDO
ZZ
Test Data Input
Sleep Mode
O
I
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on
state of TAP controller.
HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down
71V65602/5802 to the lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
VDD
VDDQ
VSS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
2.5V I/O Supply.
Ground.
5303 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.42
2
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
FunctionalBlockDiagram
256Kx36 BIT
LBO
MEMORY ARRAY
Address A [0:17]
D
D
Q
Q
Address
CE1, CE2, CE
R/
2
W
Control
CEN
ADV/LD
DI
DO
BW
x
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5303 drw 01a
,
Data I/O [0:31],
I/O P[1:4]
6.42
3
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
FunctionalBlockDiagram
512x18 BIT
LBO
MEMORY ARRAY
Address A [0:18]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5303 drw 01
,
Data I/O [0:15],
I/O P[1:2]
RecommendedDCOperating
Conditions
Symbol
VDD
VDDQ
VSS
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
2.375
0
Typ.
Max.
3.465
2.625
0
Unit
V
3.3
2.5
V
0
V
____
VIH
Input High Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
1.7
VDD+0.3
VDDQ+0.3
0.7
V
____
____
VIH
1.7
V
VIL
-0.3(1)
V
5303 tbl 03
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
6.42
4
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
SS
V
DD
V
DDQ
V
Grade
Temperature
Commercial
0° C to +70° C
0V
3.3V±5%
2.5V±5%
5303tbl 05
Pin Configuration - 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
79
78
77
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
VDDQ
VDDQ
69
68
67
66
65
64
I/O22
I/O9
I/O8
I/O23
(1)
VDD
V
SS
(1)
V
DD
DD
VDD
(1)
V
VDD
VSS
ZZ
I/O
I/O
63
62
I/O24
I/O25
7
6
61
60
59
58
57
56
55
VDDQ
V
V
DDQ
SS
V
SS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
54
53
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
I/OP1
1
52
51
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5303 drw 02
,
Top View
TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU = Do not use
6.42
5
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
Pin Configuration - 512K x 18
Symbol
Rating
Commercial
Unit
(2)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
(3,6)
1
VTERM
Terminal Voltage with
Respect to GND
-0.5 to V
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
DD
80
79
78
77
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VDD
VDD
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
2
3
4
(4,6)
VTERM
Terminal Voltage with
Respect to GND
5
76
75
74
73
6
7
8
(5,6)
VTERM
Terminal Voltage with
Respect to GND
V
9
72
71
10
11
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
12
oC
oC
oC
W
TA
13
Operating Temperature
(1)
14
(1)
15
VDD
(1)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
VDD
ZZ
Temperature
Under Bias
-55 to +125
TBIAS
TSTG
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
Storage
Temperature
-55 to +125
PT
Power Dissipation
DC Output Current
2.0
50
NC
VSS
VDDQ
NC
NC
NC
IOUT
mA
5303 tbl 06
NOTES:
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
,
5303 drw 02a
Top View
TQFP
3. VDDQ terminals only.
4. Input terminals only.
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
3. DNU = Do not use
Capacitance
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
Max. Unit
CIN
VIN = 3dV
5
7
pF
C
I/O
VOUT = 3dV
pF
5303 tbl 07
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
6
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Pin Configuration - 256K X 36 BGA(1,2,3)
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
NC(2)
ADV/LD
A
A
A
2
3
2
9
CE
NC
NC
16
NC
NC
2
CE
7
DD
V
12
15
A
A
A
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
20
19
I/O
12
I/O
DDQ
10
V
V
OE
21
I/O
11
I/O
G
H
J
I/O
A17
I/O
2
BW
3
BW
22
I/O
23
I/O
SS
DD(1)
SS
4
SS
V
9
I/O
8
I/O
V
V
V
R/
W
DDQ
V
DD
DD
DD
DDQ
V
DD(1)
V
V
V
V
V
24
I/O
26
I/O
SS
6
I/O
7
I/O
K
L
CLK
NC
CEN
25
I/O
27
I/O
4
I/O
5
I/O
1
BW
BW
DDQ
V
28
I/O
SS
V
SS
SS
SS
3
I/O
DDQ
1
M
N
P
R
T
V
V
V
V
29
I/O
30
I/O
SS
V
1
2
I/O
A
I/O
31
I/O
P4
I/O
SS
V
0
0
I/O
P1
I/O
A
(3)
5
DD
V
DD(1)
V
13
DNU
ZZ
NC
A
A
LBO
10
A
11
A
14
A
NC
NC
TMS
NC
NC
DDQ
V
DDQ
V
U
TDI
TCK
TDO
,
5303 drw 13A
Top View
Pin Configuration - 512K X 18 BGA(1,2,3)
1
2
3
4
5
6
7
DDQ
6
4
8
9
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(2)
3
2
NC
NC
CE2
NC
NC
NC
2
CE
ADV/LD
7
DD
V
13
17
A
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
V
V
V
V
9
6
I/O
NC
DDQ
I/O
NC
1
CE
NC
5
I/O
DDQ
V
V
OE
10
I/O
4
I/O
NC
NC
G
H
J
A18
BW2
11
I/O
SS
SS
3
I/O
NC
DD
V
V
V
V
NC
R/W
DD(1)
SS
DD(1)
DDQ
V
DD
V
DD
DDQ
V
V
V
V
12
SS
2
I/O
NC
I/O
NC
CLK
NC
V
NC
K
L
13
I/O
SS
1
I/O
V
V
V
V
NC
1
BW
DDQ
V
14
I/O
SS
SS
SS
SS
SS
SS
DDQ
V
V
V
V
NC
M
N
P
R
T
CEN
15
1
0
I/O
I/O
NC
NC
A
A
NC
P2
I/O
0
P1
I/O
NC
(3)
5
DD
V
12
11
NC
NC
A
VDD(1)
14
A
DNU
LBO
10
15
A
A
NC
A
A
ZZ
DDQ
V
DDQ
V
TMS
TDI
TCK
TDO
NC
U
5303 drw 13B
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A4 is reserved for future 16M.
3. DNU = Do not use
6.42
7
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
SynchronousTruthTable(1)
R/W
Chip(5)
Enable
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
(2 cycles later)
(7)
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
BURST WRITE
D
(7)
Q
(7)
Valid
LOAD WRITE /
BURST WRITE
D
(2)
(Advance burst counter)
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(2)
(Advance burst counter)
DESELECT or STOP(3)
NOOP
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
HiZ
HiZ
X
X
DESELECT / NOOP
X
(4)
SUSPEND
Previous Value
5303 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3)
OPERATION
R/W
BW
X
1
BW
X
2
BW
3
BW
4
READ
H
X
X
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/OP 1
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
H
L
(2)
)
L
H
(2)
P 2
WRITE BYTE 2 (I/O[8:15], I/O
WRITE BYTE 3 (I/O[16:23], I/OP 3
WRITE BYTE 4 (I/O[24:31], I/OP 4
NO WRITE
)
H
L
(2,3)
)
H
H
(2,3)
)
H
H
H
H
H
H
H
5303 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
8
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
Second Address
Third Address
1
0
1
1
0
0
1
0
0
1
Fourth Address(1)
1
0
0
1
0
5303 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5303 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A17)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:31], I/O P[1:4]
5303 drw 03
,
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
9
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
DeselectandNOOPCycles(2)
CE(1)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWx
X
X
X
X
X
X
X
X
L
OE
X
X
L
0
A
n
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
X
X
Load read
Burst read
Load read
n+1
X
X
L
1
A
0
Q
n+2
0+1
Q
n+3
X
X
H
X
L
L
Deselect or STOP
NOOP
1
Q
n+4
L
2
A
n+5
X
X
L
Z
Z
Load read
Burst read
Deselect or STOP
Load write
n+6
X
X
X
H
L
2
Q
n+7
3
A
2+1
Q
n+8
L
n+9
X
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
4
A
3
D
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
L
Load write
3+1
D
X
X
X
X
L
H
X
L
X
X
L
Deselect or STOP
NOOP
4
D
5
A
Z
Z
Load write
6
A
H
L
L
X
L
Load read
Load write
7
A
5
D
L
6
Q
X
X
H
X
L
X
L
L
Burst write
8
A
7
D
X
X
L
X
X
L
Load read
Burst read
Load write
7+1
D
X
X
L
9
A
8
Q
5303 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
ReadOperation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
0
A
n
H
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
L
X
X
0
Q
0
X
X
X
L
Contents of Address A Read Out
5303 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
10
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Burst Read Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
X
L
0
A
n
H
X
X
X
X
H
X
X
H
L
H
H
H
H
L
X
X
Address and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
L
X
Clock Setup Valid, Advance Counter
0
Q
0
X
L
X
Address A Read Out, Inc. Count
0+1
Q
0+1
X
L
X
L
Address A Read Out, Inc. Count
0+2
Q
0+2
X
L
X
L
Address A Read Out, Inc. Count
1
A
0+3
Q
0+3
1
L
L
X
L
Address A Read Out, Load A
0
Q
0
X
X
H
H
L
X
L
X
L
Address A Read Out, Inc. Count
1
Q
1
X
L
X
L
Address A Read Out, Inc. Count
2
A
1+1
Q
1+1
2
L
L
X
L
Address A Read Out, Load A
5303 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
0
A
n
L
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
L
X
X
0
D
0
X
L
X
X
Write to Address A
5303 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
X
X
X
X
X
X
X
X
0
A
n
L
X
X
X
X
L
L
H
H
H
H
L
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
L
L
0
D
0
X
L
L
Address A Write, Inc. Count
0+1
D
0+1
X
L
L
Address A Write, Inc. Count
0+2
D
0+2
X
L
L
Address A Write, Inc. Count
1
A
0+3
D
0+3
1
L
L
L
Address A Write, Load A
0
D
0
X
X
X
X
L
H
H
L
X
L
L
Address A Write, Inc. Count
1
D
1
X
L
L
Address A Write, Inc. Count
2
A
1+1
D
1+1
2
L
L
L
Address A Write, Load A
5303 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Read Operation with Clock Enable Used(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
L
0
A
n
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
X
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
H
L
X
1
A
X
Clock Valid
0
Q
0
X
X
X
X
L
H
H
L
X
Clock Ignored, Data Q is on the bus.
0
Q
0
X
L
Clock Ignored, Data Q is on the bus.
2
A
0
Q
0
X
L
Address A Read out (bus trans.)
3
A
1
Q
1
L
L
X
L
Address A Read out (bus trans.)
4
A
2
Q
L
L
X
L
Address A2 Read out (bus trans.)
5303 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
X
X
X
X
X
0
A
n
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
L
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
H
L
X
L
1
A
X
X
X
X
L
H
H
L
X
X
L
Clock Ignored.
Clock Ignored.
2
A
0
D
0
Write Data D
3
A
1
D
1
L
L
L
Write Data D
4
A
2
D
2
L
L
L
Write Data D
5303 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
12
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Read Operation with Chip Enable Used(1)
(3)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
0
A
Z
Z
Address and Control meet setup
Deselected or STOP.
X
H
L
1
A
0
Q
0
1
Address A Read out. Load A .
X
X
H
H
L
X
L
Z
Deselected or STOP.
1
1
Q
Z
Z
Address A Read out. Deselected.
2
A
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
2
Q
2
Address A Read out. Deselected.
5303 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
(3)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
Deselected.
0
A
Z
Z
Address and Control meet setup
Deselected or STOP.
X
X
L
H
L
X
L
1
A
0
D
0
1
Address D Write in. Load A .
X
X
X
X
L
H
H
L
X
X
L
Z
Deselected or STOP.
1
1
D
Z
Z
Address D Write in. Deselected.
2
A
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
H
X
X
2
D
2
Address D Write in. Deselected.
5303 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
LI
|I |
DD
V
IN
DD
Input Leakage Current
= Max., V = 0V to V
5
µA
(1)
___
___
___
LBO Input Leakage Current
LI
DD
IN
DD
|I |
V
= Max., V = 0V to V
30
5
µA
µA
V
LO
|I |
OUT
V
DDQ
Output Leakage Current
Output Low Voltage
Output High Voltage
= 0V to V , Device Deselected
OL
V
OL
DD
I
= +6mA, V = Min.
0.4
___
OH
V
OH
DD
I
= -6mA, V = Min.
2.0
V
5303 tbl 21
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to Vss if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
166MHz
133MHz
100MHz
Unit
DD
I
Device Selected, Outputs Open,
Operating Power
Supply Current
350
300
250
mA
DD
ADV/LD = X, V = Max.,
(2)
IN
IH
IL
MAX
V > V or < V , f = f
SB1
Device Deselected, Outputs Open,
I
CMOS Standby Power
Supply Current
40
120
40
40
110
40
40
100
40
mA
mA
DD
IN
HD
LD
V
= Max., V > V or < V ,
(2,3)
f = 0
SB2
I
Device Deselected, Outputs Open,
Clock Running Power
Supply Current
DD
IN
HD
LD
V
= Max., V > V or < V ,
(2.3)
MAX
f = f
SB3
I
Device Selected, Outputs Open,
Idle Power
Supply Current
mA
IH DD
CEN > V , V = Max.,
(2,3)
IN
HD
LD
MAX
V > V or < V , f = f
5303 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Conditions
(VDDQ = 2.5V)
VDDQ/2
AC Test Load
50Ω
Input Pulse Levels
0 to 2.5V
I/O
Z0 = 50Ω
6
5
4
,
Input Rise/Fall Times
2ns
5303 drw 04
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
VDDQ/2
VDDQ/2
Figure 1. AC Test Load
•
3
∆tCD
(Typical, ns)
See Figure 1
2
•
5303 tbl 23
•
1
•
•
20 30 50
80 100
Capacitance (pF)
200
5303 drw 05
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
14
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, TA = 0 to 70° C)
166MHz
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
t
CYC
Clock Cycle Time
6
7.5
10
ns
MHz
ns
____
____
____
(1 )
Clock Fre que ncy
166
133
100
t
F
____
____
____
(2 )
CH
Clock High Pulse Width
Clock Low Pulse Width
1.8
1.8
2.2
2.2
3.2
3.2
t
____
____
____
(2 )
CL
ns
t
Output Parameters
____
____
____
t
CD
Cloc k High to Valid Data
3.5
4.2
5
ns
ns
ns
____
____
____
t
CDC
Clock High to Data Change
1.5
1.5
1.5
1.5
1.5
1.5
____
____
____
(3 , 4,5 )
CLZ
Clock High to Output Active
t
(3 , 4,5 )
CHZ
Clock High to Data High-Z
1.5
3
1.5
3
1.5
3.3
ns
ns
ns
t
____
____
____
t
OE
Output Enable Acce s s Time
Output Enable Low to Data Active
3.5
4.2
5
____
____
____
(3,4)
OLZ
0
0
0
t
____
____
____
(3,4)
OHZ
O utp ut Enab le Hig h to Data Hig h-Z
3.5
4.2
5
ns
t
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
Clock Enable Se tup Time
Addre s s Se tup Time
Data In Se tup Tim e
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
SA
t
t
SD
SW
SADV
SC
t
Re ad/Write (R/W) Se tup Time
t
Advance /Load (ADV/LD) Se tup Time
Chip Enable /Se le ct Se tup Time
t
t
SB
Byte Write Enable (BWx) Se tup Time
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
Addre ss Hold Time
Data In Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
t
t
W
Re ad/Write (R/ ) Hold Time
t
Advance /Load (ADV/LD) Hold Time
Chip Enable /Se le ct Hold Time
t
t
Byte Write Enable (BWx) Hold Time
ns
5303 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.42
15
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
6.42
16
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
.
6.42
17
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
,
6.42
18
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
6.42
19
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
6.42
20
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
119- lead Ball Grid Array(BGA) Package Diagram Outline
6.42
21
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
,
5303 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
IDT
XXXX
S
XX
XX
Device
Type
Power Speed
Package
Plastic Thin Quad Flatpack, 100 pin
119-lead Ball Grid Array (BGA)
PF
BG
166
133
100
Clock Frequency in Megahertz
256Kx36 Pipelined ZBT SRAM
IDT71V65602
IDT71V65802 512Kx18 Pipelined ZBT SRAM
5303 drw 12
6.42
22
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
DatasheetDocumentHistory
7/26/99
8/23/99
Updatedtonewformat
AddedSmartZBT™functionality
Pp. 4, 5
Pg. 6
Added Note 4 and changed pins 38, 42, and 43 to DNU
Changed B2 to CE2 and U6 to DNU
Pg. 15
ImprovedtCD andtOE(MAX)at166MHz
Revised tCHZ(MIN) for f ≤ 133 MHz
Revised tOHZ (MAX) for f ≤ 133 MHz
ImprovedtCH, tCL forf ≤166MHz
Improvedsetuptimesfor100–200MHz
AddedDatasheetDocumentHistory
Pg. 24
Pg. 14
Pg. 15
10/4/99
RevisedACElectricalCharacteristicstable
Revised tCHZ to match tCLZ and tCDC at 133MHz and 100MHz
RemovedSmartfunctionalityand200MHzspeedgradeoffering.
Increasedtcdc.tclz,andtchz(min)to1.5ns
Added ZZ, TMS, TCK, TDI, and TDO pin descriptions and definitions.
12/31/99
Pg. 15
Pp. 1,2
Pp. 4, 5, 6, Added ZZ input.
13
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
23
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