IDT71V65703S75BQI [IDT]
256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs; 256K ×36 ， 512K ×18的3.3V同步ZBT SRAM的
| 型号： | IDT71V65703S75BQI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs |
| 文件： | 总26页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K x 36, 512K x 18
IDT71V65703
IDT71V65903
3.3VSynchronousZBT™SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs
cycle,andonthenextclockcycletheassociateddatacycleoccurs,beit
read or write.
TheIDT71V65703/5903containaddress,data-inandcontrolsignal
registers.Theoutputsareflow-through(nooutputdataregister).Output
enable is the only asynchronous signal and can be used to disable the
outputsatanygiventime.
Features
◆
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
◆
cycles
◆
A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen
CENishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.
There are three chip enable pins (CE1, CE2, CE2) that allow the
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite
isinitiated.
TheIDT71V65703/5903haveanon-chipburstcounter.Intheburst
mode,theIDT71V65703/5903canprovidefourcyclesofdataforasingle
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter
(ADV/LD = HIGH).
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V (±5%) I/O Supply (VDDQ)
Power down controlled by ZZ input
◆
◆
◆
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.
They are designed to eliminate dead bus cycles when turning the bus
aroundbetweenreads andwrites,orwrites andreads.Thus theyhave
been given the name ZBTTM, or Zero Bus Turnaround.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
TheIDT71V65703/5903SRAMsutilizeIDT’slatesthigh-performance
CMOSprocessandarepackagedinaJEDECStandard14mmx20mm100-
pinplasticthinquadflatpack(TQFP), 119 ballgridarray(BGA)and a 165
fine pitchballgridarray(fBGA).
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE2, CE2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW1, BW2, BW3, BW4
CLK
ADV/LD
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Sleep Mode
Synchronous
Static
LBO
ZZ
Asynchronous
Synchronous
Static
I/ O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input/Output
Core Power, I/O Power
Ground
Supply
Supply
VSS
Static
5298 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
DECEMBER 2002
1
©2002IntegratedDeviceTechnology,Inc.
DSC-5298/03
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O Active
Description
0
18
A -A
Address Inputs
I
N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of
CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with
the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the
internal burst counter is advanced for any burst that was in progress. The external addresses are
ignored when ADV/LD is sampled high.
R/W
Read / Write
Clock Enable
I
I
N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the current cycle takes place one clock
cycle later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load
1
4
BW -BW
1
4
write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW -BW )
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write
signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the
1
4
device one cycle later. BW -BW can all be tied low if always doing write to the entire 36-bit word.
1
2
2
Chip Enables
LOW Synchronous active low chip enable. CE and CE are used with CE to enable the IDT71V65703/5903
1
2
CE , CE
1
2
2
(CE or CE sampled high or CE sampled low) and ADV/LD low at the rising edge of clock, initiates
a deselect cycle. The ZBT has a one cycle deselect, i.e., the data bus will tri-state one clock cycle
TM
after deselect is initiated.
2
2
1
2
2
CE
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE is used with CE and CE to enable the chip. CE has
1
2
inverted polarity but otherwise identical to CE and CE .
CLK
N/A This is the clock input to the IDT71V65703/5903. Except for OE, all timing references for the device are
made with respect to the rising edge of CLK.
0
31
I/O -I/O
Data Input/Output I/O
N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
P1
I/O -I/O
P4
Linear Burst
Order
I
I
I
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO
is low the Linear burst sequence is selected. LBO is a static input, and it must not change during
device operation.
LBO
Output Enable
Sleep Mode
LOW Asynchronous output enable. OE must be low to read data from the 71V65703/5903. When OE is HIGH
the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and
write cycles. In normal operation, OE can be tied low.
OE
ZZ
HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V65703/5903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
DD
V
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A 3.3V core power supply.
N/A 3.3V I/O supply.
DDQ
V
SS
V
N/A Ground.
5298 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.422
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram 256K x 36
LBO
256K x 36 BIT
MEMORY ARRAY
Address
Address A [0:17]
D
D
Q
Q
CE1, CE2 CE2
R/W
CEN
Control
ADV/LD
DI
DO
BWx
D
Q
Control Logic
Clk
Mux
Sel
Clock
Gate
OE
Data I/O [0:31], I/O P[1:4]
,
5298 drw 01
6.42
3
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram 512K x 18
LBO
512K x 18 BIT
MEMORY ARRAY
Address
Address A [0:18]
D
D
Q
Q
CE1, CE2 CE2
R/W
CEN
Control
ADV/LD
DI
DO
BWx
D
Q
Control Logic
Clk
Mux
Sel
Clock
Gate
OE
Data I/O [0:15], I/O P[1:2]
,
5298 drw 01a
RecommendedDCOperating
Conditions
Symbol
VDD
VDDQ
VSS
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
3.135
3.135
0
Typ.
Max.
Unit
V
3.3
3.465
3.3
3.465
V
0
0
V
____
VIH
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
VDD + 0.3
VDDQ + 0.3
0.8
V
____
____
VIH
2.0
V
VIL
-0.3(1)
V
5298 tbl 04
NOTE:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
6.442
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
V
SS
DD
DDQ
V
Grade
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
5298 tbl 05
NOTES:
1. TA is the “instant on” case temperature.
Pin Configuration 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
2
3
4
5
76
75
74
73
6
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
I/O22
I/O23
VDDQ
I/O9
I/O8
69
68
67
66
65
64
63
62
(1)
VSS
VSS
(1)
VDD
VSS
(2)
VDD
VDD
ZZ
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
61
60
59
58
57
56
55
54
53
52
51
VDDQ
I/O30
I/O31
I/OP4
,
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5298 drw 02
Top View
100TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is ≤ VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. Pins 84 is reserved for a future 16M.
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
5
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 512K x 18
AbsoluteMaximumRatings(1)
Commercial &
Industrial
Symbol
Rating
Unit
(2)
TERM
V
Te rminal Vo ltag e with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VSS
VDD
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
(3,6)
(4,6)
(5,6)
TERM
DD
V
Te rminal Vo ltag e with
Respect to GND
-0.5 to V
V
V
V
2
3
4
5
76
75
74
73
TERM
V
DD
Te rminal Vo ltag e with
Respect to GND
-0.5 to V +0.5
6
7
8
9
72
71
70
TERM
V
DDQ
Te rminal Vo ltag e with
Respect to GND
-0.5 to V +0.5
10
11
12
69
68
67
66
Commercial
0 to +70
-40 to +85
-55 to +125
-55 to +125
2.0
oC
oC
oC
oC
W
13
(1)
14
(7)
A
T
(1)
15
VSS
Industrial
(2)
16
65
64
63
62
VDD
VDD
ZZ
17
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
BIAS
T
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
18
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
19
20
61
60
59
STG
T
21
22
T
P
23
58
57
56
55
24
OUT
25
I
50
mA
NC
26
VSS
VDDQ
NC
NC
NC
5298 tbl 06
27
54
53
28
,
29
NOTES:
52
51
30
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5298 drw 02a
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
100TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the
input voltage is < VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input
voltage is >VIH.
7. TA is the “instant on” case temperature.
3. Pin 84 is reserved for a future 16M.
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
100TQFPCapacitance(1)
(TA = +25°C, f = 1.0MHz)
119BGACapacitance(1)
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
5
7
pF
7
7
pF
CI/O
pF
CI/O
pF
5298 tbl 07
5298 tbl 07a
165fBGACapacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
TBD pF
CI/O
TBD pF
5298 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.462
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
NC(3)
ADV/LD
A
A
A
2
3
2
9
NC
NC
CE
NC
NC
2
CE
7
A
DD
V
12
15
A
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
20
19
I/O
12
I/O
DDQ
V
V
V
V
V
V
OE
21
I/O
11
I/O
10
I/O
G
H
J
I/O
A
17
BW
2
3
BW
22
I/O
23
I/O
SS
SS
V
9
I/O
8
I/O
V
V
R/W
DDQ
24
DD
DD
V
DD
V
DDQ
DD(2)
SS
SS(1)
V
V
26
I/O
SS
6
I/O
7
I/O
K
L
I/O
V
CLK
NC
V
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
BW
1
DDQ
29
28
I/O
SS
V
SS
V
3
I/O
DDQ
1
M
N
P
R
T
CEN
30
I/O
SS
V
1
A
SS
V
2
I/O
I/O
I/O
31
I/O
P4
I/O
SS
V
0
A
SS
V
P1
I/O
0
I/O
NC
ZZ
,
5
A
DD
V
SS(1)
13
A
NC
NC
DDQ
V
A
LBO
10
11
14
NC
A
A
NC
U
V
DNU(4)
DNU(4)
DNU(4)
DNU(4)
DNU(4)
DDQ
V
5298 drw 13a
Top View
Pin Configuration 512K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
NC(3)
3
2
9
NC
NC
CE2
NC
NC
NC
2
CE
ADV/LD
7
A
DD
V
13
17
A
A
8
I/O
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
V
9
I/O
SS
6
I/O
NC
DDQ
CE
1
V
NC
SS
5
I/O
DDQ
V
V
NC
V
OE
SS
10
V
4
I/O
G
H
J
NC
I/O
NC
NC
BW
2
A
18
11
I/O
SS
V
SS
V
3
I/O
NC
R/W
DD(2)
V
SS(1)
V
DDQ
V
DD
DD
V
DD
V
DDQ
V
V
12
SS
SS
2
I/O
K
L
NC
I/O
NC
V
CLK
NC
V
NC
13
I/O
SS
1
I/O
V
V
V
V
NC
BW
1
DDQ
V
14
I/O
SS
SS
SS
SS
V
DDQ
V
M
N
P
R
T
NC
CEN
15
I/O
1
SS
V
0
I/O
NC
A
A
NC
P2
I/O
0
SS
V
P1
I/O
NC
NC
5
DD
V
12
A
NC
NC
DDQ
A
V
SS(1)
NC
ZZ
LBO
10
15
A
14
A
11
A
A
NC
,
DNU(4)
DNU(4)
DNU(4)
DNU(4)
DNU(4)
DDQ
V
U
V
5298 drw 13b
Top View
NOTES:
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. J3 does not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
3. A4 is reserved for future 16M.
4. DNU = Do not use; Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. The current die revision allows
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
7
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(3)
A
B
C
D
E
F
NC
NC
A
ADV/LD
OE
A
A
NC
7
17
8
CE
BW
BW
CE
CEN
R/W
1
3
2
2
(3)
(3)
A
6
CE
CLK
NC
A
9
NC
2
BW
BW
4
1
I/O
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
I/O
P2
P3
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
15
I/O
14
17
16
I/O
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
19
I/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
I/O
10
11
G
H
J
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
8
23
22
DDQ
DD
SS
SS
SS
DD
DDQ
9
(1)
(2)
V
SS
V
DD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
I/O
ZZ
I/O
I/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
7
6
K
L
M
N
P
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
4
27
26
DDQ
DD
SS
SS
SS
DD
DDQ
5
I/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
I/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
(4)
(1)
I/O
P4
NC
V
DDQ
V
SS
DNU
NC
V
SS
V
SS
V
DDQ
NC
I/O
P1
(3)
(4)
(4)
NC
LBO
NC
A
A
DNU
A
DNU
A
10
A
A
14
NC
5
2
1
13
(3)
(4)
(4)
R
NC
A
A
DNU
A
DNU
A
A
A
15
A
16
4
3
0
11
12
5298 tbl 25a
Pin Configuration 512K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(3)
A
NC
NC
NC
NC
NC
NC
NC
A
NC
BW
ADV/LD
OE
A
A
8
A
7
18
10
CE1
BW
CE
CEN
R/W
2
2
(3)
(3)
B
A
6
CE
2
NC
CLK
NC
A
9
NC
1
C
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
I/O
P1
D
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
8
E
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
6
9
F
I/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
G
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
4
11
(1)
(2)
H
V
V
DD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZZ
NC
NC
NC
NC
NC
NC
SS
J
I/O
NC
NC
NC
NC
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
12
K
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
13
L
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
14
M
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
15
(4)
(1)
N
I/O
V
DDQ
V
SS
DNU
NC
V
SS
V
SS
V
DDQ
NC
P2
(4)
(4)
(3)
P
R
NC
LBO
NC
A
5
A
2
DNU
A
1
DNU
A
11
A
14
A
15
(4)
(4)
(3)
NC
A
4
A
3
DNU
A
0
DNU
A
12
A
13
A
16
A
17
5298 tbl25b
NOTES:
1. Pins H1 and N7 do not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pin H2 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. Pin B9, B11, A1, R2 and P2 are reserved for a future 18M, 36M, 72M, 144M and 288M respectively.
4. DNU = Do not use. Pins P5, R5, P7, R7 and N5 are reserved for respective JTAG pins: TDI, TMS, TDO, TCK and TRST on future revisions. The current die
revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.482
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
(5)
R/W
ADV/LD
BWx
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
1,
CE CE
2
(One cycle later)
(7)
L
L
L
L
H
X
L
L
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
BURST WRITE
D
(7)
Q
(7)
Valid
LOAD WRITE /
BURST WRITE
D
(2)
(Advance burst counter)
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(2)
(Advance burst counter)
DESELECT or STOP(3)
NOOP
L
L
H
X
X
X
H
X
X
L
H
X
X
X
X
X
X
X
X
HIZ
HIZ
DESELECT / NOOP
X
(4)
SUSPEND
Previous Value
5298 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Osremainsunchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3)
OPERATION
R/W
H
L
1
2
3
4
BW
BW
X
L
BW
X
L
BW
READ
X
X
L
WRITE ALL BYTES
L
H
H
L
(2)
(2)
P1
WRITE BYTE 1 (I/O[0:7], I/O )
L
L
H
L
H
H
H
L
P2
WRITE BYTE 2 (I/O[8:15], I/O )
L
H
H
H
H
(2,3)
P3
WRITE BYTE 3 (I/O[16:23], I/O )
L
H
H
H
(2,3)
P4
WRITE BYTE 4 (I/O[24:31], I/O )
L
H
H
NO WRITE
L
H
5298 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5298 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
6.42
9
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
0
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
1
1
0
0
1
0
0
1
1
Second Address
Third Address
1
1
0
1
0
0
1
1
0
1
Fourth Address(1)
1
0
0
1
0
5298 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
CLOCK
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
(2)
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A17)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
I/O [0:31], I/O P[1:4]
,
5298 drw 03
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.1402
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2)
(1)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWx
X
X
X
X
X
X
X
X
L
OE
X
L
1
CE
0
A
1
D
n
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
X
L
H
X
L
X
H
L
X
L
H
X
L
L
L
X
L
X
L
Load read
Burst read
0
Q
n+1
X
A1
X
n+2
L
Q0+1 Load read
1
n+3
L
Q
Z
Z
Deselect or STOP
n+4
X
X
X
L
NOOP
n+5
A2
X
Load read
Burst read
Deselect or STOP
Load write
Burst write
Load write
Deselect or STOP
NOOP
2
Q
n+6
2+1
Q
n+7
X
L
3
A
n+8
X
X
X
X
X
X
X
L
Z
3
D
n+9
X
X
L
L
4
A
3+1
D
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
L
X
X
X
X
L
X
X
L
D4
Z
5
A
Z
Load write
Load read
Load write
Burst write
Load read
Burst read
Load write
6
A
5
D
H
L
X
L
7
A
6
Q
X
X
H
X
L
L
X
X
L
D7
8
A
7+1
D
X
X
L
8
Q
X
9
A
8+1
Q
L
5298 tbl 12
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
6.42
11
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
ReadOperation(1)
(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
CE1
L
n
n+1
A0
X
H
X
L
X
Address and Control meet setup
Contents of Address A0 Read Out
X
X
X
X
L
Q0
5298 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Read Operation(1)
(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
1
CE
0
n
A
H
X
X
X
X
H
X
H
L
H
H
H
H
L
L
X
X
X
X
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
Address and Control meet setup
0
Q
0
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
X
X
Address A Read Out, Inc. Count
0+1
Q
0+1
Address A Read Out, Inc. Count
0+2
Q
0+2
Address A Read Out, Inc. Count
0+3
Q
0+3
1
Address A Read Out, Load A
1
A
0
Q
0
Address A Read Out, Inc. Count
1
Q
1
X
H
L
X
L
Address A Read Out, Inc. Count
2
A
1+1
Q
1+1
2
Address A Read Out, Load A
5298 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation(1)
(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
CE1
L
n
A0
X
L
L
X
Address and Control meet setup
Write to Address A0
n+1
X
X
X
L
X
X
D0
5298 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Write Operation(1)
(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
X
X
X
X
X
X
X
1
CE
0
A
n
L
X
X
X
X
L
L
H
H
H
H
L
L
X
X
X
X
L
X
Address and Control meet setup
0
D
0
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
X
X
L
L
Address A Write, Inc. Count
L
L
D0+1 Address A0+1 Write, Inc. Count
0+2
D
0+2
Address A Write, Inc. Count
L
L
0+3
D
0+3
1
L
L
Address A Write, Load A
1
A
0
D
0
L
L
Address A Write, Inc. Count
1
D
1
X
X
L
H
L
X
L
L
L
Address A Write, Inc. Count
A2
L
L
D1+1 Address A1+1 Write, Load A2
5298 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.1422
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
L
1
CE
n
A0
X
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
X
X
X
AddressA0 and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
H
L
X
A1
X
X
Q0
Address A0 Read out, Load A1
0
Q
0
H
H
L
X
L
Clock Ignored. Data Q is on the bus.
X
X
L
Q0
Q1
Clock Ignored. Data Q0 is on the bus.
Address A1 Read out, Load A2
A2
X
L
3
A
2
Q
2
3
L
X
L
Address A Read out, Load A
A4
L
X
L
Q3
Address A3 Read out, Load A4
5298 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation with Clock Enable Used(1)
(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
X
X
X
X
X
1
CE
0
A
0
n
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
X
X
Address A and Control meet setup.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
H
L
X
L
Clock n+1 Ignored.
1
A
0
D
0
1
Write data D , Load A .
X
X
H
H
L
X
X
L
X
X
Clock Ignored.
Clock Ignored.
A2
D1
Write Data D1, Load A2
3
A
2
D
2
3
L
L
Write Data D , Load A
A4
L
L
D3
Write Data D3, Load A4
5298 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42
13
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
(3)
(2)
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
1
CE
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Z
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
0
A
0
Z
Address A and Control meet setup.
X
H
L
Q0
Z
Address A0 read out, Deselected.
1
A
1
X
L
Address A and Control meet setup.
1
Q
1
X
X
H
H
L
Address A read out, Deselected.
X
X
L
Z
Z
Deselected.
A2
X
Address A2 and Control meet setup.
2
Q
2
H
H
Address A read out, Deselected.
X
X
Z
Deselected.
5298 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Write Operation with Chip Enable Used(1)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
X
X
L
OE
X
X
X
X
X
X
X
X
X
X
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
?
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
L
Z
Z
0
A
0
L
Address A and Control meet setup
0
D
0
X
X
L
H
L
L
X
L
Data D Write In, Deselected.
1
A
1
L
Z
Address A and Control meet setup
1
D
1
X
X
X
X
L
H
H
L
L
X
X
L
Data D Write In, Deselected.
L
Z
Z
Deselected.
2
A
2
L
Address A and Control meet setup
2
D
2
X
X
X
X
H
H
L
X
X
Data D Write In, Deselected.
L
Z
Deselected.
5298 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1442
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V±5%)
Symbol
Parameter
Input Leakage Current
Test Conditions
Min.
Max.
Unit
___
LI
|I |
DD
V
IN
DD
= Max., V = 0V to V
5
µA
(1)
___
___
___
LBO Input Leakage Current
LI
DD
IN
DD
|I |
V
= Max., V = 0V to V
30
5
µA
µA
V
LO
|I |
OUT
V
CC
= 0V to V
Output Leakage Current
Output Low Voltage
Output High Voltage
OL
V
OL
DD
I
= +8mA, V = Min.
0.4
___
OH
V
OH
DD
I
= -8mA, V = Min.
2.4
V
5298 tbl 21
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V±5%)
7.5ns
8ns
8.5ns
Com'l
Symbol
Parameter
Test Conditions
Unit
Com'l
Ind
Com'l
Ind
Ind
Operating Power
Device Selected, Outputs Open,
DD
I
DD
Supply Current
ADV/LD = X, V = Max.,
275
40
295
250
40
60
225
40
95
40
40
60
mA
(2)
IN
IH
IL
MAX
V > V or < V , f = f
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
SB1
I
DD
IN
HD
LD
V
= Max., V > V or < V ,
60
125
60
60
120
60
60
115
60
mA
mA
mA
(2,3)
f = 0
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
SB2
I
DD
IN
HD
LD
V
= Max., V > V or < V ,
105
40
100
40
(2,3)
MAX
f = f
Idle Power
Supply Current
Device Selected, Outputs Open,
SB3
I
IH DD
CEN > V , V = Max.,
(2,3)
IN
HD
LD
MAX
V > V or < V , f = f
Full Sleep Mode
Supply Current
Device Selected, Outputs Open,
ZZ
I
IL DD
HD
CEN < V , V = Max., ZZ > V
40
60
40
60
60
mA
(2,3)
MAX
IN
HD
LD
V > V or < V , f = f
NOTES:
1. All values are maximum guaranteed values.
5298 tbl 22
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Conditions
Input Pulse Levels
AC Test Load
VDDQ/2
0 to 3V
50Ω
Input Rise/Fall Times
2ns
1.5V
I/O
Z0 = 50Ω
,
5298 drw 04
Input Timing Reference Levels
Output Reference Levels
Output Load
6
5
4
3
Figure 1. AC Test Load
1.5V
Figure 1
•
5298 tbl 23
∆tCD
(Typical, ns)
2
•
•
1
•
•
20 30 50
80 100
Capacitance (pF)
200
5298 drw 05
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
CYC
t
Clock Cycle Time
10
2.5
2.5
10.5
2.7
11
3.0
3.0
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
CH
t
____
____
____
(1)
2.7
CL
t
Output Parameters
____
____
____
CD
t
Clock High to Valid Data
7.5
8
8.5
ns
ns
ns
____
____
____
CDC
t
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
2
2
2
____
____
____
(2, 3,4)
3
3
3
CLZ
t
____
____
____
(2, 3,4)
5
5
5
ns
ns
ns
ns
CHZ
t
____
____
____
OE
t
5
5
5
____
____
____
(2,3)
(2,3)
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
0
OLZ
t
____
____
____
5
5
5
OHZ
t
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
SE
t
Clock Enable Setup Time
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
SA
t
Address Setup Time
SD
t
Data In Setup Time
SW
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
SADV
t
SC
t
SB
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HE
t
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
HA
t
Address Hold Time
HD
t
Data In Hold Time
HW
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
HADV
t
HC
t
HB
t
ns
5298 tbl 24
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.1462
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
6.42
17
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
,
6.1482
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
6.42
19
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
,
6.2402
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
,
6.42
21
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.2422
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
23
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
165 Ball Grid Array (fBGA) Package Diagram Outline
6.2442
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATA
Q
Q
OUT
,
5298 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
X
IDT
XXXX
S
XX
XX
Process/
Temperature Range
Device
Type
Power Speed
Package
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
,
PF
BG
BQ
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
75
80
85
Access time (tCD) in tenths of nanoseconds
IDT71V65703 256Kx36 Flow-Through ZBT SRAM
IDT71V65903
512Kx18 Flow-Through ZBT SRAM
5298 drw 12
6.42
25
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
12/31/99
04/20/00
Creatednewpartnumberanddatasheetfrom71V657/59to71v65703/5903
Pg.5,6
AddJTAGresetpinstoTQFPpinconfiguration;removedfootnote
AddclarificationnotetoRecommendedOperatingTemperatureandAbsoluteMaxRatingstables
AddnotetoBGApinconfiguration;correctedtypowithinpinout
InsertTQFPPackageDiagramOutline
Pg. 7
Pg. 21
05/23/00
07/28/00
Addnewpackage offering:13mmx15mm, 165fine pitchballgridarray
Correctionon119BallGridArrayPackage diagramOutline
Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and
IDT71V658xx device errata sheet
Pg. 23
Pg. 5-8
Pg. 7,8
Pg. 23
Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout
UpdateBG119packagediagramdimensions
11/04/00
12/04/02
12/18/02
Pg. 8
Pg. 15
Pg. 1-25
Pg.5,6,15,16,25
Pg. 1,2,5,6,7,8
Pg. 7
Add reference note to pin N5 on the BQ165 pinout, reserved for JTAG TRST
AddIzztoDCElectricalCharacteristics
ChangeddatasheetfromPreliminarytofinalrelease.
AddedItemptodatasheet
RemovedJTAGfunctionalityforcurrentdierevision.
Correctedpinconfigurationonthe x36, 119BGA. Switchedpins I/O0andI/OP1.
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800-544-7726, x4033
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.2462
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