IDT71V65803S133BQI [IDT]
256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs; 256K ×36 ， 512K ×18的3.3V同步ZBT SRAM的
| 型号： | IDT71V65803S133BQI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs |
| 文件： | 总26页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™Feature
IDT71V65603
IDT71V65803
3.3V I/O, Burst Counter
PipelinedOutputs
Features
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
◆
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
◆
◆
Internally synchronized output buffer enable eliminates the
AClockEnable(CEN)pinallowsoperationoftheIDT71V65603/5803to
besuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen
(CEN)ishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired.Ifanyoneofthesethreearenotasserted
whenADV/LDislow,nonewmemoryoperationcanbeinitiated.However,
anypendingdatatransfers(readsorwrites)willbecompleted.Thedatabus
willtri-statetwocyclesafterchipisdeselectedorawriteisinitiated.
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst
mode,theIDT71V65603/5803canprovidefourcyclesofdataforasingle
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter
(ADV/LD = HIGH).
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).
◆
◆
◆
◆
◆
◆
◆
◆
◆
Description
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus
cycleswhenturningthebusaroundbetweenreadsandwrites,orwritesand
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-
pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)and
165 fine pitch ball grid array (fBGA) .
TM
reads.Thus,theyhavebeengiventhenameZBT ,orZeroBusTurnaround.
PinDescriptionSummary
0
18
A -A
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
1
2
2
CE , CE , CE
Output Enable
OE
R/W
CEN
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
1
2
3
4
BW , BW , BW , BW
CLK
ADV/LD
LBO
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
ZZ
Asynchronous
Synchronous
Static
0
31
P1
P4
I/O -I/O , I/O -I/O
Data Input / Output
Core Power, I/O Power
Ground
DD DDQ
V , V
Supply
Supply
SS
V
Static
5304 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
DECEMBER 2002
1
©2002IntegratedDeviceTechnology,Inc.
DSC-5304/05
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
0
18
A -A
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD
is sampled high then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is sampled high.
R/W
Read / Write
Clock Enable
I
I
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs remain unchanged. The effect of CEN
sampled high on the device outputs is as if the low to high clock transition did not occur.
For normal operation, CEN must be sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.
1
4
BW -BW
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
1
4
signal (BW -BW ) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
1
4
byte(s) of data are written into the device two cycles later. BW -BW can all be tied low if
always doing write to the entire 36-bit word.
1
2
2
Chip Enables
LOW Synchronous active low chip enable. CE and CE are used with CE to enable the
1
2
CE , CE
1
2
2
IDT71V65603/5803. (CE or CE sampled high or CE sampled low) and ADV/LD low at the
rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
2
2
1
2
CE
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE is used with CE and CE to enable the chip.
2
1
2
CE has inverted polarity but otherwise identical to CE and CE .
CLK
N/A
N/A
This is the clock input to the IDT71V65603/5803. Except for OE, all timing references for the
device are made with respect to the rising edge of CLK.
0
31
I/O -I/O
I/O -I/O
Data Input/Output
Linear Burst Order
I/O
I
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
P1
P4
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Linear burst sequence is selected. LBO is a static input and it must
not change during device operation.
LBO
Output Enable
Sleep Mode
I
I
LOW Asynchronous output enable. OE must be low to read data from the 71V65603/5803. When
OE is high the I/O pins are in a high-impedance state. OE does not need to be actively
controlled for read and write cycles. In normal operation, OE can be tied low.
OE
ZZ
N/A
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
71V65603/5803 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
DD
V
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
DDQ
V
SS
V
Ground.
5304tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.42
2
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
256Kx36 BIT
LBO
MEMORY ARRAY
Address A [0:17]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5304 drw 01a
,
Data I/O [0:31],
I/O P[1:4]
6.42
3
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
512x18 BIT
LBO
MEMORY ARRAY
Address A [0:18]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5304 drw 01
,
Data I/O [0:15],
I/O P[1:2]
RecommendedDCOperating
Conditions
Symbol
VDD
VDDQ
VSS
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
3.135
0
Typ.
Max.
3.465
3.465
0
Unit
V
3.3
3.3
V
0
V
____
VIH
Input High Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
2.0
VDD+0.3
VDDQ+0.3
0.8
V
____
____
VIH
2.0
V
VIL
-0.3(1)
V
5304 tbl 04
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
6.42
4
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Temperature(1)
0° C to +70° C
-40°C to +85°C
V
V
SS
DD
DDQ
V
Grade
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
5304 tbl 05
NOTES:
1. TA is the "instant on" case temperature.
Pin Configuration - 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
2
3
4
5
76
75
74
73
6
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
I/O22
I/O23
VDDQ
I/O9
I/O8
69
68
67
66
65
64
(1)
VDD
VSS
VDD
(1)
VDD
(1)
VDD
VDD
ZZ
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
63
62
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
61
60
59
58
57
56
55
54
53
VDDQ
I/O30
I/O31
I/OP4
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5304 drw 02
,
TopView
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
5
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
Pin Configuration - 512K x 18
Commercial &
Industrial
Symbol
Rating
Unit
(2)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
2
NC
(3,6)
VTERM
DD
-0.5 to V
Terminal Voltage with
Respect to GND
V
V
3
NC
4
VDDQ
5
VSS
76
75
74
73
6
NC
(4,6)
TERM
V
Terminal Voltage with
Respect to GND
-0.5 to V +0.5
DD
7
NC
8
I/O8
9
I/O9
72
71
10
(5,6)
TERM
VSS
V
Terminal Voltage with
Respect to GND
-0.5 to V +0.5
DDQ
V
11
70
69
68
67
66
VDDQ
12
I/O10
13
I/O11
VDD
(1)
oC
14
Commercial
Operating Temperature
-0 to +70
(1)
15
VDD
VDD
VDD
ZZ
(7)
(1)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
65
64
VDD
A
T
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
63
62
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
Industrial
Operating Temperature
-40 to +85
oC
oC
61
60
59
BIAS
Temperature
Under Bias
-55 to +125
T
58
57
56
55
NC
STG
T
Storage
Temperature
-55 to +125
oC
VSS
VDDQ
NC
54
53
52
51
NC
NC
PT
Power Dissipation
DC Output Current
2.0
50
W
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
IOUT
mA
5304 drw 02a
5304 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
7. TA is the "instant on" case temperature.
100TQFPCapacitance(1)
(TA = +25° C, f = 1.0MHz)
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
5
7
pF
TBD
TBD
pF
CI/O
pF
CI/O
pF
5304 tbl 07
5304 tbl 07b
119BGACapacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
7
7
pF
CI/O
pF
5304 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
6
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K X 36, 119 BGA
1
2
3
4
5
6
7
(2)
DDQ
6
4
NC
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
2
3
2
9
NC
NC
16
CE
NC
NC
2
CE
ADV/LD
7
DD
V
12
15
A
A
A
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
20
19
I/O
12
I/O
DDQ
10
V
V
OE
21
I/O
11
I/O
G
H
J
I/O
A17
I/O
2
BW3
BW
22
I/O
23
I/O
SS
V
SS
V
9
I/O
8
I/O
R/W
DDQ
V
DD
DD
V
DD
V
DDQ
7
DD(1)
DD(1)
V
V
V
V
V
V
24
I/O
26
I/O
SS
4
SS
6
I/O
K
L
CLK
NC
I/O
25
I/O
27
I/O
4
I/O
5
I/O
1
BW
BW
DDQ
28
SS
V
SS
SS
SS
3
DDQ
V
M
N
P
R
T
V
I/O
V
V
V
I/O
CEN
29
I/O
30
I/O
SS
V
1
2
I/O
1
I/O
A
0
I/O
31
I/O
P4
I/O
SS
0
P1
I/O
V
A
5
DD
11
VDD(1)
14
13
NC
NC
A
V
A
LBO
10
A
NC
NC
DNU
A
A
NC
DNU
ZZ
(3)
(3)
(3)
(3)
(3)
DDQ
V
DDQ
V
DNU
DNU
DNU
U
,
5304 drw 13A
Top View
Pin Configuration - 512K X 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
9
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
NC(2)
3
2
CE2
NC
NC
NC
NC
NC
2
CE
ADV/LD
7
A
DD
V
13
17
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
V
V
V
V
9
I/O
6
I/O
1
CE
NC
NC
DDQ
V
5
I/O
DDQ
V
NC
OE
10
4
I/O
G
H
J
NC
I/O
NC
NC
A18
BW2
11
I/O
SS
SS
3
I/O
V
V
NC
R/W
DD(1)
DD(1)
DDQ
V
DD
12
DD
V
DD
DDQ
V
V
V
V
V
V
SS
SS
2
I/O
K
L
NC
I/O
CLK
NC
V
NC
13
I/O
SS
1
I/O
NC
V
NC
1
BW
DDQ
14
SS
SS
SS
SS
DDQ
V
M
N
P
R
T
V
I/O
V
V
V
V
V
V
NC
CEN
15
SS
SS
1
0
0
I/O
I/O
NC
NC
A
A
NC
P2
P1
I/O
I/O
NC
5
DD
V
12
A
DD(1)
V
NC
NC
DDQ
A
NC
LBO
10
15
14
A
11
A
A
A
NC
ZZ
(3)
(3)
(3)
(3)
(3)
DNU
DNU
DNU
DNU
DNU
DDQ
V
U
V
5304 drw 13B
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A4 is reserved for future 16M.
3. DNU = Do not use. Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. The current die revision allows
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
7
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K X 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
A8
11
(2)
A
B
C
D
E
F
NC
A7
ADV/LD
A17
NC
CE1
BW3
BW4
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A2
BW2
BW1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CEN
R/W
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(2)
(2)
NC
A6
CE2
NC
A9
NC
OE
I/OP3
I/O17
I/O19
I/O21
I/O23
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
I/OP2
I/O14
I/O12
I/O10
I/O8
ZZ
I/O16
I/O18
I/O20
I/O22
I/O15
I/O13
I/O11
I/O9
NC
G
H
J
(1)
(1)
VDD
VDD
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
I/O7
I/O5
I/O3
I/O1
NC
I/O6
I/O4
I/O2
I/O0
I/OP1
NC
K
L
M
N
P
(3)
(1)
DNU
VDD
(2)
(3)
(3)
NC
DNU
A1
DNU
A14
A15
(2)
(3)
(3)
R
NC
A4
A3
DNU
A0
DNU
A11
A12
A16
LBO
5304 tbl 25a
Pin Configuration - 512K X 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(2)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
NC
BW
ADV/LD
OE
A
A
8
A
7
18
10
CE
BW
CE
CEN
R/W
1
2
2
(2)
(2)
A
6
CE
2
NC
CLK
NC
A
9
NC
1
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
I/O
P1
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
8
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
6
9
I/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
G
H
J
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
4
11
(1)
(1)
V
V
DD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZZ
NC
NC
NC
NC
NC
NC
DD
I/O
NC
NC
NC
NC
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
12
K
L
M
N
P
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
13
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
14
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
15
(3)
(1)
I/O
V
DDQ
V
SS
DNU
NC
V
V
SS
V
DDQ
NC
P2
DD
(2)
(3)
(3)
NC
LBO
NC
A
5
A
2
DNU
A
1
DNU
A
11
A
14
A
15
(2)
(3)
(3)
R
NC
A
4
A
3
DNU
A
0
DNU
A12
A
13
A
16
A
17
5304 tbl25b
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. B9, B11, A1, R2 and P2 is reserved for future 18M, 36M, 72M, 144M and 288M, respectively.
3. DNU=Do not use. Pins P5, R5, P7 and R7 are reserved for respective JTAG pins: TDI, TMS, TDO and TCK on future revisions. The current die revision
allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
8
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
R/W
Chip(5)
Enable
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
(2 cycles later)
(7)
L
L
L
L
H
X
Select
Select
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
BURST WRITE
D
(7)
Q
(7)
Valid
LOAD WRITE /
BURST WRITE
D
(2)
(Advance burst counter)
(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(2)
(Advance burst counter)
DESELECT or STOP(3)
NOOP
L
L
H
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
HiZ
HiZ
X
X
DESELECT / NOOP
X
(4)
SUSPEND
Previous Value
5304 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3)
OPERATION
R/W
H
L
1
2
3
4
BW
BW
X
L
BW
X
L
BW
READ
X
X
L
WRITE ALL BYTES
L
H
H
L
(2)
(2)
P1
WRITE BYTE 1 (I/O[0:7], I/O )
L
L
H
L
H
H
H
L
P2
WRITE BYTE 2 (I/O[8:15], I/O )
L
H
H
H
H
(2,3)
P3
WRITE BYTE 3 (I/O[16:23], I/O )
L
H
H
H
(2,3)
P4
WRITE BYTE 4 (I/O[24:31], I/O )
L
H
H
NO WRITE
L
H
5304 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
9
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5304 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5304 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A17)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:31], I/O P[1:4]
5304 drw 03
,
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
10
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
DeselectandNOOPCycles(2)
CE(1)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BWx
X
X
X
X
X
X
X
X
L
OE
X
X
L
0
A
n
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
X
X
Load read
Burst read
Load read
Deselect or STOP
NOOP
n+1
X
X
L
1
A
0
Q
n+2
0+1
Q
n+3
X
X
H
X
L
L
1
Q
n+4
L
2
A
n+5
X
X
L
Z
Z
Load read
Burst read
Deselect or STOP
Load write
Burst write
Load write
Deselect or STOP
NOOP
n+6
X
X
X
H
L
2
Q
n+7
3
A
2+1
Q
n+8
L
n+9
X
X
L
X
L
L
X
X
X
X
X
X
X
L
Z
4
A
3
D
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
L
3+1
D
X
X
X
X
L
H
X
L
X
X
L
4
D
5
A
Z
Z
Load write
Load read
Load write
Burst write
Load read
Burst read
Load write
6
A
H
L
L
X
L
7
A
5
D
L
6
Q
X
X
H
X
L
X
L
L
8
A
7
D
X
X
L
X
X
L
7+1
D
X
X
L
9
A
8
Q
5304tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
ReadOperation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
0
A
n
H
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
L
X
X
0
Q
0
X
X
X
L
Contents of Address A Read Out
5304 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
X
L
0
A
n
H
X
X
X
X
H
X
X
H
L
H
H
H
H
L
X
X
Address and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
L
X
Clock Setup Valid, Advance Counter
0
Q
0
X
L
X
Address A Read Out, Inc. Count
0+1
Q
0+1
X
L
X
L
Address A Read Out, Inc. Count
0+2
Q
0+2
X
L
X
L
Address A Read Out, Inc. Count
1
A
0+3
Q
0+3
1
L
L
X
L
Address A Read Out, Load A
0
Q
0
X
X
H
H
L
X
L
X
L
Address A Read Out, Inc. Count
1
Q
1
X
L
X
L
Address A Read Out, Inc. Count
2
A
1+1
Q
1+1
2
L
L
X
L
Address A Read Out, Load A
5304 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
0
A
n
L
X
X
L
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
L
X
X
0
D
0
X
L
X
X
Write to Address A
5304 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
L
OE
X
X
X
X
X
X
X
X
X
0
A
n
L
X
X
X
X
L
L
H
H
H
H
L
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
X
X
X
X
L
L
0
D
0
X
L
L
Address A Write, Inc. Count
0+1
D
0+1
X
L
L
Address A Write, Inc. Count
0+2
D
0+2
X
L
L
Address A Write, Inc. Count
1
A
0+3
D
0+3
1
L
L
L
Address A Write, Load A
0
D
0
X
X
X
X
L
H
H
L
X
L
L
Address A Write, Inc. Count
1
D
1
X
L
L
Address A Write, Inc. Count
2
A
1+1
D
1+1
2
L
L
L
Address A Write, Load A
5304 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
12
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
L
0
A
n
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
X
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
H
L
X
1
A
X
Clock Valid
0
Q
0
X
X
X
X
L
H
H
L
X
Clock Ignored, Data Q is on the bus.
0
Q
0
X
L
Clock Ignored, Data Q is on the bus.
2
A
0
Q
0
X
L
Address A Read out (bus trans.)
3
A
1
Q
1
L
L
X
L
Address A Read out (bus trans.)
4
A
2
Q
L
L
X
L
Address A2 Read out (bus trans.)
5304 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
X
X
X
X
X
0
A
n
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
L
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
H
L
X
L
1
A
X
X
X
X
L
H
H
L
X
X
L
Clock Ignored.
Clock Ignored.
2
A
0
D
0
Write Data D
3
A
1
D
1
L
L
L
Write Data D
4
A
2
D
2
L
L
L
Write Data D
5304 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
(3)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
Deselected.
0
A
Z
Z
Address and Control meet setup
Deselected or STOP.
X
H
L
1
A
0
Q
0
1
Address A Read out. Load A .
X
X
H
H
L
X
L
Z
Deselected or STOP.
1
1
Q
Z
Z
Address A Read out. Deselected.
2
A
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
2
Q
2
Address A Read out. Deselected.
5304 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
(3)
CE(2)
H
H
L
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
I/O
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
?
Deselected.
0
A
Z
Z
Address and Control meet setup
Deselected or STOP.
X
X
L
H
L
X
L
1
A
0
D
0
1
Address D Write in. Load A .
X
X
X
X
L
H
H
L
X
X
L
Z
Deselected or STOP.
1
1
D
Z
Z
Address D Write in. Deselected.
2
A
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
H
X
X
2
D
2
Address D Write in. Deselected.
5304 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
14
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
LI
|I |
DD
V
IN
DD
Input Leakage Current
= Max., V = 0V to V
5
µA
(1)
___
___
___
LBO Input Leakage Current
LI
DD
IN
DD
|I |
V
= Max., V = 0V to V
30
5
µA
µA
V
LO
|I |
OUT
V
DDQ
Output Leakage Current
Output Low Voltage
= 0V to V , Device Deselected
L
VO
OL
DD
I
= +8mA, V = Min.
0.4
___
OH
V
OH
DD
Output High Voltage
I
= -8mA, V = Min.
2.4
V
NOTE:
5304 tbl 21
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to Vss if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V +/-5%)
150MHz
133MHz
100MHz
Com'l
Unit
Symbol
Parameter
Test Conditions
Com'l
Ind
Com'l
Ind
Ind
IDD
Device Selected, Outputs Open,
Operating Power
Supply Current
mA
ADV/LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX
325
40
345
300
40
320
250
40
270
(2)
ISB1
ISB2
ISB3
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
CMOS Standby Power
Supply Current
mA
mA
mA
60
140
60
60
130
60
60
120
60
(2,3)
f = 0
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
Clock Running Power
Supply Current
120
40
110
40
100
40
(2.3)
f = fMAX
Device Selected, Outputs Open,
Idle Power
Supply Current
CEN > V
IH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX
(2,3)
Device Selected, Outputs Open
CEN ≤ VIL, VDD = Max., ZZ ≥ VHD
VIN ≥ VHD or ≤ VLD, f = fMax(2, 3)
Full Sleep Mode
Supply Current
IZZ
40
60
40
60
40
60
mA
5304 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Load
AC Test Conditions
(VDDQ = 3.3V)
VDDQ/2
50Ω
I/O
Z0 = 50Ω
Input Pulse Levels
0 to 3V
2ns
,
5304 drw 04
6
5
4
Input Rise/Fall Times
Figure 1. AC Test Load
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
1.5V
•
3
∆tCD
(Typical, ns)
See Figure 1
2
•
5304 tbl 23
•
1
•
•
20 30 50
80 100
Capacitance (pF)
200
,
5304 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
(6)
150MHz
133MHz
100MHz
Max.
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Unit
____
____
____
tCYC
Clock Cycle Time
6.7
7.5
10
ns
MHz
ns
(1)
____
____
____
Clock Frequency
150
133
100
tF
(2)
____
____
____
Clock High Pulse Width
Clock Low Pulse Width
2.0
2.0
2.2
2.2
3.2
3.2
tCH
(2)
____
____
____
ns
tCL
Output Parameters
____
____
____
tCD
Clock High to Valid Data
3.8.
4.2
5
ns
ns
ns
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
1.5
1.5
1.5
1.5
1.5
1.5
(3,4,5)
____
____
____
tCL Z
(3,4,5)
1.5
3
1.5
3
1.5
3.3
ns
ns
ns
ns
tCHZ
____
____
____
tOE
Output Enable Access Time
3.8
4.2
5
(3,4)
____
____
____
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
0
tOLZ
(3,4)
____
____
____
3.8
4.2
5
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSE
Clock Enable Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
tSA
Address Setup Time
tSD
Data In Setup Time
tSW
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
tSADV
tSC
tSB
Hold Times
tHE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
tHA
Address Hold Time
tHD
Data In Hold Time
tHW
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
tHADV
tHC
tHB
5304 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6. Commercial temperature range only.
6.42
16
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
6.42
17
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
.
6.42
18
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
,
6.42
19
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
6.42
20
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
6.42
21
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42
22
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array(BGA) Package Diagram Outline
6.42
23
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
24
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
,
5304 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
IDT
XXXX
S
XX
XX
X
Process/
Temperature
Range
Device
Type
Power Speed
Package
Commerical (0° to 70°C)
Industrial (-40° to 85°C)
Blank
I
PF
BG
BQ
100 pin Plastic Thin Quad Flatpack, (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
150
133
100
Clock Frequency in Megahertz
5304 drw 12
IDT71V65603
IDT71V65803
256Kx36 Pipelined ZBT SRAM
512Kx18 Pipelined ZBT SRAM
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
sramhelp@idt.com
800-544-7726, x4033
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
25
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
03/04/00
04/20/00
Creatednewdatasheetfromobsoletedevices IDT71V656andIDT71V658
Pg. 1,14,15 Removed166MHzspeedgrade offering;Added150MHzspeedgrade offering
Pg. 5,6
Pg. 5,6
Pg. 7
AddedJTAGtestpinstoTQFPpinconfiguration;removedfootnote
AddclarificationnotetoRecommendedOperatingtemperatureandAbsoluteMaxRatingstables
AddnotetoBGApinConfiguration;correcttypowithinpinout
InsertTQFPPackageDiagramOutline
Pg. 21
05/23/00
07/28/00
Addnewpackage offering, 13x15mm165fBGA
CorrectioninBG119PackageDiagramOutline
Addindustrialtemperature
Pg. 23
Pg. 2
Correction VDDQ 3.3V I/O supply
Pg. 5-8
Pg. 7
Remove JTAG offerings, refer to IDT71V656xx and IDT71V658xx device errata sheet
Correct pin B2
Pg. 8
Change pin B1 to NC
Pg. 23
Pg. 8
Pg. 15
Pg. 16
UpdateBG119PackageDiagramOutline
11/04/00
10/16/01
12/04/02
Add note to pin N5 on BQ165 pinout, reserved for JTAG TRST
AddIzzparametertoDCElectricalCharacteristics
Changedsub-headertoinclude CommercialandIndustrialTemperature Ranges. Correctedthe TCH
from 22ns to 2.2ns and TSADV from 20ns to 2.0ns.
ChangeddatasheetfromPrelininarytofinalrelease.
AddedItempto150MHz.
Pg. 1-25
Pg. 15
Pg. 16
Correctedtypofrom22to2.2.
12/19/02
Pg. 1,2,5,6, RemovedJTAGfunctionalityforcurrentdierevision.
7,8
Pg. 7
Correctedpinconfigurationonthe x36, 119BGA. Switchedpins I/O0andI/OP1.
6.42
26
相关型号：
IDT71V65803S150BGGI
ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MO-028AA, BGA-119
IDT
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