IDT71V6590385PFGI [IDT]

3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs;


型号：	IDT71V6590385PFGI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs 静态存储器
文件：	总23页 (文件大小：615K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

◆

256K x 36, 512K x 18

IDT71V65703

IDT71V65903

3.3VSynchronousZBT™SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

Features

256K x 36, 512K x 18 memory configurations

Address and control signals are applied to the SRAM during one

clock cycle, and on the next clock cycle the associated data cycle

occurs, be it read or write.

The IDT71V65703/5903 contain address, data-in and control

signal registers. The outputs are flow-through (no output data

used to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903

tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen

CEN is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

user to deselect the device when desired. If any one of these three

is not asserted when ADV/LD is low, no new memory operation can

be initiated. However, any pending data transfers (reads or writes)

will be completed. The data bus will tri-state one cycle after the chip

is deselected or a write is initiated.

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply ( 5%)

3.3V ( 5%) I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

TheIDT71V65703/5903haveanon-chipburstcounter.Intheburst

mode,theIDT71V65703/5903canprovidefourcyclesofdataforasingle

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

The IDT71V65703/5903 SRAMs utilize a high-performance CMOS

process and are packaged in a JEDEC Standard 14mm x 20mm 100-

pin plasticthinquadflatpack(TQFP), 119 ballgridarray(BGA) and a 165

fine pitch ball grid array (fBGA).

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Green parts available, see ordering information

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

aroundbetweenreadsandwrites, orwritesandreads. Thustheyhave

been given the name ZBT^TM, or Zero Bus Turnaround.

Pin Description Summary

-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE

2, CE2

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

BW , BW

CLK

Individual Byte Write Selects

Clock

2, BW3, BW4

ADV/LD

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/O

0-I/O31 , I/OP1-I/OP4

Data Input/Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5298 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2014

DSC-5298/05

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Definitions⁽¹⁾

Symbol

Pin Function

I/O Active

Description

0-A18

Address Inputs

N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of

CLK, ADV/LD low, CEN low, and true chip enables.

ADV/LD

Advance / Load

N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control

when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with

the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the

internal burst counter is advanced for any burst that was in progress. The external addresses are

ignored when ADV/LD is sampled high.

R/W

Read / Write

Clock Enable

N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or

Write access to the memory array. The data bus activity for the current cycle takes place one clock

cycle later.

LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including

clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device

outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be

sampled low at rising edge of clock.

CEN

Individual Byte

Write Enables

LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load

BW1-BW4

write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW

must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write

signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the

device one cycle later. BW -BW can all be tied low if always doing write to the entire 36-bit word.

1-BW4)

Chip Enables

LOW Synchronous active low chip enable. CE

and CE2 are used with CE2 to enable the IDT71V65703/5903

CE1, CE2

(CE or CE sampled high or CE

2 sampled low) and ADV/LD low at the rising edge of clock, initiates

a deselect cycle. The ZBT^TMhas a one cycle deselect, i.e., the data bus will tri-state one clock cycle

after deselect is initiated.

Chip Enable

Clock

HIGH Synchronous active high chip enable. CE

is used with CE

1 and CE2 to enable the chip. CE2 has

inverted polarity but otherwise identical to CE

and CE

CLK

N/A This is the clock input to the IDT71V65703/5903. Except for OE, all timing references for the device are

made with respect to the rising edge of CLK.

I/O

I/OP1-I/OP4

-I/O31 Data Input/Output I/O

N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The

data output path is flow-through (no output register).

Linear Burst

Order

LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO

is low the Linear burst sequence is selected. LBO is a static input, and it must not change during

device operation.

LBO

Output Enable

Sleep Mode

LOW Asynchronous output enable. OE must be low to read data from the 71V65703/5903. When OE is HIGH

the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and

write cycles. In normal operation, OE can be tied low.

HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V65703/5903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.

DDQ

Power Supply

Ground

N/A

N/A 3.3V core power supply.

N/A 3.3V I/O supply.

N/A Ground.

5298 tbl 02

NOTE:

1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.

6.422

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Functional Block Diagram 256K x 36

LBO

256K x 36 BIT

MEMORY ARRAY

Address

Address A [0:17]

CE1, CE2 CE2

R/W

CEN

Control

ADV/LD

BWx

Control Logic

Clk

Mux

Sel

Clock

Gate

Data I/O [0:31], I/O P[1:4]

5298 drw 01

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Functional Block Diagram 512K x 18

LBO

512K x 18 BIT

MEMORY ARRAY

Address

Address A [0:18]

CE1, CE2 CE2

R/W

CEN

Control

ADV/LD

BWx

Control Logic

Clk

Mux

Sel

Clock

Gate

Data I/O [0:15], I/O P[1:2]

5298 drw 01a

RecommendedDCOperating

Conditions

Symbol

V^DD

V^DDQ

V^SS

Parameter

Core Supply Voltage

I/O Supply Voltage

Ground

Min.

3.135

Typ.

3.3

Max.

3.465

Unit

3.3

3.465

____

V^IH

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

2.0

V^DD+ 0.3

V^DDQ+ 0.3

0.8

____

V^IH

2.0

V^IL

-0.3⁽¹⁾

5298 tbl 04

NOTE:

1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

6.442

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

Grade

Commercial

Industrial

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

VDDQ

3.3V 5%

5298 tbl 05

NOTE:

1. TA is the “instant on” case temperature.

Pin Configuration — 256K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/OP3

I/O16

I/O17

I/OP2

I/O15

I/O14

VDDQ

I/O18

I/O19

I/O20

I/O21

I/O13

I/O12

I/O11

I/O10

VSS

VDDQ

DDQ

I/O22

I/O

I/O23

(1)

VDD

VSS

(2)

VDD

VSS

I/O

I/O24

I/O25

VDDQ

DDQ

VSS

I/O26

I/O27

I/O28

I/O29

I/O

VSS

VDDQ

DDQ

I/O30

I/O31

I/OP4

I/O

I/OP1

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5298 drw 02

Top View

100 TQFP

NOTES:

1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is ≤ VIL.

2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.

3. Pins 84 is reserved for a future 16M.

4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins TMS, TDI, TDO and TCK. The

current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).

6.42

(TA = +25

C, f = 1.0MHz)

(TA = +25

C, f = 1.0MHz)

(TA = +25

C, f = 1.0MHz)

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration — 512K x 18

Absolute Maximum Ratings⁽¹⁾

Commercial &

Industrial

Symbol

Rating

Unit

(2)

TERM

Terminal Voltage with

Respect to GND

-0.5 to +4.6

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

(3,6)

(4,6)

(5,6)

TERM

Terminal Voltage with

Respect to GND

-0.5 to VDD

DDQ

VDDQ

Terminal Voltage with

Respect to GND

-0.5 to VDD +0.5

-0.5 to VDDQ +0.5

I/OP1

I/O

Terminal Voltage with

Respect to GND

VSS

VDDQ

I/O10

I/O5

I/O4

I/O11

(1)

Commercial

0 to +70

-40 to +85

-55 to +125

2.0

^oC

VSS

A⁽⁷⁾

(1)

Industrial

(2)

I/O

I/O12

I/O13

TBIAS

Temperature Under Bias

Storage Temperature

Power Dissipation

DC Output Current

VDDQ

DDQ

TSTG

I/O14

I/O15

I/OP2

I/O1

I/O0

IOUT

VSS

DDQ

VDDQ

5298 tbl 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5298 drw 02a

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;

however, the voltage on any input or I/O pin cannot exceed VDDQ during power

supply ramp up.

Top View

100 TQFP

NOTES:

1. Pins 14 and 66 do not have to be connected directly to VSS as long as the

input voltage is < VIL.

7. TA is the “instant on” case temperature.

2. Pin 16 does not have to be connected directly to VDD as long as the input

voltage is >VIH.

3. Pin 84 is reserved for a future 16M.

4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective

JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows

these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).

100 TQFP Capacitance⁽¹⁾

119 BGA Capacitance⁽¹⁾

Symbol

Parameter⁽¹⁾

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

Symbol

Parameter⁽¹⁾

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

CIN

Input Capacitance

I/O Capacitance

CIN

Input Capacitance

I/O Capacitance

CI/O

5298 tbl 07

5298 tbl 07a

165 fBGA Capacitance⁽¹⁾

Symbol

Parameter⁽¹⁾

Conditions

VIN = 3dV

Max. Unit

CIN

Input Capacitance

I/O Capacitance

TBD

CI/O

VOUT = 3dV

5298 tbl 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.462

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration — 256K x 36, 119 BGA

DDQ

NC(3)

ADV/LD

CE2

I/O

DDQ

I/O

DDQ

I/O

A17

BW3

I/O

R/W

DDQ

DD(2)

SS(1)

I/O

CLK

I/O

DDQ

I/O

DDQ

CEN

I/O

VSS(1)

DDQ

LBO

(4)

DDQ

DNU

5298 drw 13a

Top View

Pin Configuration — 512K x 18, 119 BGA

DDQ

NC(3)

CE2

I/O

ADV/LD

I/O

DDQ

I/O

DDQ

I/O

A18

I/O

DDQ

R/W

DD(2)

SS(1)

DDQ

I/O

CLK

I/O

DDQ

I/O

CEN

I/O

DDQ

SS(1)

LBO

(4)

DDQ

5298 drw 13b

DNU

Top View

NOTES:

1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.

2. J3 does not have to be connected directly to VDD as long as the input voltage is ≥ VIH.

3. A4 is reserved for future 16M.

4. DNU = Do not use; Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. The current die revision allows

these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration — 256K x 36, 165 fBGA

NC⁽³⁾

ADV/LD

CEN

R/W

CLK

NC⁽³⁾

I/OP2

I/O14

I/O12

I/O10

BW4

BW1

I/OP3

I/O17

I/O19

I/O21

I/O23

DDQ

I/O16

I/O18

I/O20

I/O22

I/O15

I/O13

I/O11

I/O

I/O8

SS⁽¹⁾

DD⁽²⁾

I/O24

I/O26

I/O28

I/O30

I/O25

I/O27

I/O29

I/O31

I/OP4

DDQ

I/O

DNU⁽⁴⁾

SS⁽¹⁾

I/OP1

NC⁽³⁾

DNU⁽⁴⁾

A16

LBO

5298 tbl 25a

Pin Configuration — 512K x 18, 165 fBGA

(3)

ADV/LD

A10

CE1

CEN

R/W

(3)

CLK

BW1

DDQ

I/OP1

I/O

I/O7

I/O6

I/O5

I/O4

I/O

I/O10

I/O11

SS⁽¹⁾

I/O12

I/O13

I/O14

I/O15

I/OP2

DD⁽²⁾

DDQ

I/O

I/O1

I/O

DNU⁽⁴⁾

SS⁽¹⁾

DNU⁽⁴⁾

(3)

LBO

5298 tbl25b

NOTES:

1. Pins H1 and N7 do not have to be connected directly to VSS as long as the input voltage is < VIL.

2. Pin H2 does not have to be connected directly to VDD as long as the input voltage is > VIH.

3. Pin B9, B11, A1, R2 and P2 are reserved for a future 18M, 36M, 72M, 144M and 288M respectively.

4. DNU = Do not use. Pins P5, R5, P7, R7 and N5 are reserved for respective JTAG pins: TDI, TMS, TDO, TCK and TRST on future revisions. The current die

revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).

6.482

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Synchronous Truth Table⁽¹⁾

(5)

R/W

ADV/LD

BWx

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(One cycle later)

CEN

CE2

Valid

External

Internal

LOAD WRITE

LOAD READ

D⁽⁷⁾

Q⁽⁷⁾

D⁽⁷⁾

Valid

LOAD WRITE /

BURST WRITE

(Advance burst counter)⁽²⁾

Internal

LOAD READ /

BURST READ

(Advance burst counter)⁽²⁾

Q⁽⁷⁾

DESELECT or STOP⁽³⁾

NOOP

HIZ

DESELECT / NOOP

SUSPEND⁽⁴⁾

Previous Value

5298 tbl 08

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will

tri-state one cycle after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propagating through the part. The state of all the internal registers and the

I/Osremainsunchanged.

5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z during device power-up.

7. Q - data read from the device, D - data written to the device.

Partial Truth Table for Writes⁽¹⁾

OPERATION

(3)

R/W

BW1

BW2

BW3

BW4

READ

WRITE ALL BYTES

WRITE BYTE 1 (I/O[0:7], I/OP1)⁽²⁾

WRITE BYTE 2 (I/O[8:15], I/OP2)⁽²⁾

WRITE BYTE 3 (I/O[16:23], I/OP3)^(2,3)

WRITE BYTE 4 (I/O[24:31], I/OP4)^(2,3)

NO WRITE

5298 tbl 09

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for x18 configuration.

Interleaved Burst Sequence Table (LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

5298 tbl 10

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Linear Burst Sequence Table (LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

5298 tbl 11

NOTE:

1. UponcompletionoftheBurstsequencethecounterwrapsaroundtoitsinitialstateandcontinuescounting.

Functional Timing Diagram⁽¹⁾

CYCLE

n+29

n+30

n+31

n+32

n+33

n+34

n+35

n+36

n+37

CLOCK

(2)

ADDRESS

A29

C29

A30

C30

A31

C31

A32

C32

A33

C33

A34

C34

A35

C35

A36

C36

A37

C37

(A0 - A17)

CONTROL

(R/W, ADV/LD, BWx)

(2)

DATA

D/Q28

D/Q29

D/Q30

D/Q31

D/Q32

D/Q33

D/Q34

D/Q35

D/Q36

I/O [0:31], I/O P[1:4]

5298 drw 03

NOTES:

1. This assumes CEN, CE1, CE2 and CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

6.1402

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles⁽²⁾

(1)

Cycle

Address

R/W

ADV/LD

I/O

Comments

CEN

BWx

Load read

Burst read

n+1

n+2

Q0+1 Load read

n+3

Q¹Deselect or STOP

n+4

NOOP

n+5

Load read

Burst read

n+6

n+7

Q2+1 Deselect or STOP

n+8

Load write

Burst write

Load write

Deselect or STOP

NOOP

n+9

n+10

n+11

n+12

n+13

n+14

n+15

n+16

n+17

n+18

n+19

D3+1

Load write

Load read

Load write

Burst write

Load read

Burst read

D7+1

Q8+1 Load write

5298 tbl 12

NOTES:

1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

2. H = High; L = Low; X = Don't Care; Z = High Impedence.

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Read Operation⁽¹⁾

(2)

Cycle

Address

R/W

ADV/LD

I/O

Comments

CEN

BWx

Address and Control meet setup

n+1

Contents of Address A0 Read Out

5298 tbl 13

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Burst Read Operation⁽¹⁾

(2)

Cycle

Address

R/W

ADV/LD

I/O

Comments

CEN

BWx

Address and Control meet setup

Address A Read Out, Inc. Count

n+1

n+2

n+3

n+4

n+5

n+6

n+7

Q0+1

Address A0+1 Read Out, Inc. Count

Address A0+2 Read Out, Inc. Count

0+2

0+3

Address A0+3 Read Out, Load A1

Address A

Read Out, Inc. Count

Q1+1

Address A1+1 Read Out, Load A2

5298 tbl 14

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Write Operation⁽¹⁾

(2)

Cycle

Address

R/W

ADV/LD

I/O

Comments

CEN

BWx

Address and Control meet setup

n+1

Write to Address A0

5298 tbl 15

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Burst Write Operation⁽¹⁾

(2)

Cycle

Address

R/W

ADV/LD

I/O

Comments

CEN

BWx

Address and Control meet setup

Address A Write, Inc. Count

n+1

n+2

n+3

n+4

n+5

n+6

n+7

D0+1

Address A0+1 Write, Inc. Count

Address A0+2 Write, Inc. Count

0+2

0+3

Address A0+3 Write, Load A1

Address A

Write, Inc. Count

D1+1

Address A1+1 Write, Load A2

5298 tbl 16

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

6.1422

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Read Operation with Clock Enable Used⁽¹⁾

(2)

Cycle

Address

R/W

ADV/LD

I/O

Comments

CEN

BWx

AddressA

Clock n+1 Ignored

Address A Read out, Load A

0 and Control meet setup

n+1

n+2

n+3

n+4

n+5

n+6

n+7

Clock Ignored. Data Q

is on the bus.

Clock Ignored. Data Q

Address A

Read out, Load A

5298 tbl 17

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Write Operation with Clock Enable Used⁽¹⁾

(2)

Cycle

Address

R/W

ADV/LD

I/O

Comments

CEN

BWx

CE1

Address A0 and Control meet setup.

Clock n+1 Ignored.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

Write data D0, Load A1.

Clock Ignored.

Write Data D1, Load A2

Write Data D2, Load A3

Write Data D3, Load A4

5298 tbl 18

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Read Operation with Chip Enable Used⁽¹⁾

I/O⁽³⁾

(2)

Cycle

Address

R/W

ADV/LD

Comments

CEN

BWx

Deselected.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

Address A

and Control meet setup.

read out, Deselected.

and Control meet setup.

read out, Deselected.

Deselected.

Address A

and Control meet setup.

read out, Deselected.

Deselected.

5298 tbl 19

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

3. Device outputs are ensured to be in High-Z during device power-up.

Write Operation with Chip Enable Used⁽¹⁾

CE⁽²⁾

Cycle

Address

R/W

ADV/LD

I/O

Comments

CEN

BWx

Deselected.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

Address A

Data D

Address A

Data D Write In, Deselected.

Deselected.

Address A

Data D Write In, Deselected.

Deselected.

and Control meet setup

Write In, Deselected.

and Control meet setup

2 and Control meet setup

5298 tbl 20

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.1442

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V±5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

DD = Max., VIN = 0V to VDD

µA

LBO Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

___

|I^LI

DD = Max., VIN = 0V to VDD

OUT = 0V to VCC

µA

|I^LO

IOL = +8mA, VDD = Min.

0.4

___

Output High Voltage

IOH = -8mA, VDD = Min.

2.4

5298 tbl 21

NOTE:

1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾(VDD = 3.3V±5%)

7.5ns

8ns

8.5ns

Com'l

Symbol

Parameter

Test Conditions

Unit

Com'l

Ind

Com'l

Ind

Operating Power

Device Selected, Outputs Open,

Supply Current

ADV/LD = X, V^DD= Max.,

275

295

250

270

225

245

(2)

VIN > VIH or < VIL, f = fMAX

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open,

DD = Max., VIN > VHD or < VLD

f = 0^(2,3)

SB1

125

120

115

Clock Running Power

Supply Current

Device Deselected, Outputs Open,

DD = Max., VIN > VHD or < VLD

SB2

SB3

105

100

(2,3)

f = f^MAX

Idle Power

Supply Current

Device Selected, Outputs Open,

CEN > VIH, VDD = Max.,

(2,3)

VIN > VHD or < VLD, f = fMAX

Full Sleep Mode

Supply Current

Device Selected, Outputs Open,

CEN < VIL, VDD = Max., ZZ > VHD

(2,3)

VIN > VHD or < VLD, f = fMAX

5298 tbl 22

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.

AC Test Conditions

Input Pulse Levels

AC Test Load

DDQ/2

0 to 3V

2ns

50Ω

Input Rise/Fall Times

I/O

Z0 = 50Ω

5298 drw 04

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V

Figure 1. AC Test Load

1.5V

Figure 1

•

5298 tbl 23

∆tCD

(Typical, ns)

•

20 30 50

80 100

Capacitance (pF)

200

5298 drw 05

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)

7.5ns

8ns

8.5ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

t^CYC

Clock Cycle Time

2.5

10.5

2.7

3.0

(1)

Clock High Pulse Width

Clock Low Pulse Width

t^CH

____

(1)

2.7

t^CL

Output Parameters

____

t^CD

Clock High to Valid Data

7.5

8.5

____

t^CDC

Clock High to Data Change

Clock High to Output Active

Clock High to Data High-Z

Output Enable Access Time

____

(2, 3,4)

t^CLZ

____

(2, 3,4)

t^CHZ

____

t^OE

____

(2,3)

Output Enable Low to Data Active

Output Enable High to Data High-Z

t^OLZ

____

t^OHZ

Set Up Times

____

t^SE

Clock Enable Setup Time

2.0

tSA

Address Setup Time

t^SD

Data In Setup Time

t^SW

Read/Write (R/W) Setup Time

Advance/Load (ADV/LD) Setup Time

Chip Enable/Select Setup Time

Byte Write Enable (BWx) Setup Time

tSADV

t^SC

tSB

Hold Times

t^HE

____

Clock Enable Hold Time

0.5

t^HA

Address Hold Time

t^HD

Data In Hold Time

t^HW

Read/Write (R/W) Hold Time

Advance/Load (ADV/LD) Hold Time

Chip Enable/Select Hold Time

Byte Write Enable (BWx) Hold Time

tHADV

tHC

t^HB

5298 tbl 24

NOTES:

1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.

2. Transition is measured 200mV from steady-state.

3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.

4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.

The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,

which is a Max. parameter (worse case at 70 deg. C, 3.135V).

6.1462

tCYC

CLK

tCH

tCL

tSE

tHE

CEN

tSADV

tHADV

ADV/

tSW

tSA

tHW

tHA

R/W

ADDRESS

tSC

tHC

(2)

CE1, CE2

BW BW

1 -

(CEN high, eliminates

current L-H clock edge)

(Burst Wraps around

to initial state)

tCD

tCDC

tCD

tCLZ

tCHZ

Q(A2+1)

Q(A2+3)

tCDC

Q(A2+2)

Q(A1)

Q(A2)

DATAOUT

Q(A2)

Burst Read

Read

5298 drw 06

NOTES:

1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence

of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBOinput.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.

4. R/Wis don’t care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/Wsignal when new address and control are

loadedintotheSRAM.

tCYC

CLK

tCH

tCL

tSE

tHE

CEN

tSADV

tHADV

ADV/LD

tSW

tHW

R/W

tSA

tHA

ADDRESS

tSC

tHC

(2)

CE1, CE2

tSB

tHB

B(A2+1

)

B(A2+3

)

B(A2+2

)

B(A2)

B(A1)

BW1 - BW4

(CEN high, eliminates

(Burst Wraps around

to initial state)

tHD

tSD

tHD

tSD

current L-H clock edge)

D(A2+1

)

D(A2+2

)

D(A2)

D(A2+3)

D(A1)

DATAIN

Burst Write

Write

5298 drw 07c

NOTES:

1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base

address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.

4. R/Wisdon’tcarewhentheSRAMisbursting(ADV/LD sampledHIGH). Thenatureoftheburstaccess(ReadorWrite)isfixedbythestateoftheR/W signalwhennewaddressandcontrolare

loadedintotheSRAM.

5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one

cycle before the actual data is presented to the SRAM.

NOTES:

1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one

cycle before the actual data is presented to the SRAM.

NOTES:

1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur.

All internal registers in the SRAM will retain their previous state.

4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one

cycle before the actual data is presented to the SRAM.

NOTES:

1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the

deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.

4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one

cycle before the actual data is presented to the SRAM.

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of OE Operation⁽¹⁾

NOTE:

1. A read operation is assumed to be in progress.

Ordering Information

NOTE:

1. 71V65703 only.

6.2422

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with

3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Datasheet Document History

12/31/99

04/20/00

Created new part number and datasheet from 71V657/59 to 71v65703/5903

Pg.5,6

AddJTAGresetpinstoTQFPpinconfiguration;removedfootnote

AddclarificationnotetoRecommendedOperatingTemperatureandAbsoluteMaxRatingstables

AddnotetoBGApinconfiguration;correctedtypowithinpinout

InsertTQFPPackageDiagramOutline

Pg. 7

Pg. 21

05/23/00

07/28/00

Add new package offering: 13mm x 15mm, 165 fine pitch ball grid array

Correction on 119 Ball Grid Array Package diagram Outline

Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and

IDT71V658xx device errata sheet

Pg. 23

Pg. 5-8

Pg. 7,8

Pg. 23

Pg. 8

Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout

UpdateBG119packagediagramdimensions

Add reference note to pin N5 on the BQ165 pinout, reserved for JTAG TRST

AddIzztoDCElectricalCharacteristics

11/04/00

Pg. 15

12/04/02 Pg. 1-25

Changed datasheet from Preliminary to final release

Pg. 5,6,15,16,25 Added I temp to datasheet

12/18/02 Pg. 1,2,5,6,7,8

Pg. 7

10/16/14 Pg. 1

Pg. 15

Removed JTAG functionality for current die revision

Corrected pin configuration on the x36, 119 BGA. Switched pins I/O0 and I/OP1.

Added green availability to Features and corrected a typo

DC Electrical Chars Table corrected typos for IDD in the Industrial Temp range for the

8.0ns & 8.5ns speed grades

Pg. 22

Removed IDT from and added green and T&R indicators to the ordering information

Added footnote annotation to 75 access speed in the ordering information table

(1)

Added the corresponding footnote to the text “71V65703 only”.

CORPORATE HEADQUARTERS

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for SALES:

for Tech Support:

sramhelp@idt.com

408-284-4532

800-345-7015 or 408-284-8200

fax:408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

IDT71V6590385PFGI [IDT]

相关型号：

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IDT71V65903S75BG

IDT71V65903S75BG8

IDT71V65903S75BGG

IDT71V65903S75BGI

IDT71V65903S75BQ

IDT71V65903S75BQGI

IDT71V65903S75BQI

IDT71V65903S75PF

IDT71V65903S75PF8

IDT71V65903S75PFG

IDT71V65903S75PFG8