IDT71V67703S75BQI [IDT]
256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect; 256K X 36 , 512K X 18 3.3V同步SRAM 3.3VI / O ,突发流量计数器,通过输出,单周期取消型号: | IDT71V67703S75BQI |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect |
文件: | 总23页 (文件大小:976K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
256K X 36, 512K X 18
3.3VSynchronousSRAMs
IDT71V67703
IDT71V67903
3.3V I/O, Burst Counter
Flow-ThroughOutputs,SingleCycleDeselect
Features
data, address and control registers. There are no registers in the data
outputpath(flow-througharchitecture). InternallogicallowstheSRAMto
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil
theendofthewritecycle.
◆
256K x 36, 512K x 18 memory configurations
◆
Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V67703/7903canprovidefourcyclesof
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe
next three rising clock edges. The order of these three addresses are
definedbytheinternalburstcounterandtheLBO inputpin.
◆
LBO input selects interleaved or linear burst mode
◆
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite
enable (BWE), and byte writes (BWx)
◆
3.3V core power supply
◆
Power down controlled by ZZ input
3.3V I/O supply (VDDQ)
Packaged in a JEDEC Standard 100-pin thin plastic quad
◆
◆
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball
grid array (fBGA).
TheIDT71V67703/7903SRAMsutilizeIDT’slatesthigh-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
Description
The IDT71V67703/7903 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS0, CS1
OE
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
GW
BWE
(1)
BW1, BW2, BW3, BW4
CLK
Clock
Input
Input
Input
Input
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
ADV
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
N/A
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Ground
Supply
Supply
VSS
N/A
5309 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67903.
DECEMBER 2003
1
©2002IntegratedDeviceTechnology,Inc.
DSC-5309/05
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
ADSC
ADSP
ADV
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses.
is gated by
.
CE
ADSP
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BWE
Individual Byte
Write Enables
I
I
I
LOW
LOW
N/A
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
Any active byte write causes all outputs to be disabled.
BW1-BW4
CE
Chip Enable
Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V67703/7903.
CE also gates ADSP.
CLK
Clock
This is the clock input. All timing references for the device are made with respect to this
input.
CS0
CS1
GW
Chip Select 0
Chip Select 1
I
I
I
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by
the rising edge of CLK. The data output path is flow-through (no output register).
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
OE
VDD
VDDQ
VSS
NC
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
1
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
N/A
Ground.
No Connect
Sleep Mode
N/A
NC pins are not electrically connected to the device.
ZZ
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down
the IDT71V67703/7903 to its lowest power consumption level. Data retention is guaranteed
in Sleep Mode.
5309 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
256K x 36/
512K x 18-
BIT
MEMORY
ARRAY
CLK
2
Burst
Logic
18/19
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
CLR
ADSP
2
CLK EN
A ,A
0
1
A2 - A18
ADDRESS
REGISTER
A0–A17/18
G W
36/18
36/18
18/19
BW E
Byte 1
Write Register
Byte 1
Write Driver
1
BW
9
9
Byte 2
Write Register
Byte 2
Write Driver
2
BW
Byte 3
Write Register
Byte 3
Write Driver
3
BW
9
9
Byte 4
Write Register
Byte 4
Write Driver
4
BW
CE
CS0
CS1
Q
D
Enable
DATA INPUT
REGISTER
Register
CLK EN
ZZ
Powerdown
OE
OUTPUT
BUFFER
O E
,
36/18
I/O0–I/O31
I/OP1–I/OP4
5309 drw 01
6.42
3
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureSupplyVoltage
Symbol
Rating
Commercial
Unit
(2)
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
VSS
0V
0V
VDD
VDDQ
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
3.3V±5%
3.3V±5%
3.3V±5%
(3,6)
TERM
V
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
3.3V±5%
5309 tbl 04
(4,6)
VTERM
Terminal Voltage with
Respect to GND
NOTE:
1. TA is the "instant on" case temperature.
(5,6)
VTERM
Terminal Voltage with
Respect to GND
V
RecommendedDCOperating
Conditions
oC
oC
oC
W
(7)
TA
Operating Temperature
Symbol
Parameter
Min. Typ.
3.135 3.3
3.135 3.3
Max.
3.465
3.465
0
Unit
V
Temperature
Under Bias
-55 to +125
TBIAS
VDD Core Supply Voltage
VDDQ I/O Supply Voltage
V
Storage
Temperature
-55 to +125
TSTG
VSS
VIH
Supply Voltage
0
0
V
PT
Power Dissipation
DC Output Current
2.0
50
____
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
VDD +0.3
VDDQ +0.3
0.8
V
V
IOUT
mA
____
____
VIH
2.0
5309 tbl 03
VIL
-0.3(1 )
V
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
5309 tbl 05
NOTE:
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
165fBGACapacitance
(TA = +25° C, f = 1.0MHz)
100-PinTQFPCapacitance
(TA = +25° C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
7
7
pF
5
7
pF
CI/O
pF
CI/O
pF
5309 tbl 07b
5309 tbl 07
119BGACapacitance
(TA = +25° C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
7
7
pF
CI/O
pF
5309 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.442
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/OP3
2
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
3
4
5
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
I/O22
I/O23
(1)
VSS
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
,
I/O0
I/OP1
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5309 drw 02a
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 512K x 18, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
2
3
4
5
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
(1)
VSS
VDD
NC
VSS
VDD
ZZ(2)
I/O3
I/O2
VDDQ
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
,
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5309 drw 02b
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.462
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
ADSP
ADSC
(4)
3
2
9
A17
15
CS
NC
NC
NC
NC
0
7
DD
12
A
A
V
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
CE
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
DDQ
19
I/O
12
I/O
DDQ
V
V
OE
20
22
21
3
2
BW
11
10
I/O
I/O
I/O
I/O
G
H
J
BW
ADV
GW
23
I/O
SS
SS
9
I/O
8
I/O
I/O
V
V
DDQ
DD
DD
V
DD
DDQ
V
NC
V
V
NC
V
24
25
26
SS
SS
6
7
I/O
I/O
I/O
V
CLK
NC
V
I/O
K
L
27
I/O
4
1
BW
4
I/O
5
I/O
I/O
BW
DDQ
28
SS
SS
SS
SS
SS
3
DDQ
V
V
I/O
V
V
V
V
V
V
V
I/O
M
N
P
R
T
BWE
29
31
30
I/O
SS
SS
1
A
2
I/O
1
0
I/O
I/O
P4
0
A
I/O
I/O
I/OP1
I/O
(1)
5
DD
13
A
NC
A
V
NC
LBO
(2)
10
11
14
NC
NC
A
A
A
NC
ZZ
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DDQ
DDQ
V
U
V
5309 drw 02c
Top View
Pin Configuration 512K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
ADSP
ADSC
(4)
3
2
9
A18
NC
NC
CS
NC
NC
NC
0
7
DD
V
13
A
17
A
A
8
I/O
SS
SS
SS
2
SS
SS
SS
SS
SS
P1
I/O
NC
V
V
V
NC
CE
V
V
V
V
V
9
7
I/O
NC
DDQ
I/O
NC
NC
6
I/O
DDQ
V
V
OE
10
5
I/O
G
H
J
NC
I/O
NC
NC
BW
ADV
GW
11
I/O
SS
4
I/O
V
NC
DDQ
DD
DD
DD
DDQ
V
V
V
V
NC
V
NC
12
SS
SS
SS
3
K
L
NC
I/O
NC
V
V
CLK
NC
V
NC
I/O
13
I/O
1
BW
2
I/O
NC
DDQ
14
SS
SS
SS
SS
SS
SS
DDQ
V
M
N
P
R
T
V
I/O
NC
V
V
V
V
V
V
V
A
NC
BWE
15
1
A
1
I/O
I/O
NC
NC
P2
0
A
0
I/O
I/O
NC
(1)
5
DD
SS
12
11
NC
NC
A
V
A
A
NC
LBO
(2)
10
15
14
A
A
NC
ZZ
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DDQ
DNU(3)
DDQ
V
U
V
5309 drw 02d
,
Top View
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. T7 can be left unconnected and the device will always remain in active mode.
3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
4. On future 18M devices CS0 will be removed, B2 will be used for address expansion.
6.42
7
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(3)
A
B
C
D
E
F
NC
A
A
NC
7
8
CE
BW
BW
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
3
2
(3)
NC
A
6
CS
0
CLK
A
9
NC
BW4
BW1
I/O
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
I/O
I/O
P2
P3
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
14
17
16
15
I/O
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
19
I/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
I/O
10
11
G
H
J
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
8
23
22
DDQ
DD
SS
SS
SS
DD
DDQ
9
(1)
(2)
V
SS
NC
I/O
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
I/O
ZZ
I/O
25
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
6
24
7
K
L
M
N
P
I/O
I/O
V
V
V
V
V
V
V
I/O
I/O
4
27
26
DDQ
DD
SS
SS
SS
DD
DDQ
5
I/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
I/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
(3)
I/O
P4
NC
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
I/O
P1
(3)
(4)
(4)
NC
LBO
NC
A
A
DNU
A
DNU
A
10
A
A
14
A
17
5
2
1
13
(3)
(4)
(4)
R
NC
A
A
DNU
A
DNU
A
A
A
15
A
16
4
3
0
11
12
5309tbl 17a
Pin Configuration 512K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(3)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
NC
A
A
10
7
8
CE
BW
CS
BWE
GW
ADSC
OE
ADV
2
1
(3)
A
6
CS
NC
CLK
A
9
NC
0
BW
ADSP
1
NC
I/O
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
I/O
P1
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
8
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
6
9
I/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
G
H
J
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
4
11
(1)
(2)
V
NC
NC
NC
NC
NC
NC
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZZ
SS
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
NC
NC
NC
NC
NC
12
K
L
M
N
P
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
13
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
14
I/O
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
15
(3)
I/O
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
P2
(3)
(4)
(4)
NC
LBO
NC
A
5
A
2
DNU
A
1
DNU
A
11
A
14
A
15
A
18
(3)
(4)
(4)
R
NC
A
4
A
3
DNU
A
0
DNU
A
12
A
13
A
16
A
17
5309 tbl 17b
NOTES:
1. H1 does not have to be directly connected to VSS, as long as the input voltage is < VIL.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
6.482
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1 )
___
___
___
LBO Input Leakage Current
|ILI|
VDD = Max., VIN = 0V to VDD
VOUT = 0V to VCC
30
5
µA
µA
V
|ILO|
VOL
VOH
Output Leakage Current
Output Low Voltage
Output High Voltage
IOL = +8mA, VDD = Min.
IOH = -8mA, VDD = Min.
0.4
___
2.4
V
5309 tbl 08
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ in will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1)
7.5ns
8ns
Com'l
8.5ns
Com'l
Unit
Symbol
Parameter
Test Conditions
Com'l
Ind
285
70
Ind
230
70
Ind
210
70
Operating Power Supply Current
Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
mA
DD
I
(2)
265
50
210
50
190
50
ISB1
ISB2
IZZ
CMOS Standby Power Supply Current Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
mA
mA
Clock Running Power Supply Current Device Deselected, Outputs Open, VDD = Max.,
(2,.3)
VDDQ = Max., VIN > VHD or < VLD, f = fMAX
145
50
165
70
140
50
160
70
135
50
155
70
Full Sleep Mode Supply Current
ZZ > VHD, VDD = Max.
mA
5309 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
(VDDQ = 3.3V/2.5V)
AC Test Load
V
DDQ/2
50Ω
Input Pulse Levels
0 to 3V
2ns
I/O
Z = 50Ω
0
Input Rise/Fall Times
,
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
5309 drw 03
1.5V
6
5
4
3
See Figure 1
Figure 1. AC Test Load
5309 tbl 10
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
,
5309 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,3)
CE
CS1 ADSP ADSC ADV
GW BWE BWx OE(2)
Operation
Address
Used
CS0
CLK
I/O
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
DOUT
HI-Z
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Read Cycle, Begin Burst
L
L
L
H
L
OUT
D
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
Read Cycle, Begin Burst
L
L
L
L
DOUT
HI-Z
DIN
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
Write Cycle, Begin Burst
L
L
L
L
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
X
X
X
X
L
Next
L
Next
L
X
L
X
L
DIN
Next
L
H
L
DIN
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
H
L
H
L
H
L
H
X
X
X
X
X
L
X
L
DIN
H
L
DIN
X
X
DIN
5309 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ - low for the table.
6.1402
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table (1, 2)
Operation
GW
H
H
L
BWE
H
L
BW1
BW2
X
BW3
X
BW4
X
Read
X
Read
H
H
H
H
Write all Bytes
Write all Bytes
X
L
X
X
X
X
H
H
H
H
H
L
L
L
L
(3)
Write Byte 1
L
L
H
H
H
(3)
Write Byte 2
L
H
L
H
H
(3)
Write Byte 3
L
H
H
L
H
(3)
Write Byte 4
L
H
H
H
L
5309 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67903.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
ZZ
I/O Status
Power
OE
Read
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
5309 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table ( LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
5309 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table ( LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5309 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 3.3V ±5%, Commercial and Industrial
Temperature Ranges)
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
Clock Parameter
____
____
____
____
____
____
tCY C
Clock Cycle Time
8.5
3
10
4
11.5
4.5
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
tCH
____
____
____
(1)
3
4
4.5
tCL
Output Parameters
____
____
____
tCD
Clock High to Valid Data
7.5
8
8.5
ns
ns
ns
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
Output Enable Low to Output Active
2
0
2
0
2
0
(2)
____
____
____
tCL Z
(2)
2
3.5
2
3.5
2
3.5
ns
ns
ns
ns
tCHZ
____
____
____
tOE
3.5
3.5
3.5
____
____
____
(2)
0
0
0
tOLZ
____
____
____
(2)
Output Enable High to Output High-Z
3.5
3.5
3.5
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSA
tSS
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
2
2
2
2
2
2
2
2
2
2
2
2
ns
ns
ns
ns
ns
ns
Address Status Setup Time
Data In Setup Time
tSD
tSW
tSAV
tSC
Write Setup Time
Address Advance Setup Time
Chip Enable/Select Setup Time
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
tHS
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Address Status Hold Time
Data In Hold Time
tHD
tHW
tHAV
tHC
Write Hold Time
Address Advance Hold Time
Chip Enable/Select Hold Time
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
____
____
____
tZZPW
ZZ Pulse Width
100
100
34
100
100
40
100
100
50
ns
ns
(3)
tZZR
ZZ Recovery Time
Configuration Set-up Time
tCFG(4)
ns
5309 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.1422
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Flow-Through Read Cycle (1,2)
,
6.42
13
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
,
6.1442
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
(1,2,3)
Timing Waveform of Write Cycle No. 1 - GW Controlled
,
6.42
15
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled (1,2,3)
,
6.1462
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
,
6.42
17
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW , BW E, BW x
CE, CS1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
5309 drw 10
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
5309 drw 11
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.1482
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.42
19
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.2402
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
21
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
IDT XXX
S
XX
X
X
Process/
Temperature Rance
Device
Type
Power
Speed
Package
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
PF
BG
BQ
100-Pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 fine pitch Ball Grid Array (fBGA)
75
80
85
Access Time in Tenths of Nanoseconds
71V67703 256K x 36 Flow-Through Burst Synchronous SRAM
71V67903 512K x 18 Flow-Through Burst Synchronous SRAM
,
5309 drw 12
6.2422
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
04/26/00
CreatedDatasheetfrom71V677and71V679Datasheets
For2.5VI/Ooffering, see 71V67702AND71V67902Datasheets.
AddcapacitanceforBGApackage;InsertclarificationnotetoAbsoluteMaxRatingsandRecommended
OperatingTemperaturetables.
Pg. 4
Pg. 7
Pg. 18
Replace PinU6withTRST pininBGApinconfiguration;Addpindescriptionnote inpinout
Inserted100pinTQFPPackageDiagramOutline
05/24/00
07/12/00
Pg. 1,4,8,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correctnote 2on BGA and TQFP pinconfiguration
Pg. 20
Pg. 5,6,8
Pg. 7
Pg. 20
Pg. 9
Correctioninthe119BGAPackageDiagramOutline
RemovenotefromTQFPandBQ165pinouts
Add/RemovenotefromBG119pinout
UpdateBG119pinout
12/18/00
10/29/01
UpdatedISB2levels for7.5-8.5ns.
Pg. 1,2
Pg. 7
RemoveJTAGpins
Changed U2-U6 pins to DNU.
Pg. 8
Pg. 9
Pg. 1-23
Changed P5,P7,R5 & R7 to DNU pins.
Raised specs by 10mA on 7.5ns, 8ns and 8.5ns.
ChangeddatasheetfromAdvancedtoFinalRelease.
10/22/02
Pg. 4,9,12, AddedItemptodatasheet.
22
04/15/03
12/20/03
Pg. 4
Pg. 7
Updated165fBGAtablefromTBDto7.
Updated 119BGS pin configurations- reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7,
H6, G7, F6, E7, D6 (256K x 18).
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
sramhelp@idt.com
800-544-7726
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
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