IDT7207L15DB_技术文档

CMOS ASYNCHRONOUS FIFO

32,768 x 9

IDT7207

Integrated Device Technology, Inc.

DESCRIPTION:

FEATURES:

The IDT7207 is a monolithic dual-port memory buffer with

internal pointers that load and empty data on a first-in/first-out

basis. The device uses Full and Empty flags to prevent data

overflow and underflow and expansion logic to allow for

unlimited expansion capability in both word size and depth.

Data is toggled in and out of the device through the use of

the Write (W) and Read (R) pins.

The devices 9-bit width provides a bit for a control or parity

at the user’s option. It also features a Retransmit (RT) capa-

bilitythatallowsthereadpointertoberesettoitsinitialposition

when RT is pulsed LOW. A Half-Full Flag is available in the

single device and width expansion modes.

• 32768 x 9 storage capacity

• High-speed: 15ns access time

• Low power consumption

— Active: 660mW (max.)

— Power-down: 44mW (max.)

• Asynchronous and simultaneous read and write

• Fully expandable in both word depth and width

• Pin and functionally compatible with IDT720x family

• Status Flags: Empty, Half-Full, Full

• Retransmit capability

• High-performance CMOS technology

• Military product compliant to MIL-STD-883, Class B

• Industrial temperature range (-40^oC to +85^oC) is avail-

able, tested to military electrical specifications

The IDT7207 is fabricated using IDT’s high-speed CMOS

technology. It is designed for applications requiring asynchro-

nous and simultaneous read/writes in multiprocessing, rate

buffering, and other applications.

Military grade product is manufactured in compliance with

the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

(D₀–D ₈

)

WRITE

CONTROL

W

RAM ARRAY

32,768 x 9

WRITE

POINTER

READ

POINTER

THREE-

STATE

BUFFERS

RS

DATA OUTPUTS

(Q ₀

–Q₈

)

READ

CONTROL

RESET

LOGIC

R

FLAG

LOGIC

EF

FF

FL/RT

EXPANSION

LOGIC

XO/HF

XI

3140 drw 01

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1996

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

1996 Integrated Device Technology, Inc.

DSC-3140/2

5.05

1

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

INDEX

W

D ₈

D₃

D

D₁

D0

XI

FF

Q0

Q1

Q₂

Q 3

Q₈

1

2

3

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Vcc

D₄

D₅

5

29

28

27

26

25

24

23

22

21

D2

D1

D0

XI

FF

Q₀

Q1

NC

Q₂

D 6

D 7

NC

FL/RT

RS

EF

XO/HF

Q ₇

4

5

6

7

2

6

D₇

D

P28-1

D28-1

J32-1

&

L32-1

6

7

FL/RT

RS

EF

XO/HF

Q₇

8

9

8

9

10

11

12

13

10

11

12

13

14

Q6

5

Q

Q₄

R

GND

3140 drw 03

3140 drw 02

PLCC/LCC

TOP VIEW

DIP

TOP VIEW

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

Rating

Commercial

Military

Unit

Symbol

Parameter

Min.

Typ.

Max.

Unit

VTERM

Terminal

Voltage with

Respect to

GND

–0.5 to + 7.0

–0.5 to +7.0

V

VCCM

Military Supply

Voltage

4.5

5.0

5.5

V

VCCC

GND

Commercial Supply

Voltage

4.5

5.0

5.5

V

TA

Operating

Temperature

0 to +70

–55 to +125

–65 to +135

–65 to +155

50

° C

Supply Voltage

0

V

TBIAS

TSTG

IOUT

Temperature –55 to +125

Under Bias

(1)

VIH

Input High Voltage

Commercial

2.0

—

Storage

Temperature

–55 to + 125

° C

(1)

VIH

Input High Voltage

Military

2.2

—

V

DC Output

Current

50

mA

(1)

VIL

Input Low Voltage

Commercial and

Military

0.8

NOTE:

3140 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

onlyandfunctionaloperationofthedeviceattheseoranyotherconditions

abovethoseindicatedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

NOTE:

3140 tbl 02

1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS FOR THE 7207

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)

IDT7207

Commercial

IDT7207

Military

tA = 15, 20, 25, 35, 50 ns

tA = 20, 30, 50 ns

Symbol

Parameter

Min.

–1

Typ.

—

Max.

1

Min.

–1

Typ.

—

Max.

Unit

µA

V

(1)

ILI

Input Leakage Current (Any Input)

Output Leakage Current

1

(2)

ILO

–10

2.4

—

10

–10

2.4

—

10

—

VOH

VOL

Output Logic “1” Voltage IOH = –2mA

Output Logic “0” Voltage IOL = 8mA

Active Power Supply Current

—

0.4

120⁽⁴⁾

12

—

0.4

150⁽⁴⁾

V

(3)

ICC1

—

mA

(3)

ICC2

Standby Current (R=W=RS=FL/RT=VIH)

—

25

ICC3(L)⁽³⁾Power Down Current (All Input = VCC - 0.2V)

—

8

—

12

mA

NOTES:

3140 tbl 04

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3. ICC measurements are made with outputs open (only capacitive loading).

4. Tested at f = 20MHz.

5.05

2

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS⁽¹⁾

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Com'l

Com'l & Mil.

7207L20

Com'l

Military

Com'l

Com'l & Mil.

7207L50

7207L15

7207L25

7207L30

7207L35

Symbol

fS

Parameters

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Shift Frequency

—

25

—

10

15

5

40

—

15

—

15

—

25

15

—

15

25

—

15

—

30

—

10

20

5

33.3

—

20

—

15

—

30

20

—

20

30

—

20

—

35

—

10

25

5

28.5

—

25

—

18

—

35

25

—

25

35

—

25

—

40

—

10

30

5

25

—

30

—

20

—

40

30

—

30

40

—

30

—

45

—

10

35

5

22.2

—

35

—

20

—

45

30

—

30

45

—

35

—

65

—

15

50

10

15

5

15 MHz

tRC

Read Cycle Time

—

50

—

30

—

65

45

—

45

65

—

50

—

ns

tA

Access Time

tRR

Read Recovery Time

Read Pulse Width⁽²⁾

Read LOW to Data Bus LOW⁽³⁾

Write HIGH to Data Bus Low-Z^{(3, 4)}

Data Valid from Read HIGH

Read HIGH to Data Bus High-Z⁽³⁾

Write Cycle Time

Write Pulse Width⁽²⁾

Write Recovery Time

Data Set-up Time

tRPW

tRLZ

tWLZ

tDV

5

10

5

tRHZ

tWC

tWPW

tWR

tDS

—

25

15

10

11

0

—

30

20

10

12

0

—

35

25

10

15

0

—

40

30

10

18

0

—

45

35

10

18

0

—

65

50

15

30

5

tDH

Data Hold Time

tRSC

tRS

Reset Cycle Time

25

15

10

25

15

10

—

15

—

15

—

15

10

30

20

10

30

20

10

—

20

—

20

—

20

10

35

25

10

35

25

10

—

25

—

25

—

25

10

40

30

10

40

30

10

—

30

—

30

—

30

10

45

35

10

45

35

10

—

35

—

35

—

35

10

15

65

50

15

65

50

15

—

50

—

50

—

50

10

15

Reset Pulse Width⁽²⁾

Reset Set-up Time⁽³⁾

Reset Recovery Time

Retransmit Cycle Time

Retransmit Pulse Width⁽²⁾

Retransmit Set-up Time⁽³⁾

Retransmit Recovery Time

Reset to EF LOW

tRSS

tRTR

tRTC

tRT

tRTS

tRSR

tEFL

tHFH, tFFH Reset to HF and FF HIGH

tRTF

tREF

tRFF

tRPE

tWEF

tWFF

tWHF

tRHF

tWPF

tXOL

tXOH

tXI

Retransmit LOW to Flags Valid

Read LOW to EF LOW

Read HIGH to FF HIGH

Read Pulse Width after EF HIGH

Write HIGH to EF HIGH

Write LOW to FF LOW

Write LOW to HF Flag LOW

Read HIGH to HF Flag HIGH

Write Pulse Width after FF HIGH

Read/Write LOW to XO LOW

Read/Write HIGH to XO HIGH

XI Pulse Width⁽²⁾

tXIR

XI Recovery Time

tXIS

XI Set-up Time

NOTES:

3140 tbl 05

1. Timings referenced as in AC Test Conditions.

2. Pulse widths less than minimum are not allowed.

3. Values guaranteed by design, not currently tested.

4. Only applies to read data flow-through mode.

5.05

3

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

5V

Input Pulse Levels

GND to 3.0V

5ns

1.5V

See Figure 1

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.1KΩ

D.U.T.

3140 tbl 07

30pF*

680Ω

CAPACITANCE⁽¹⁾(TA = +25°C, f = 1.0 MHz)

Symbol

Parameter

Condition

VIN = 0V

Max. Unit

(1)

CIN

Input Capacitance

Output Capacitance

10

pF

OR EQUIVALENT CIRCUIT

3140 drw 04

(1,2)

COUT

VOUT = 0V

pF

Figure 1. Output Load

NOTES:

3140 tbl 08

1. This parameter is sampled and not 100% tested.

2. With output deselected.

*Includes jig and scope capacitances.

READ ENABLE ( ) — A read cycle is initiated on the falling

R

SIGNAL DESCRIPTIONS

Inputs:

edgeoftheReadEnable(R),providedtheEmptyFlag(EF)isnot

set. The data is accessed on a First-In/First-Out basis, inde-

pendentofanyongoingwriteoperations. AfterReadEnable(R)

goes HIGH, the Data Outputs (Q0 through Q8) will return to a

high-impedance condition until the next Read operation. When

all the data has been read from the FIFO, the Empty Flag (EF)

will go LOW, allowing the “final” read cycle but inhibiting further

read operations, with the data outputs remaining in a high-

impedancestate. Onceavalidwriteoperationhasbeenaccom-

plished, the Empty Flag (EF) will go HIGH after tWEF and a valid

Readcanthenbegin. WhentheFIFOisempty,theinternalread

pointer is blocked from Rso external changes will not affect the

FIFO when it is empty.

DATA IN (D0–D8) — Data inputs for 9-bit wide data.

Controls:

RESET ( ) — Reset is accomplished whenever the Reset

RS

(RS) input is taken to a LOW state. During reset, both internal

read and write pointers are set to the first location. A reset is

required after power-up before a write operation can take place.

Both the Read Enable ( ) and Write Enable ( ) inputs must

R

W

be in the HIGH state during the window shown in Figure 2

(i.e. tRSS before the rising edge of ) and should not

RS

change until tRSR after the rising edge of

FIRST LOAD/RETRANSMIT (

/

) — This is a dual-

FL RT

.

RS

purpose input. In the Depth Expansion Mode, this pin is

grounded to indicate that it is the first device loaded (see

Operating Modes). The Single Device Mode is initiated by

grounding the Expansion In (XI).

The IDT7207 can be made to retransmit data when the

RetransmitEnableControl(RT)inputispulsedLOW. Aretrans-

mit operation will set the internal read pointer to the first location

and will not affect the write pointer. The status of the Flags will

changedependingontherelativelocationsofthereadandwrite

pointers. Read Enable (R) and Write Enable (W) must be in the

HIGH state during retransmit. This feature is useful when less

than 32,768 writes are performed between resets. The retrans-

mit feature is not compatible with the Depth Expansion Mode.

WRITEENABLE( )—Awritecycleisinitiatedonthefalling

W

edge of this input if the Full Flag (FF) is not set. Data set-up and

hold times must be adhered-to, with respect to the rising edge

of the Write Enable (W). Data is stored in the RAM array

sequentially and independently of any on-going read operation.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (HF) will be set to LOW,

and will remain set until the difference between the write pointer

and read pointer is less-than or equal to one-half of the total

memory of the device. The Half-Full Flag (HF) is reset by the

rising edge of the read operation.

To prevent data overflow, the Full Flag (FF) will go LOW on

thefallingedgeofthelastwritesignal,whichinhibitsfurtherwrite

operations. Upon the completion of a valid read operation, the

Full Flag (FF) will go HIGH after tRFF, allowing a new valid write

to begin. When the FIFO is full, the internal write pointer is

blockedfromW,soexternalchangesinWwillnotaffecttheFIFO

when it is full.

EXPANSION IN ( ) — This input is a dual-purpose pin.

XI

Expansion In (XI) is grounded to indicate an operation in the

single device mode. Expansion In (XI) is connected to Expan-

sion Out (XO) of the previous device in the Depth Expansion or

Daisy-Chain Mode.

5.05

4

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

and will remain set until the difference between the write pointer

and read pointer is less than or equal to one half of the total

memory of the device. The Half-Full Flag (HF) is then reset by

the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is con-

nected to Expansion Out (XO) of the previous device. This

output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device

reaches the last location of memory. There will be an XO pulse

whentheWritepointerreachesthelastlocationofmemory, and

an additional XO pulse when the Read pointer reaches the last

location of memory.

Outputs:

FULLFLAG( )—TheFullFlag(FF)willgoLOW,inhibiting

FF

further write operations, when the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go

LOW after 32,768 writes.

EMPTY FLAG ( ) — The Empty Flag (EF) will go LOW,

inhibitingfurtherreadoperations, whenthereadpointerisequal

to the write pointer, indicating that the device is empty.

EF

EXPANSION OUT/HALF-FULL FLAG (

/

) — This is a

XO HF

dual-purpose output. In the single device mode, when Expan-

sionIn(XI)isgrounded,thisoutputactsasanindicationofahalf-

full memory.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (HF) will be set to LOW

DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-

bit wide data. These outputs are in a high-impedance condition

whenever Read (R) is in a HIGH state.

tRSC

t RS

RS

W

t _RSS

t _RSR

t _RSS

R

t _EFL

EF

t _HFH

, t _FFH

HF, FF

3140 drw 05

NOTE:

1. W and R = VIH around the rising edge of RS.

Figure 2. Reset

tRC

t RPW

t RR

t _A

t A

R

t_DV

t _RHZ

t _RLZ

DATA VALID

OUT

DATA

t _WC

VALID

Q₀–Q₈

OUT

t WPW

t WR

W

t _DS

DATA IN

t _DH

VALID

DATA IN

VALID

D0 –D8

3140 drw 06

Figure 3. Asynchronous Write and Read Operation

5.05

5

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IGNORED

WRITE

LAST WRITE

FIRST READ

R

W

t _WFF

t _RFF

FF

3140 drw 07

Figure 4. Full FlagTiming From Last Write to First Read

IGNORED

READ

LAST READ

FIRST WRITE

W

R

t

REF

t

WEF

EF

t

A

DATAOUT

VALID

3171 drw 08

Figure 5. Empty Flag Timing From Last Read to First Write

t

RTC

t _RT

RT

t _RTS

t _RTR

W,R

RTF

HF, EF, FF

FLAG VALID

3140 drw 09

NOTE:

1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.

Figure 6. Retransmit

5.05

6

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

W

EF

R

t

WEF

t

RPE

3140 drw 10

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.

R

FF

W

t _RFF

t _WPF

3140 drw 11

Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.

W

R

t _RHF

t WHF

HF

HALF-FULL OR LESS

MORE THAN HALF-FULL

HALF-FULL OR LESS

3140 drw 12

Figure 9. Half-Full Flag Timing

WRITE TO

LAST PHYSICAL

LOCATION

W

R

READ FROM

LAST PHYSICAL

LOCATION

t _XOL

t _XOH

t _XOL

t _XOH

XO

3140 drw 13

Figure 10. Expansion Out

5.05

7

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

t

t _XIR

XI

W

R

t _XIS

WRITE TO

FIRST PHYSICAL

LOCATION

t XIS

READ FROM

FIRST PHYSICAL

LOCATION

3140 drw 14

Figure 11. Expansion In

corresponding input control signals of multiple devices. Sta-

tusflags(EF, FFandHF)canbedetectedfromanyonedevice.

Figure 13 demonstrates an 18-bit word width by using two

IDT7207s. Any word width can be attained by adding addi-

tional IDT7207s (Figure 13).

OPERATING MODES:

Care must be taken to assure that the appropriate flag is

monitored by each system (i.e. FF is monitored on the device

where W is used; EF is monitored on the device where R is

used). For additional information, refer to Tech Note 8: Oper-

ating FIFOs on Full and Empty Boundary Conditions and

Tech Note 6: Designing with FIFOs.

Bidirectional Operation

Applications which require data buffering between two

systems (each system capable of Read and Write operations)

can be achieved by pairing IDT7207s as shown in Figure 16.

Both Depth Expansion and Width Expansion may be used in

this mode.

Single Device Mode

A single IDT7207 may be used when the application

requirements are for 32,768 words or less. The IDT7207 is

in a Single Device Configuration when the Expansion In (XI)

control input is grounded (see Figure 12).

Data Flow-Through

Depth Expansion

Two types of flow-through modes are permitted, a read

flow-through and write flow-through mode. For the read flow-

through mode (Figure 17), the FIFO permits a reading of a

single word after writing one word of data into an empty FIFO.

The data is enabled on the bus in (tWEF + tA) ns after the rising

edgeofW, calledthefirstwriteedge, anditremainsonthebus

until the R line is raised from LOW-to-HIGH, after which the

buswouldgointoathree-statemodeaftertRHZ ns. TheEFline

would have a pulse showing temporary deassertion and then

would be asserted.

In the write flow-through mode (Figure 18), the FIFO

permits the writing of a single word of data immediately after

reading one word of data from a full FIFO. The R line causes

the FFto be deasserted but the Wline being LOW causes it to

be asserted again in anticipation of a new data word. On the

rising edge of W, the new word is loaded in the FIFO. The W

line must be toggled when FFis not asserted to write new data

in the FIFO and to increment the write pointer.

The IDT7207 can easily be adapted to applications when

the requirements are for greater than 32,768 words. Figure 14

demonstrates Depth Expansion using three IDT7207s. Any

depth can be attained by adding additional IDT7207s. The

IDT7207 operates in the Depth Expansion mode when the

following conditions are met:

1. The first device must be designated by grounding the First

Load (FL) control input.

2. All other devices must have FL in the HIGH state.

3. The Expansion Out (XO) pin of each device must be tied to

the Expansion In (XI) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag

(FF) and Empty Flag (EF). This requires the ORing of all

EFsandORingofallFFs(i.e. allmustbesettogeneratethe

correct composite FF or EF). See Figure 14.

5. The Retransmit (RT) function and Half-Full Flag (HF) are

not available in the Depth Expansion Mode.

Compound Expansion

Foradditionalinformation,refertoTechNote9: Cascading

The two expansion techniques described above can be

applied together in a straightforward manner to achieve large

FIFO arrays (see Figure 15).

FIFOs or FIFO Modules.

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting the

5.05

8

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(HALF–FULL FLAG)

WRITE (W)

DATA IN (D)

(HF)

READ (R)

9

IDT

7207

DATA OUT (Q)

FULL FLAG (FF)

RESET (RS)

EMPTY FLAG (EF)

RETRANSMIT (RT)

3140 drw 15

EXPANSION IN (XI)

Figure 12. Block Diagram of 32,768 x 9 FIFO Used in Single Device Mode

HF

18

9

DATA_IN(D)

WRITE (W)

IDT

7207

READ (R)

IDT

7207

FULL FLAG (FF)

RESET (RS)

EMPTY FLAG (EF)

RETRANSMIT (RT)

9

XI

18

_OUT(Q)

DATA

3140 drw 16

NOTE:

1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.

Do not connect any output signals together.

Figure 13. Block Diagram of 32,768 x 18 FIFO Memory Used in Width Expansion Mode

5.05

9

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLES

TABLE I – RESET AND RETRANSMIT

SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE

Inputs

Internal Status

Outputs

Mode

Read Pointer

Location Zero

Increment⁽¹⁾

Write Pointer

Location Zero

Unchanged

RS

0

RT

X

XI

0

EF

0

FF

1

HF

1

Reset

Retransmit

1

0

X

Read/Write

1

0

Increment⁽¹⁾

X

NOTE:

3140 tbl 09

1. Pointer will Increment if flag is HIGH.

TABLE II – RESET AND FIRST LOAD

DEPTH EXPANSION/COMPOUND EXPANSION MODE

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Location Zero

X

RS

0

FL

0

XI

EF

0

FF

Reset First Device

Reset all Other Devices

(1)

Location Zero

X

1

X

0

1

0

Read/Write

1

X

NOTES:

3140 tbl 10

1. XI is connected to XO of previous device. See Figure 14.

2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output

XO

W

D

R

Q

IDT

7207

FF

9

EF

FL

9

V_CC

XI

XO

FF

EF

FL

IDT

7207

EMPTY

FULL

9

XI

XO

FF

EF

IDT

7207

9

RS

FL

XI

3140 drw 17

Figure 14. Block Diagram of 98,304 x 9 FIFO Memory (Depth Expansion)

5.05

10

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Q ₉–Q₁₇Q _(N-8)-Q_N

Q ₀–Q₈

• • •

Q ₉–Q₁₇

Q _(N-8)-Q_N

IDT7207

DEPTH

EXPANSION

BLOCK

IDT7207

DEPTH

EXPANSION

BLOCK

IDT7207

DEPTH

EXPANSION

BLOCK

R, W, RS

• • •

D ₀-D₈

D ₉-D₁₇

D _(N-8)-D_N

D0 –D N

• • •

D ₉-D_N

D ₁₈-D _N

D _(N-8)-D_N

NOTES:

3140 drw 18

1. For depth expansion block see section on Depth Expansion and Figure 14.

2. For Flag detection see section on Width Expansion and Figure 13.

Figure 15. Compound FIFO Expansion

W_A

R_B

EF_B

HF_B

IDT

7207

IDT

7201A

FFA

D_{A 0-8}

Q_{B 0-8}

SYSTEM A

SYSTEM B

A 0-8

Q

DB 0-8

IDT

7207

RA

HFA

EFA

W_B

FFB

3140 drw 19

Figure 16. Bidirectional FIFO Operation

DATA _IN

W

R

t _RPE

EF

t _WEF

t _REF

t _A

t _WLZ

DATA _OUT

DATA VALID

OUT

3171 drw 20

Figure 17. Read Data Flow-Through Mode

5.05

11

IDT7207 CMOS ASYNCHRONOUS FIFO

32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

R

t _WPF

W

t _RFF

FF

DATA _IN

t _WFF

t _DH

DATA IN

t _DS

VALID

t

A

DATA OUT

DATA OUT VALID

Figure 18. Write Data Flow-Through Mode

3140 drw 21

ORDERING INFORMATION

XXXX

X

XX

X

IDT

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

B

Commercial (0°C to +70°C)

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

Plastic DIP

P

D

J

Ceramic DIP

Plastic Leaded Chip Carrier

Leadless Chip Carrier (Military only)

L

15

20

25

30

35

50

Commercial Only

Access Time (tA)

Speed in ns

Commercial Only

Military Only

Commercial Only

L

Low Power

7207 32,768 x 9 FIFO

3140 drw 22

5.05

12


型号：	IDT7207L15DB
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	CMOS ASYNCHRONOUS FIFO 32,768 x 9 CMOS异步FIFO 32,768 ×9 先进先出芯片
文件：	总12页 (文件大小：152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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