IDT72104L50J8 [IDT]
FIFO, 4KX9, 50ns, Synchronous, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | IDT72104L50J8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 4KX9, 50ns, Synchronous, CMOS, PQCC44, PLASTIC, LCC-44 先进先出芯片 |
| 文件： | 总30页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72103
IDT72104
CMOS PARALLEL-SERIAL FIFO
2,048 x 9 and 4,096 x 9
Integrated Device Technology, Inc.
FEATURES:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial input/output frequency
• Serial-to-parallel, parallel-to-serial, serial-to-serial, and
parallel-to-parallel operations
APPLICATIONS:
• High-speed data acquisition systems
• Local area network (LAN) buffer
• High-speed modem data buffer
• Remote telemetry data buffer
• FAX raster video data buffer
• Expandable in both depth and width with no external
components
• Laser printer engine data buffer
• Flexishift™ — Sets programmable serial word width
from 4 bits to any width with no external components
• Multiple flags: Full, Almost-Full (Full-1/8),Full-Minus-
One, Empty, Almost-Empty (Empty + 1/8), Empty-Plus-
One, and Half-Full
• High-speed parallel bus-to-bus communications
• Magnetic media controllers
• Serial link buffer
DESCRIPTION:
•
Asynchronous and simultaneous read or write operations
TheIDT72103/72104arehigh-speedParallel-SerialFlFOs
to be used with high-performance systems for functions such
as serial communications, laser printer engine control and
local area networks.
• Dual-Port, zero fall-through time architecture
• Retransmit capability in single-device mode
• Packaged in 44-pin PLCC
•
Industrial temperature range (–40oC to +85oC)
FUNCTIONAL BLOCK DIAGRAM
SERIAL
INPUT
DATA INPUTS (D0
-D
8)
SI
SIX
SICP
SERIAL
INPUT
CIRCUITRY
FLAG
LOGIC
SERIAL/
PARALLEL
CONTROL
/PI
/PO
RAM ARRAY
2048 x 9
WRITE
POINTER
READ
POINTER
4096 x 9
RESET
LOGIC
DEPTH
EXPANSION
LOGIC
SERIAL
OUTPUT
SO
SOX
SOCP
SERIAL
OUTPUT
CIRCUITRY
0
DATA OUTPUTS (Q -Q
8
)
2753 drw 01
The IDT logo is a registered trademark of Integrated Device Technology,Inc.
INDUSTRIAL TEMPERATURE RANGE
DECEMBER 1999
©1999 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DSC-2753/-
1
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
Seven flags are provided to signal memory status of the
FIFO. The flags are FF (Full), AF (7/8 full), FF–1 (Full-minus-
one), EF (Empty), AE (1/8 full), EF+1 (Empty-plus-one), and
HF (Half-full).
Read (R) and Write (W) control pins are provided for
asynchronous and simultaneous operations. An Output En-
able (OE) control pin is available on the parallel output port for
high-impedancecontrol.ThedepthexpansioncontrolpinsXO
and Xl are provided to allow cascading for deeper FlFOs.
TheIDT72103/72104aremanufacturedusingIDT’sCMOS
technology.
DESCRIPTION (Continued)
A serial input, a serial output and two 9-bit parallel ports
make four modes of data transfer possible: serial-to-parallel,
parallel-to-serial,serial-to-serial,andparallel-to-parallel.These
devicesareexpandableinbothdepthandwidthforallofthese
operational configurations.
These FIFOs may be configured to handle serial word
widths of four or greater using IDT’s unique Flexishift feature.
Flexishift allows serial width and depth expansion without
external components. For example, you may configure a 4K
x 24 FIFO using three IDT72104s in a serial width expansion
configuration.
PIN CONFIGURATIONS
INDEX
6
5 4 3 2
44 43 42 41 40
D
0
7
39
GND
1
8
9
38
37
/PO
SOX
SOCP
SO
SI
SICP
SIX
10
11
36
35
12
13
34
33
14
15
16
17
32
31
30
29
Q
GND
0
18 19 20 21 22 23 24 25 26 27 28
2753 drw 03
PLCC (J44-1, order code: J)
TOP VIEW
2
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
D0-D8 Data Inputs
Serial Input Word
Name
I/O
Description
I/O In a parallel input configuration – data inputs for 9-bit wide data.
In a serial input configuration – one of the nine output pins is used to select the serial input
word width.
Width Select
RS
W
Reset
I
When RSis set low, internal READ and WRITE pointers are set to the first location of the RAM
array. EF, EF+1, AEF are all LOW after a reset, while FF, FF-1, HF are HIGH after a reset.
A parallel word write cycle is initiated on the falling edge of W if the FF is high. When the FIFO
is full, FF will go low inhibiting further write operations to prevent data overflow. In a serial
input configuration, data bits are clocked into the input shift register and the write pointer does
not advance until a full parallel word is assembled. One of the pins, Di, is connected to W and
advances the write pointer every i-th serial input clock.
A read cycle is initiated on the falling edge of R if the EF is HIGH. After all the data from the
FIFO has been read EF will go LOW inhibiting further read operations. In a serial output
configuration, a data word is read from memory into the output shift register. One of the pins,
Qj, is connected to R and advances the read pointer every j-th serial output clock.
This is a dual-purpose pin. In multiple-device mode, FL/RT is grounded to indicate the first
device loaded. In single-device mode, FL/RT acts as the retransmit input. Single-device mode
is initiated by grounding the XI pin.
Write
Read
I
R
I
I
FL/RT First Load/
Retransmit
Xl
Expansion In
I
In single-device mode, XI is grounded. In depth expansion or daisy chain mode, XI is con-
nected to the XO pin of the previous device.
OE
Output Enable
I
When OEis LOW, both parallel and serial outputs are enabled. When OEis HIGH, the parallel
output buffers are placed in a high-impedance state.
Q0-Q8 Data Outputs/Serial
Output Word Width Select
O
O
O
O
In a parallel output configuration - data outputs for 9-bit wide data. In a serial output
configuration - one of nine output pins used to select the serial output word width.
FF is asserted LOW when the FIFO is full and further write operations are inhibited. When
the FF is HIGH, the FIFO is not full and data can be written into the FIFO.
FF-1 goes LOW when the FIFO memory array is one word away from being full. It will remain
LOW when every memory location is filled.
HFis LOW when the FIFO is more than half-full in the single device or width expansion modes.
The HF will remain LOW until the difference between the write and read pointers is less than
or equal to one-half of the FIFO memory.
FF
Full Flag
FF-1
Full-1 Flag
XO/HF Expansion Out/
Half-Full Flag
In depth expansion mode, a pulse is written from XO to XI of the next device when the last
location in the FIFO is filled. Another pulse is sent from XO to Xl of the next device when the
last FIFO location is read.
AEF
Almost-Empty/
Almost-Full Flag
O
When AEF is LOW, the FIFO is empty to 1/8 full or 7/8 full to completely full. If AEF is HIGH,
then the FIFO is greater than 1/8 full, but less than 7/8 full.
EF+1 Empty+1 Flag
O
O
EF+ 1 is LOW when there is zero or one word in the FIFO memory array.
EF goes LOW when the FIFO is empty and further read operations are inhibited. FF is HIGH
when the FIFO is not empty and data reads are permitted.
EF
Empty Flag
Sl
SO
Serial Input Expansion
Serial Output Expansion
I
O
I
Data input for serial data.
Data output for serial data.
This pin is the serial input clock. On the rising edge of the SICP signal, new serial data bits
are read into the serial input shift register.
SICP Serial Input Clock
SOCP Serial Output
Clock
I
I
This pin is the serial output clock. On the rising edge of the SOCP signal, new serial data bits
are read from the serial output shift register.
SIX controls the serial input expansion for word widths greater than 9 bits. In a serial input
configuration, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other
devices is connected to the D8 pin of the previous device. In parallel input configurations or
serial input configurations of 9 bits or less, SIX is tied HIGH.
SIX
Serial Input
Expansion
SOX
SI/PI
Serial Output
Expansion
I
SOX controls the serial output expansion for word widths greater than 9 bits. In a serial output
configuration, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other
devices is connected to the Q8 pin of the previous device. In parallel output configurations or
serial output configurations of 9 bits or less, SOX is tied HIGH.
Serial/Parallel Input
I
I
When this pin is HIGH, the FIFO is in a parallel input configuration and accepts input data through
D
0
-D
When this pin is HIGH, the FIFO is in a parallel output configuration and sends output data through
-Q . When SO/PO is LOW the FIFO is in a serial output configuration and data is input through SO.
8. When SI/PI is LOW, the FIFO is in a serial input configuration and data is input through Sl.
SO/PO Serial/Parallel Output
GND Ground
Q
0
8
Five ground pins for the PLCC.
One + 5V power pin.
VCC
Power
2753 tbl 04
3
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage
with Respect to GND
Storage Temperature
–0.5 to +7.0
V
VCC
Commercial Supply
Voltage
4.5
5.0
5.5
V
TSTG
IOUT
–55 to +125
–50 to +50
°C
mA
GND
VIH
Supply Voltage
0
0
0
V
V
DC Output Current
Input High Voltage
Commercial
2.0
—
—
NOTE:
2753 tbl 01
1.Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VIL(1)
TA
Input Low Voltage
—
—
—
0.8
85
V
Operating Temperature -40
Industrial
°C
NOTE:
2753 tbl 03
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
IDT72103
IDT72104
Industrial
tA = 35, 50ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
ILI(1)
Input Leakage Current (Any Input)
–1
—
1
µA
ILO(2)
VOH
Output Leakage Current
–10
2.4
—
—
10
—
µA
Output Logic "1" Voltage,
IOUT = –2mA(4)
V
VOL
Output Logic "0" Voltage,
IOUT = 8mA(5)
—
—
0.4
V
ICC1(3)
Active Power Supply Current
—
—
90
8
140
12
mA
mA
ICC2(3,6)
Standby Current
(R = W = RS = FL/RT = VIH)
(SOCP = SICP = VIL)
ICC3(3,6)
Power Down Current
—
—
2
mA
NOTES:
2753 tbl 06
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≥ VIH, SOCP ≤ VIL, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. For SO, IOUT = –8mA.
5. For SO, IOUT =16mA.
6. SOCP = SICP ≤ 0.2V; other Inputs = VCC - 0.2V.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions
Max. Unit
5V
Symbol
CIN
Input Capacitance
VIN = 0V
10
12
pF
pF
1.1KΩ
COUT
Output Capacitance VOUT = 0V
NOTE:
2753 tbl 02
1. This parameter is sampled and not 100% tested.
D.U.T.
30pF*
680Ω
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
2753 drw 04
1.5V
or equivalent circuit
1.5V
Figure 1. Ouput Load
*Including jig and scope capacitances
See Figure 1
2753 tbl 07
4
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
Industrial
IDT72103L35
IDT72104L35
IDT72103L50
IDT72104L50
Timing
Symbol
fS
Parameter
Parallel Shift Frequency
Min.
—
Max.
22.2
50
Min.
—
Max.
15
Unit Figure
MHz
MHz
MHz
—
—
—
fSOCP
fSICP
Serial-Out Shift Frequency
Serial-In Shift Frequency
—
—
40
—
50
—
40
PARALLEL-OUTPUT MODE TIMINGS
tA
Access Time
—
10
35
45
5
35
—
—
—
—
—
20
—
—
15
50
65
15
10
—
5
50
—
—
—
—
—
30
—
ns
ns
ns
ns
ns
ns
ns
ns
4
4
tRR
Read Recovery Time
tRPW
tRC
Read Pulse Width
4
Read Cycle Time
4
tWLZ
tRLZ
tRHZ
tDV
Write Pulse LOW to Data Bus at Low-Z(1)
Read Pulse LOW to Data Bus at Low-Z(1)
Read Pulse HIGH to Data Bus at High-Z(1)
Data Valid from Read Pulse HIGH
15
4
5
—
5
4
4
PARALLEL-INPUT MODE TIMINGS
tDS
Data Set-up Time
Data Hold Time
18
0
—
—
—
—
—
20
0
—
—
—
—
—
ns
ns
ns
ns
ns
3
3
3
3
3
tDH
tWC
tWPW
tWR
Write Cycle Time
Write Pulse Width
Write Recovery Time
45
35
10
50
40
10
RESET TIMINGS
tRSC
tRS
Reset Cycle Time
45
35
35
10
—
—
—
—
50
40
40
10
—
—
—
—
ns
ns
ns
ns
2,18
2,18
Reset Pulse Width
Reset Set-up Time
Reset Recovery Time
tRSS
tRSR
2,18
2,17,18
RESET TO FLAG TIMINGS
tRSF1
tRSF2
Reset to EF, AEF, and EF+1 LOW
Reset to HF, FF, and FF-1 LOW
—
—
45
45
—
—
65
65
ns
ns
2
2
RESET TO OUTPUT TIMINGS – SERIAL MODE ONLY
tRSQL
tRSQH
tRSDL
Reset Going LOW to Q0-8 LOW
Reset Going HIGH to Q0-8 HIGH
Reset Going LOW to D0-8 LOW
20
20
20
—
—
—
20
20
20
—
—
—
ns
ns
ns
18
18
17
RETRANSMIT TIMINGS
tRTC
tRT
Retransmit Cycle Time
45
35
35
10
—
—
—
—
—
35
50
40
40
10
—
—
—
—
—
50
ns
ns
ns
ns
ns
5
5
5
5
5
Retransmit Pulse Width
Retransmit Set-up Time
Retransmit Recovery Time
Retransmit to Flags
tRTS
tRTR
tRTF
PARALLEL MODE FLAG TIMINGS
tREF
tRFF
tRF
Read LOW to EF LOW
—
—
—
—
35
—
—
—
—
35
30
30
45
45
—
30
30
45
45
—
—
—
—
—
40
—
—
—
—
40
45
45
65
65
—
45
45
65
65
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
7
Read HIGH to FF HIGH
Read HIGH to Transitioning HF, AEF and FF-1
Read LOW to EF+1 LOW
8,9,10
11
tRE
tRPE
tWEF
tWFF
tWF
Read Pulse Width after EF HIGH
Write HIGH to EF HIGH
15
6
Write LOW to FF LOW
7
Write LOW to Transitioning HF, AEF and FF-1
Write HIGH to EF+1 HIGH
8,9,10
11
tWE
tWPF
NOTE:
Write Pulse Width after FF HIGH
16
2753 tbl 08
1. Values guaranteed by design, not tested.
5
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
Industrial
IDT72103L35
IDT72104L35
IDT72103L50
IDT72104L50
Timing
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit Figure
DEPTH EXPANSION MODE TIMINGS
tXOL
tXOH
tXI
Read/Write to XO LOW
Read/Write to XO HIGH
XI Pulse Width
—
—
35
10
15
35
35
—
—
—
—
—
50
10
15
50
50
—
—
—
ns
ns
ns
ns
ns
13
13
14
14
14
tXIR
tXIS
XI Recovery Time
XI Set-up Time
SERIAL-INPUT MODE TIMINGS
tS2
Serial Data In Set-up Time to SICP Rising Edge
12
0
—
—
—
—
—
—
—
15
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
19
19
19
19
19
19
19
tH2
tS3
Serial Data In Hold Time to SICP Rising Edge
SIX Set-up Time to SICP Rising Edge
W Set-up Time to SICP Rising Edge
W Hold Time to SICP Rising Edge
Serial In Clock Width High/Low
5
5
tS4
5
5
tH4
tSICW
tS5
7
7
8
10
50
SI/PI Set-up Time to SICP Rising Edge
35
SERIAL-OUTPUT MODE TIMINGS
tS6
SO/PO Set-up Time to SOCP Rising Edge
35
5
—
—
—
—
—
50
5
—
—
—
—
—
ns
ns
ns
ns
ns
20
20
20
20
20
tS7
SOX Set-up Time to SOCP Rising Edge
R Set-up Time to SOCP Rising Edge
R Hold Time to SOCP Rising Edge
Serial Out Clock Width HIGH/LOW
tS8
5
5
tH8
7
7
tSOCW
8
10
SERIAL MODE RECOVERY TIMINGS
tREFSO
tRFFSI
Recovery Time SOCP after EF Goes HIGH
Recovery Time SICP after FF Goes HIGH
35
15
—
—
80
15
—
—
ns
ns
22
23
SERIAL MODE FLAG TIMINGS
tSOCEF
tSOCFF
tSOCF
tSOCF
tSICEF
tSICFF
tSICF
SOCP Rising Edge (Bit 0- Last Word) to EF LOW
—
—
—
—
—
—
—
—
20
30
30
30
45
30
45
45
—
—
—
—
—
—
—
—
25
40
40
40
65
40
65
65
ns
ns
ns
ns
ns
ns
ns
ns
22
24
SOCP Rising Edge (Bit 0- First Word) to FF HIGH
SOCP Rising Edge to FF-1, HF, AEF HIGH
SOCP Rising Edge to AEF, EF, EF+1 LOW
SICP Rising Edge (Last Bit-First Word) to EF HIGH
SICP Rising Edge (Bit 1-Last Word) to FF LOW
SICP Rising Edge to EF+1, AEF HIGH
24,26
22,26
21
23
21,25
23,25
tSICF
SICP Rising Edge to FF-1, HF, AEF HIGH
SERIAL-INPUT MODE TIMINGS
SICP Rising Edge to D(1)
SERIAL-OUTPUT MODE TIMINGS
tPD1
5
17
5
20
ns
17,19
tPD2
SOCP Rising Edge to Q(1)
5
5
17
16
22
18
5
5
20
16
22
18
ns
ns
ns
ns
20
20
20
20
tSOHZ
tSOLZ
tSOPD
SOCP Rising Edge to SO at High-Z(1)
SOCP Rising Edge to SO at Low-Z(1)
SOCP Rising Edge to Valid Data on SO
5
5
—
—
OUTPUT ENABLE/DISABLE TIMINGS
tOEHZ
tOELZ
tAOE
Output Enable to High-Z (Disable)(1)
Output Enable to Low-Z (Enable)(1)
Output Enable to Data Valid (Q0-8)
—
5
16
—
20
—
5
16
—
22
ns
ns
ns
12
12
12
—
—
NOTE:
2753 tbl 09
1. Values guaranteed by design, not tested.
6
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
GENERAL SIGNAL DESCRIPTION
Expansion In (XI)
The XI pin is grounded to indicate an operation in the the
single-device mode. In the depth expansion or daisy-chain
mode, the XI pin is connected to the XO pin of the previous
device.
INPUTS:
Data Inputs (D0-D8)
Theparallel-inmodeisselectedbyconnectingtheSI/PIpin
to VCC. D0-D8 are the data input lines.
The serial-input mode is selected by grounding the SI/PI
pin. The D0-D8 lines are control output pins used to program
the serial word width.
Output Enable (OE)
When OEis HIGH, the parallel output buffers are tristated.
When OE is LOW, both parallel and serial outputs are en-
abled.
Reset (RS)
Serial Input (SI)
Reset is accomplished whenever the RS input is taken to
alowstate. Bothinternalreadandwritepointersaresettothe
first location during reset. A reset is required after power up
before a write operation can take place. Both Read (R) and
Write (W) inputs must be HIGH during reset.
SerialdataisreadintotheserialinputregisterviatheSlpin.
In both depth and serial width expansion modes, the serial-
input signals of the different FlFOs in the expansion array are
connected together.
Serial Input Clock (SICP)
Write (W)
Serial data is read into the serial input register on the rising
edge of the SICP signal. In both depth and serial width
expansion modes, the SICP signals of the different FlFOs in
the expansion array are connected together.
A write cycle is initiated on the falling edge of W provided
the Full Flag (FF) is not asserted. Data set-up and hold times
must be met with respect to the rising edge of W. Data is
stored in the RAM array sequentially and independently of
any on going read operation.
When the FIFO is full, the FF will go LOW inhibiting further
write operations to prevent data overflow. After a valid read
operationiscompleted, theFFwillgoHIGHaftertRFF allowing
a valid write to begin.
Serial Output Clock (SOCP)
New serial data bits are read from the serial output register
ontherisingedgeoftheSOCPsignal. Inbothdepthandserial
width expansion modes, the SOCP signals of the different
FlFOs in the expansion array are connected together.
Read (R)
Serial Input Expansion (SIX)
A read cycle is initiated on the falling edge of R, provided
the EF is not set. Data is accessed on a first-in/first out basis
independent of any on going write operations. After R goes
HIGH, the Data Outputs (Q0-Q8) go to a high-impedance
condition until the next read operation. When all the data has
been read from the FIFO, the EFwill go LOW, and Q0-Q8 will
go to a high-impedance state inhibiting further read opera-
tions.Afterthecompletionofavalidwriteoperation,theEFwill
go HIGH after tWEF allowing a valid read to begin.
The SlX pin is tied HIGH for single-device serial or parallel
input operation. In a serial input configuration, the SIX pin of
theleastsignificantdeviceistiedHIGH.TheSIXpinofallother
devices is connected to the D8 pin of the previous device.
Serial Output Expansion (SOX)
TheSOXpinistiedHIGHforsingle-deviceserialorparallel
output operation. In a serial output configuration, the SOX pin
of the least significant device is tied HIGH. The SOX pin of all
other devices is connected to the Q8 pin of the previous
device.
First Load/Retransmit (FL/RT)
Inthedepth-expansionmode, theFL/RTpinisgroundedto
indicate that it is the first device loaded. In the single-device
mode, the FL/RTpin acts as the retransmit input. The single-
device mode is initiated by grounding the Expansion-ln (XI)
pin.
The IDT72103/72104 can be made to retransmit data
when the RTinput is pulsed LOW. A retransmit operation will
set the internal read pointer to the first location and will not
affect the write pointer. During retransmit, R and W must be
set HIGH and theFFwill be affected depending on the relative
locations of the read and write pointers. This feature is useful
when less than 2,048/4,096 writes are performed between
resets. The retransmit feature is not available in the depth
expansion mode.
Serial/Parallel Input (SI/PI)
The SI/PI pin programs whether the IDT72103/72104
accepts parallel or serial data as input. When this pin is LOW,
the FIFO expects serial data and the D0-D8 pins become
output pins used to program the write signal and the serial
input word width. For instance, connecting D8 to W will
program a serial word width of 9 bits; connecting D7 to Wwill
program a serial word width of 8 bits and so on.
Serial/Parallel Output (SO/PO)
The SO/PO pin programs whether the IDT72103/72104
outputsparallelorserialdata. WhenthispinisLOW, theFIFO
expects serial data and the Q0-Q8 pins output signals used to
program the read signal and the serial output word width.
7
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
rising edge of the read operation.
In the multiple-device mode, the XI pin is connected to the
XO pin of the previous device. The XO pin signals a pulse to
the next device when the previous device reaches the best
location of memory in the daisy chain configuration.
OUTPUTS:
Data Outputs (Q0–Q8)
Data outputs for 9-bit wide data. These output lines are in
ahigh-impedanceconditionwheneverRisinahighstate. The
serial output mode is selected by grounding the SO/PO pin.
The Q0-Q8 lines are control pins used to program the serial
word width.
Almost–Empty or Almost–Full Flag (AEF)
The AEF asserts LOW if there are 0-255 or 1,793-2,048
bytes in the IDT72103, 2,048 x 9 FIFO. The AEFasserts LOW
if there are 0-511 or 3,585-4,096 bytes in the IDT72104,
4,096 x 9 FIFO.
Serial Output (SO)
Serial data is output on the SO pin. In both depth and serial
width expansion modes the serial output signals of the
different FlFOs in the expansion array are connected to-
gether. Following reset, SO is tristated until the first rising
edge of the Serial Out Clock (SOCP) signal. Data is clocked
out least significant bit first. In the serial width expansion
mode, SO is tristated again after the ninth bit is output.
Empty–Plus–One Flag (EF+1)
In the parallel-output mode, the EF+1flag is asserted LOW
when there is one word or less in the FIFO. It will remain LOW
when the FIFO is empty.
In the serial-output mode, the EF+1 flag operates as an
EF+2 flag. It goes LOW when the second to the last word is
read from the RAM array and is ready to be shifted out.
Full Flag (FF)
FFis asserted LOW when the FIFO is full. When the FIFO
is full, the internal write pointer will not be incremented by any
additional write pulses.
Empty Flag (EF) — Parallel–Out Mode
When the FIFO is in the parallel out mode and there is only
one word in the FIFO, the falling edge of the R line will cause
theEFlinetobeassertedLOW. ThisisshowninFigure6. The
EFis then de-asserted HIGH by either the rising edge of W or
the rising edge of SICP, as shown in Figure 6.
Full Flag — Serial In Mode
WhentheFIFOisloadedserially,theSerialInClock(SICP)
asserts the FF. On the second rising edge of the SICP for the
last word in the FIFO, the FFwill assert LOW, and it will remain
asserted until the next read operation. Note that when the FF
isasserted,thelastSICPforthatwordwillhavetobestretched
as shown in Figure 23.
Empty Flag — Serial–Out Mode
The use of the EF is important for proper serial-out opera-
tion when the FIFO is almost empty. The EF flag is asserted
LOW after the first bit of the last word is shifted out. This is
shown in Figure 22.
Full Flag — Parallel–ln Mode
When the FIFO is in the Parallel-ln mode, the falling edge
ofWassertsthe FF(LOW). TheFFisthende-asserted(HIGH)
by subsequent read operations - either serial or parallel.
TABLE 1 — STATUS FLAGS
Number of
Words in FIFO
IDT72103 IDT72104
(1)
FF FF-1 AEF HF EF+1 EF
Full–Minus — One Flag (FF–1)
0
1
0
1
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
L
L
L
H
H
L
L
L
H
H
H
H
L
L
L
L
The FF–1 flag is asserted low when the FIFO is one word
away from being full. It will remain asserted when the FIFO is
full.
H
2-255
256-1,024
2-511
512-2,048
H
H
H
H
H
H
H
'
H
Expansion Out/Half–Full Flag (XO/HF)
1,025-1,792 2,049-3,584
1,793-2,046 3,585-4,094
H
In the single-device mode, the XO/HFpin operates as aHF
pin when the Xl pin is grounded. After half of the memory is
filled, the HFwill be set to LOW at the falling edge of the next
write operation. It will remain set until the difference between
the write pointer and read pointer is less than or equal to one-
half of the FIFO total memory. The HF is then reset by the
L
H
H
2,047
2,048
4,095
4,096
L
L
L
H
NOTE:
1. EF+1 acts as EF+2 in the serial out mode.
2753 tbl 10
8
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
PARALLEL TIMINGS:
t
RSC
t
RS
t
RSS
tRSR
t
RSS
RSF1
t
t
RSF2
2753 drw 05
Figure 2. Reset
tRC
t
WC
tRPW
tRR
t
WPW
tWR
t
DH
t
DS
Q0–8
VALID DATA
2753 drw 07
D
0–8
t
DV
2753 drw 06
t
RLZ
t
A
t
RHZ
Figure 3. Write Operation in Parallel Data In Mode
Figure 4. Read Operation in Parallel Data Out Mode
t
RTC
t
RT
t
RTS
tRTR
t
RTF
FLAG VALID
All Flags
2753 drw 08
Figure 5. Retransmit
9
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
(1)
t
WEF
(2)
REF
t
(3)
2753 drw 09
NOTES:
1. Data is valid on this edge.
2. The Empty Flag is asserted by R in the Parallel-Out mode and is specified by tREF. The EF flag is deasserted by the rising edge of W.
3. First rising edge of Write after EF is set.
Figure 6. Empty Flag Timings in Parallel Out Mode
t
WFF
(1)
RFF
t
2753 drw 10
NOTE:
1. For the assertion time, tWFF is used when data is written in the Parallel mode. The FF is de-asserted by the rising edge of R.
Figure 7. Full Flag Timings in Parallel-In Mode
t
WF
t
WF
t
RF
t
RF
Almost
Empty
Almost
Empty
Almost
Full
2753 drw 11
2753 drw 12
Figure 8. Almost-Empty Flag Region
Figure 9. Almost-Full Flag Region
10
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
t
WF
t
RF
2753 drw 13
Figure 10. Half-Full and Full-minus-1 Flag Timings
t
RE
t
WE
2753 drw 14
Figure 11. Empty+1 Flag Timings
t
RC
t
RR
TERMINATEREADCYCLE
tA
SECOND READ BY CONTROLLING
t
DV
t
OEHZ
t
AOE
OELZ
t
RLZ
t
Q0-8
DATA 1
DATA 1
2753 drw 15
Figure 12. Output Enable Timings
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
t
XOL
tXOH
t
XOL
tXOH
2753 drw 16
Figure 13. Expansion-Out
11
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
t
XI
tXIR
t
XIS
WRITE TO
FIRST PHYSICAL
LOCATION
t
XIS
READ FROM
FIRST PHYSICAL
LOCATION
2573 drw 17
Figure 14. Expansion-In
Dn
t
RPE
t
REtF
A
t
WEF
t
WLZ
Q
n
DATAOUT VALID
2753 drw 18
Figure 15. Read Data Flow-Through Mode
tWPF
tWFF
t
RFF
t
DH
t
DS
DATA IN
VALID
Dn
tA
DATA
OUT VALID
Q
n
2753 drw 19
Figure 16. Write Data Flow-Through Mode
12
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
SERIAL TIMINGS:
tRS
t
RSR
t
RSS
(1)
0
i
i
SICP
SICP
0
i-1
(1)
t
PD1
D0
tPD1
tRSDL
2753 drw 20
D1-8
NOTE:
1. SICP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.
Figure 17. Reset Timings for Serial-In Mode
t
RSC
tRS
tRSS
tRSR
SOCP
SOCP
(1)
(1)
tRSQH
tRSQL
Q
0-8
2753 drw 21
NOTE:
1. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.
Figure 18. Reset Timings for Serial-Out Mode
13
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
tSICW
t
SICW
1
(1)
0
2
n – 1
SICP
1/tSICP
/PI(3)
tS5
SIX
SI
t
S3
t
S2
tH2
Di
(2)
S4
(2)
H4
t
t
tPD1
NOTES:
1. For the stand alone mode, n ≥ 4 and the input bits are numbered 0 to n-1.
2753 drw 22
2. For the recommended interconnections, Di is to be directly tied to W and the tS4 and tH4 requirements will be satisfied. For users that modify W
externally, tS4 and tH4 requirements have to be met.
3. After SI/PI has been set up, it cannot be dynamically changed; it can only be changed after a reset operation.
Figure 19. Write Operation In Serial-ln Mode
t
SOCW
0
tSOCW
1
n – 1
SOCP
1/tSOCP
/PO(1)
SOX
t
S6
t
S7
Qi
t
S8
t
PD2
t
H8
(2)
SO
SO
t
SOHZ
t
SOLZ
SOPD
t
(3)
NOTES:
2753 drw 23
1. After SO/PO has been set up, it cannot be dynamically changed; it can only be changed after a reset operation.
2. For single device: Read out the last bit after EF is asserted.
For Serial Width Expansion mode: Read out the last bit of the current memory location from the active device.
3. For single device: The operation starts after Reset.
For Serial Width Expansion mode: Read the first bit of the current memory location from the active device.
Figure 20. Read Operation In Serial-Out Mode
14
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
FIRST
SERIAL-IN WORD
SECOND
SERIAL-IN WORD
THIRD
SERIAL-IN
WORD
0
1
n – 1
0
1
n – 1
0
SICP
Dn-1
t
PD1
t
SICEF
(2)
t
SICF
t
REF
(3)
t
REE
(1)
2753 drw 24
NOTES:
1. Parallel Read shown for reference only. Can also use serial output mode.
2. The Empty Flag is de-asserted after the N–1 rising edge of SICP of the first serial-in word. In the Serial-Out mode, a new read operation can begin
tREFSO after EF goes HIGH. In the Parallel-Out mode, a new read operation can occur immedately after FF goes HIGH.
3. The EF+1 Flag is de-asserted after the N–1 rising edge of SICP of the second serial-in word.
Figure 21. Empty Flag and Empty+1 Flag De-assertion in the Serial-ln Mode
SERIAL
WORD A
SERIAL
WORD B
LAST SERIAL
WORD
0
1
n-2
n-1
0
1
n-2
n-1
0
1
n-2
n-1
0
1
SOCP
=Qn-1
t
SOCF
t
SOCEF
tREFSO
(2)
t
WEF
(3)
(1)
2753 drw 25
WORD WORD THIRD
A
B
WORD
NOTES:
1. Parallel write shown for reference only. Can also use serial input mode.
2. The Empty Flag (EF) is asserted in Serial-Out mode by using the tSOCEF parameter. This parameter is measured in the worst case condition from the
rising edge of the SOCP used to clock data bit 0. Whenever EF goes LOW, there is only one word to be shifted out. In the Parallel-ln mode, the EF
flag is de-asserted by the rising edge of W. In the Serial-ln mode, the EF flag is de-asserted by the rising edge of W.
3. First Write rising edge after EF is set.
4. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
Figure 22. Empty Flag and Empty+1 Flag Assertion in the Serial-Out Mode (FIFO Being Emptied)
15
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
NEXT TO LAST
SERIAL WORD
LAST SERIAL
WORD
0
1
n-2
n-1
0
1
n-2
n-1
0
1
SICP
=Dn-1
tSICF
tSICFF
tRFFSI
(1)
t
RFF
(2)
2753 drw 26
NOTES:
1. The Full Flag is asserted in the Serial-ln mode by using the tSICFF parameter. This parameter is measured in the worst case condition from the rising
edge of SICP following a (tPD1+tWFF) delay from the first SICP rising edge of the last word.
2. First Read rising edge after FF is set.
3. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
Figure 23. Full Flag and Full-1 Flag Assertlon in the Serial-ln Mode (FIFO Being Filled)
FIRST
SERIAL-OUT WORD
SECOND
SERIAL-OUT WORD
0
1
n – 1
0
1
n – 1
SOCP
Q
n+
t
PD2
(1)
(2)
tSOCF
t
SOCFF
tWFF
t
WF
2753 drw 27
NOTES:
1. The FIFO is full and a new read sequence is started.
2. On the first rising edge of SOCP, the FF is de-asserted. In the Serial-ln mode, a new write operation can begin following tRFFS1 after FF, goes HIGH.
In the Parallel-ln mode, a new write operation can occur immediately after FF goes HIGH.
3. The FF-1 flag is de-asserted after the first SOCP of the second serial word.
Figure 24. Full Flag and Full-1 Flag De-assertion in the Serial-Out Mode
16
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
HALF-FULL (1/2)
SICF
HALF-FULL + 1
HALF-FULL + 1
t
t
t
RF
0
1
n – 1
0
SICP
t
SICF
ALMOST-FULL + 1
(7/8 Full + 1)
ALMOST-FULL + 1
(7/8 Full + 1)
ALMOST-FULL
(7/8 Full)
RF
ALMOST-EMPTY – 1
(1/8 Full–1)
ALMOST-EMPTY
(1/8 Full)
ALMOST-EMPTY
(1/8 Full)
2753 drw 28
Figure 25. Half-Full, Almost-Full and Almost-Empty Timings for Serial-In Mode
HALF-FULL +1
HALF-FULL (1/2)
n – 1 0
HALF-FULL (1/2)
t
SOCF
t
WF
0
1
SOCP
t
SOCF
ALMOST-FULL
(7/8 Full)
ALMOST-FULL
(7/8 Full)
ALMOST-FULL + 1
(7/8 Full+1)
tWF
ALMOST-EMPTY
(1/8 Full)
ALMOST-EMPTY – 1
(1/8 Full–1)
ALMOST-EMPTY – 1
(1/8 Full–1)
2753 drw 29
Figure 26. Half-Full, Almost-Full and Almost-Empty Timings for Serial-Out Mode
17
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
Single Device Mode
OPERATING DESCRIPTION
Asingle IDT172103/72104 maybeusedwhenapplication
requirementsarefor2,048/4,096wordsorless. TheIDT72103/
72104 is in the Single Device Configuration when the Expan-
sion In (Xl) control input is grounded (See Figure 27). In this
mode, the HF/XO is used as a Half-Full flag.
PARALLEL OPERATING MODES:
Parallel Data Input
By setting SI/PI HIGH, data is written into the FIFO in
parallel through the D0-D8 input data lines.
Wldth Expanslon Mode
Parallel Data Output
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Sta-
tus flags can be detected from any one of the connected
devices. Figure 28 demonstrates an 18-bit word width by
using two IDT72103/72104s. Any word width can be attained
by adding additional IDT72103/72104s.
By setting SO/PO HIGH, the parallel-out mode is chosen.
In the parallel-out mode, as shown in Figure 4, data is
available tA after the falling edge of R and the output bus Q
goes into high-impedance after R goes HIGH.
Alternately, the user can access the FIFO by keeping R
LOW and enabling data on the bus by asserting OE. When R
is LOW, theOEis HIGH and the output bus is tri-stated. When
R is HIGH, the output bus is disabled irrespective of OE. The
enable and disable timings for OE are shown in Figure 12.
HALF-FULL FLAG
V
CC
VCC
/PI)
WRITE )
(
/PO)
) READ
9
9
DATA IN
(D)
(Q)
DATA OUT
IDT
72103
72104
) EMPTY FLAG
FULL FLAG
)
) EMPTY-PLUS-ONE
) ALMOST-EMPTY
) RETRANSMIT
FULL-MINUS-ONE
ALMOST-FULL (
RESET (
)
)
)
) OUTPUT ENABLE
2573 drw 30
EXPANSION IN ( )
Figure 27. Block Diagram of Single 2,048 x 9 and 4,096 x 9 FIFO in Parallel Mode
18
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
INPUT CONFIGURATION TABLE
Serial Input
Width Expansion
All Other
Parallel
Input
Single
Device
Least Significant
Device
Most Significant
Device
Pin
/PI
Devices
HIGH
LOW
Input Data
Input Clock
HIGH
LOW
Input Data
Input Clock
HIGH
LOW
LOW
Sl
HIGH or LOW
HIGH or LOW
HIGH
Input Data
Input Clock
Input Data
Input Clock
SICP
SIX
D8
of next least
significant device
D
8
of next least
significant device
of most
D
i
Write Control
Input Data
Di
Di
of most
Di of most
significant device
significant device
significant device
D
0
-D
8
No connect
No connect except D
8
No connect except D
8
No connect except Di
except D
i
D(1)
i
—
—
—
—
of all devices
—
D8
—
SIX of next most
significant device
SIX of next most
significant device
2753 tbl 11
NOTE:
1. Di refers to the most significant bit of the serial word. If multiple devices are width cascaded. Di is the most significant bit from the most significant
device.
OUTPUT CONFIGURATION TABLE
Serial Output
Width Expansion
Parallel
Output
Single
Device
Least Significant
Device
All Other
Devices
Most Significant
Device
Pin
/PO
SO
HIGH
—
LOW
LOW
LOW
LOW
Output Data
Output Clock
HIGH
Output Data
Output Clock
HIGH
Output Data
Output Clock
Output Data
Output Clock
SOCP HIGH or LOW
SOX
HIGH
Q8
of next least
Q8
of next least
significant device
significant device
Read Control
Output Data
Q
i
Q
i
of most
Q
i
of most
Qi of most
significant device
significant device
significant device
Q
0
-Q8
No connect
No connect except Q
8
No connect except Q
8
No connect except Qi
except D
i
Q (1)
i
—
—
—
—
of all devices
—
Q
8
—
SOX of next most
significant device
SOX of next most
significant device
2753 tbl 12
NOTE:
1. Qi refers to the most significant bit of the serial word. If multiple devices are width cascaded. Qi isthe most significant bit from the most significant
device.
19
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
18
9
9
DATA IN
(D)
/PO)
V
CC
/PO)
) OUTPUT ENABLE
WRITE
)
)
) READ
IDT
72103
72104
FULL FLAG
IDT
72103
72104
) EMPTY FLAG
) RETRANSMIT
RESET
)
9
9
/PI)
/PI)
V
CC
)
)
(Q) DATA OUT
18
2753 drw 31
NOTE:
1. Flag detection is accomplished by monitoring all the flag signals of either (any) device used in the width expansion configuration. Do not connect any
flag signals together.
Figure 28. Block Diagram of 2,048 x 18 and 4,096 x 18 FIFO Memory Used in Width Expansion in Parallel Mode
TRUTH TABLES
TABLE 2: RESET AND RETRANSMIT —
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION IN PARALLEL MODE
(2)
(1)
Inputs
Internal Status
Outputs
RS
0
FL
X
0
XI
0
AEF EF
FF
HF
I
Mode
Reset
Read Pointer
Location Zero
Location Zero
Write Pointer
Location Zero
Unchanged
,
0
X
X
1
1
Retransmit
Read/Write
NOTES:
1
0
X
X
X
(1)
(1)
1
1
0
Increment
Increment
X
2753 tbl 13
1. Pointer will increment if appropriate flag is HIGH.
RS
FL RT
EF
FF
XI
= Expansion Input.
2.
= Reset Input,
/
= First Load/Retransmit,
= Empty Flag Output,
= Full Flag Output,
20
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
3. The Expansion Out (XO) pin of each device must be tied
to the Expansion In (Xl) pin of the next device. See
Figure 29.
4. External logic is needed to generate a composite
Full Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (i.e., all must be
set to generate the correct composite FF or EF). See
Figure 29.
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT72103/72104 can be easily adapted to applica-
tionswheretherequirementsareforgreaterthan2,048/4,096
words. Figure 29 demonstrates Depth Expansion using three
IDT72103/72104s. Any memory depth can be attained by
adding additional IDT72103/72104s. The IDT72103/72104
operates in the Depth Expansion configuration when the
following conditions are met:
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion mode.
1. The first device must be designated by grounding the
First Load (FL) control input pin.
2. All other devices must have the FL pin in the high state.
R
IDT
9
9
9
9
9
72103
72104
Q
D
Vcc
IDT
72103
72104
IDT
72103
72104
2753 drw 32
NOTE:
1. SI/PI and SO/PO pins are tied to VCC.
Figure 29. Block Diagram of 6,144 x 9 and 12,288 x 9-FIFO Memory, Depth Expansion in Parallel Mode
21
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
achieved by pairing IDT72103/72104 as shown in Figure 30.
Both Depth Expansion and Width Expansion may be used in
this mode.
BIDIRECTIONAL MODE
Applicationsrequiringdatabufferingbetweentwosystems
(each system capable of Read and Write operations) can be
B
B
A
A
IDT
72103
72104
B
DA0-8
QB0-8
SYSTEM A
SYSTEM B
QA0-8
DB0-8
IDT
72103
72104
B
B
A
A
A
2573 drw 33
NOTE:
1. SI/PI and SO/PO pins are tied to VCC.
Figure 30. Bidirectional FIFO Mode
COMPOUND EXPANSION MODE
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 31).
Q
N–8 - QN
Q
0
- Q8
Q
9
9
- Q17
- Q17
Q0
- Q8
Q
Q
N–8 - Q
N
IDT72103
IDT72104
DEPTH
EXPANSION
BLOCK
IDT72103
IDT72104
DEPTH
EXPANSION
BLOCK
IDT72103
IDT72104
DEPTH
EXPANSION
BLOCK
D0
- D8
D
N–8 - D
N
D9
- D17
D0 - DN
D9 - DN
D18 - D
N
DN–8 - DN
2753 drw 34
NOTES:
1. SI/PI and SO/PO pins are tied to VCC.
2. For depth expansion block see DEPTH EXPANSION Section and Figure 29.
3. For Flag Detection see WIDTH EXPANSION SECTION and Figure 28.
Figure 31. Compound FIFO Expansion
22
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
TABLE 3: RESET AND FIRST LOAD TRUTH TABLE —
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs(2)
Internal Status
Outputs
RS
FL
XI
I
EF
FF
Mode
Read Pointer
Write Pointer
Reset-First
Device
0
0
1
(1)
(1)
(1)
Location Zero
Location Zero
0
1
Retransmit all
Other Devices
0
1
Location Zero
X
Location Zero
X
0
1
Read/Write
X
X
X
NOTES:
2753 tbl 14
XI
XO
of previous device.
1.
is connected to
RS
FL RT
EF
FF
XI
= Expansion Input.
2.
= Reset Input,
/
= First Load/Retransmit,
= Empty Flag Ouput,
= Full Flag Output,
SERIAL OPERATING MODES:
Serial Data Input
connected to W, goes HIGH. On the next clock cycle, after W
is HIGH, all of the D lines go LOW again and a new serial word
input starts.
The Serial Input mode is selected by grounding the Sl/PI
line. The D0-8 lines are then outputs which are used to
programthewidthoftheserialword. Theyaretapsoffadigital
delay line which are meant for connection to the W input. For
instance, connecting D6 to Wwill program a serial word width
of 7 bits, connecting D7 to W will program a serial word width
of 8 bits and so on.
By programming the serial word width, an economy of
clock cycles is achieved. As an example, if the word width is
6 bits, then on every 6th clock cycle the serial data register is
written in parallel into the FIFO RAM array. Thus, the possible
In the cascaded case, the first LOW-to-HlGH SICP clock
edge for a serial word will cause all timed outputs (D) to go
LOW except for D0 of the least significant device. The D
outputs of the least significant device will go high on consecu-
tive clock cycles until D8. When D8 goes HlGH, the SlX of the
next device goes HlGH. On the next cycle after the SIX input
is brought HIGH, the D0 goes HIGH; then on the next cycle D1
and so on. A Di output from the most significant device is
issued to create the W for all cascaded devices.
The minimum serial word width is 4 bits and the maximum
clock cycles for an extra 3 bits of width in the RAM array are is virtually unlimited.
not required.
WhenintheSerialmode,theLeastSignificantBitofaserial
The SIX signal is used for Serial-ln Expansion. When the stream is shifted in first. If the FIFO output is in the Parallel
serial word width is 9 or less, the SIX input must be tied HIGH. mode, the first serial bit will come out on Q0. The second bit
When more than 9 bits of serial word width is required, more shifted in is on Q1 and so on.
than one device is required. The SIX input of the least
In the Serial Cascade mode, the serial input (Sl) pins must
significant device must be tied HIGH. The D8 pin of the least be connected together. Each of the devices then receives
significant device must be tied to SIX of the next significant serial information together and uses the SIX and D0-8 lines to
device. In other words, the SIX input of the most significant determine whether to store it or not.
andintermediatedevicesmustalwaysbeconnectedtotheD8
of the next least significant device.
The example shown in Figure 34 shows the interconnec-
tions for a serializing FIFO that transfers data to the internal
Figure32showstherelationshipoftheSIX, SICPand D0-8 RAM in 16-bit quantities (i.e. every 16 SlCP cycles). This
lines. In the stand alone case (Figure 32), on the first LOW-to- corresponds to incrementing the write pointer every 16 SICP
HlGH of SICP, the D1-8 lines go LOW and the D0 line remains cycles.
HIGH. On the next SICP clock edge, the D1 goes HIGH, then
Once W goes HIGH With the last serial bit in, SICP should
D2 and so on. This continues until the D line, which is not be clocked again until FF goes HIGH.
23
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
SINGLE DEVICE SERIAL INPUT CONFIGURATION
V
CC
GND
/PI
/PO
SICP
SI
SERIAL-IN CLOCK
SERIAL-IN DATA
Q
0-7
IDT72103/72104
8
V
CC
SIX
D0 D1 D2 D3 D4 D5 D6 D7 D8
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
SICP
=1
D0
D
1
2
3
4
5
6
D
D
D
D
D
D7
2753 drw 35
Figure 32. Serial-In Mode Where 8-Bit Parallel Output Data is Read
SERIAL DATA IN DATA IN/TIMED
OUTPUTS D0-8
SERIAL-INPUT
CLOCK
RGTR
9
9
MUX
/PI
DELAYED
TIMING
GENERATOR
DATA IN TO
FIFO RAM
Figure 33. Serial-Input Circuitry
24
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
SERIAL INPUT WIDTH EXPANSION
VCC
VCC
/PO
GND
GND
/PI
/PI
/PO
SERIAL-IN
SI
SI
DATA
SERIAL-IN
IDT72103/72104
FIFO #1
IDT72103/72104
FIFO #2
SICP
SICP
SIX
CLOCK
VCC
SIX
Q0-8
D8
D6 Q0-6
7
9
9
16-BIT
PARALLEL
OUTPUT
0
1
7
8
9
10
14
15
0
SICP
8
D OF FIFO #1
AND SIX OF
FIFO #2
6
D OF FIFO #2
ANOF
FIFO #1 AND
FIFO #2
2753 drw 37
Figure 34. Serial-In Configuration for Serial-In to Parallel-Out Data of 16 bits
SERIAL INPUT WITH DEPTH EXPANSION
Q0-7
VCC
GND
VCC
/PI
SIX
/PO
Q0-7
IDT72104
7
D
SOX SI SICP
VCC
SICP
VCC
/PI
SIX
/RT
/PO
GND
Q
0-7
IDT72104
SICP
VCC
7
D
SI
SOX
VCC
2753 drw 38
SI
NOTE:
1. All SI/PI pins are tied to GND and SO/PO pins are tied to VCC. OE is tied LOW. For FF and EF connections see Figure 29.
Figure 35. An 8,192 x 8 Serial-In, Parallel-Out FIFO
25
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL
DATA IN
VCC
SI
D
8
SI
D
8
SI
D5
SIX
SIX
SIX
IDT72104
IDT72104
SICP
SICP
SICP
IDT72104
Q0-8
Q0-8
Q0-5
V
CC
SIX
SIX
SIX
SI D5
SI
D
8
SI
D
8
SERIAL
INPUT
CLOCK
SICP
SICP
SICP
IDT72104
IDT72104
IDT72104
READ
Q0-8
Q0-8
Q0-5
P0-8
P9-17
P18-23
2753 drw 39
PARALLEL DATA OUT
NOTE:
1. All SI/PI pins are tied to GND. SO/PO pins are tied to VCC. For FL/RT, FF and EF connections see Figure 29.
Figure 36. An 8,192 x 24 Serial-In, Parallel-Out FIFO Using Six IDT72104s
In the cascaded case, word width of more than 9 bits can
beachievedbyusingmorethanonedevice. BytyingtheSOX
line of the least significant device HIGH and the SOX of the
subsequent devices to Q8 of the previous device, a cascaded
serial word is achieved. On the first LOW-to-HIGH clock edge
of SOCP, all the Q lines go low except for Q0. Just as in the
stand alone case, on each consecutive clock cycle, each Q
line goes HIGH in the order of least to most significant. When
Q8 (which is connected to the SOX input of the next device)
goes HIGH, the D0 of that device goes HIGH, thus cascading
from one device to the next. The Q line of the most significant
device, which programs the serial word width, is connected to
all R inputs.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is tri-stated, only
thedevicewhichiscurrentlyshiftingoutisenabledanddriving
the 1-bit bus.
Figure 39 shows an example of the interconnections for a
16-bit serialized FIFO.
SERIAL DATA OUTPUT
The Serial Output mode is selected by setting the SO/PO
line LOW. When in the Serial-Out mode, one of the Q1-8 lines
shouldbeusedtocontroltheRsignal. IntheSerial-Outmode,
the Q0-8 are taps off a digital delay line. By selecting one of
these taps and connecting it to R, the width of the serial word
to be read and shifted is programmed. For instance, if the Q5
line is connected to the R input, on every sixth clock cycle a
new word is read from the FIFO RAM array and begins to be
shifted out. The serial word is shifted out Least Significant Bit
first. If the input mode of the FIFO is parallel, the information
that was written into the D0 bit will come out as the first bit of
the serial word. The second bit of the serial stream will be the
D1 bit and so on.
In the stand alone case, the SOX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SOCP clock, all of the
Q outputs except for Q0 go LOW and a new serial word is
started. On the next clock cycle, Q1 will go HIGH, Q2 on the
next clock cycle and so on, as shown in Figure 37. This
continues until the Q line, which is connected to R, goes HIGH
at which point all of the Q lines go LOW on the next clock and
a new word is started.
OnceR goesHIGHwiththelastserialbitout,SOCPshould
not be clocked again until EF goes HIGH.
26
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
VCC
GND
PARALLEL DATA IN
D0-7
/PI
/PO
SOCP
SERIAL-OUT CLOCK
SERIAL-OUT DATA
SO
IDT72103/72104
GND
VCC
SOX
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
SOCP
=1
Q
0
Q
1
2
3
4
5
6
Q
Q
Q
Q
Q
Q
7
2753 drw 40
NOTE:
1. Input data is loaded in 8-bit quantities and read out serially.
Figure 37. Serial-Out Configuration
27
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
SOCP-SERIAL
OUTPUT CLOCK
OUTPUT FROM
RAM ARRAY
/PO
9
DELAYED
TIMING
GENERATOR
CONTROL
CIRCUIT
SERIAL-
OUTPUT
DATA
SERIAL-OUT
REGISTER
/PO
MUX
(SO)
9
PARALLEL-OUT DATA/
TIMED OUTPUT Q 0-8
2753 drw 41
Figure 38. Serial-Output Circuitry
PARALLEL DATA IN
16-BITS WIDE
SERIAL-OUT
DATA
9
7
VCC
GND
VCC
GND
/PI
FIFO #1
/PO
/PI
FIFO #2
/PO
D
0-8
D0-6
SO
SO
SERIAL-OUTPUT
CLOCK
SOCP
SOX
SOCP
SOX
VCC
Q8
Q6
0
1
7
8
9
10
14
15
0
SOCP
Q
8
OF FIFO #1
AND SOX OF
FIFO #2
6
Q OF FIFO #2
AND OF FIFO
#1 AND FIFO #2
2753 drw 42
NOTE:
1. The parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2.
Figure 39. Serial-Output for 16-Bit Parallel Data In
28
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
SERIAL OUTPUT WITH DEPTH EXPANSION
D0-7
D0-7
IDT72104
SO SOCP
7
Q
SOX
VCC
SOCP
D0-7
IDT72104
SO SOCP
VCC
7
Q
SOX
VCC
2753 drw 43
SO
NOTE:
1. All SI/PI pins are tied to VCC and SO/PO pins are tied to GND. OE is tied LOW. For FF and EF connections see Figure 17.
Figure 40. An 8,192 x 8 Parallel-In Serial-Out FIFO
SERIAL IN AND SERIAL OUT WITH WIDTH AND DEPTH EXPANSION
SICP
SI
VCC
6
D
SIX
SI SICP
IDT72104
SOX SO SOCP
D8
SIX
SI SICP
IDT72104
SOX SO SOCP
8
Q
6
Q
VCC
FULL
FLAG
EMPTY
FLAG
VCC
VCC
VCC
VCC
SI SICP
D8
SI SICP
D
6
SIX
XI XO
IDT72104
SOX SO SOCP
SIX
XI XO
IDT72104
SOX SO SOCP
8
Q
6
Q
SOCP
SO
2753 drw 44
NOTE:
1. All RS pins are connected together. All OE pins are connected LOW. All SI/PI and SO/PO pins are grounded.
Figure 41. 131,072 x 1 Serial-In Serial-Out FIFO
29
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXXX
IDT
X
XXX
X
X
DeviceType Power
Speed
Package
Process/
Temperature
Range
Blank Industrial (-40°C to +85°C)
J
Plastic Leaded Chip Carrier (PLCC, J44-1)
35
50
(50MHz serial shift rate)
(40MHz serial shift rate)
L
Low Power
2,048 x 9-Bit Configurable Parallel-Serial FIFO
4,096 x 9-Bit Configurable Parallel-Serial FIFO
72103
72104
2753 drw 45
30
相关型号：
IDT72104L50P
FIFO, 4KX9, 50ns, Asynchronous, CMOS, PDIP40, 0.600 INCH, 0.100 INCH PITCH, PLASTIC, DIP-40
IDT
©2020 ICPDF网 联系我们和版权申明