IDT7210L40J [IDT]
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR; 16 ×16并行CMOS乘法累加器
| 型号： | IDT7210L40J |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR |
| 文件： | 总10页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7210L
16 x 16 PARALLEL CMOS
MULTIPLIER-ACCUMULATOR
Integrated Device Technology, Inc.
FEATURES:
• 16 x 16 parallel multiplier-accumulator with selectable
accumulation and subtraction
• High-speed: 20ns multiply-accumulate time
DESCRIPTION:
TheIDT7210isahigh-speed,low-power16x16-bitparallel
multiplier-accumulatorthatisideallysuitedforreal-timedigital
signal processing applications. Fabricated using CMOS
• IDT7210 features selectable accumulation, subtraction, silicon gate technology, this device offers a very low-power
rounding and preloading with 35-bit result alternative to existing bipolar and NMOS counterparts, with
• IDT7210 is pin and function compatible with the TRW only 1/7 to 1/10 the power dissipation and exceptional speed
TDC1010J, TMC2210, Cypress CY7C510, and AMD (25ns maximum) performance.
AM29510
• Performs subtraction and double precision addition and IDT7210operatesfromasingle5voltsupplyandiscompatible
multiplication withstandardTTLlogiclevels.ThearchitectureoftheIDT7210
• Produced using advanced CMOS high-performance is fairly straightforward, featuring individual input and output
A pin and functional replacement for TRW’s TDC1010J the
technology
• TTL-compatible
registers with clocked D-type flip-flop, a preload capability
which enables input data to be preloaded into the output
• Available in topbraze DIP, PLCC, Flatpack and Pin Grid registers, individual three-state output ports for the Extended
Array
Product (XTP) and Most Significant Product (MSP) and a
Least Significant Product output (LSP) which is multiplexed
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-88733 is listed on this with the Y input.
function
The XIN and YIN data input registers may be specified
• Speeds available:
Commercial: L20/25/35/45/55/65
through the use of the Two’s Complement input (TC) as either
a two’s complement or an unsigned magnitude, yielding a full-
precision 32-bit result that may be accumulated to a full 35-bit
result. The three output registers – Extended Product (XTP),
Most Most Significant Product (MSP) and Least Significant
Product (LSP) – are controlled by the respective TSX, TSM
andTSLinputlines.TheLSPoutputcanberoutedthroughYIN
ports.
Military:
L25/30/40/55/65/75
FUNCTIONAL BLOCK DIAGRAM
ACC, SUB,
RND, TC
XIN
(X15-X0)
YIN
CLKX
CLKY (Y15-Y0/P15-P0)
16
4
16
CONTROL
REGISTER
XREGISTER
YREGISTER
MULTIPLIER ARRAY
+
32
TSL
+/–
ACCUMULATOR
PREL
35
35
16
XTP REGISTER MSP REGISTER
LSP REGISTER
CLKP
TSX
3
TSM
PREL
3
16
XTPOUT
(P34-P32)
MSPOUT
(P31-P16)
2577 drw 01
IDT7210
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
1995 Integrated Device Technology, Inc.
11.2
DSC-2018/7
1
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Continued)
TheAccumulateinput(ACC)enablesthedevicetoperform Productoutput(XTP)issignextendedinthetwo’scomplement
either a multiply or a multiply-accumulate function. In the mode or set to zero in the unsigned mode. The Round (RND)
multiply-accumulate mode, output data can be added to or control rounds up the Most Significant Product (MSP) and the
subtractedfrompreviousresults.WhentheSubtraction(SUB) 3-bit Extended Product (XTP) outputs. When Preload input
inputisactivesimultaneouslywithanactiveACC,asubtraction (PREL) is active, all the output buffers are forced into a high-
canbeperformed. Thedoubleprecisionaccumulatedresultis impedance state (see Preload truth table) and external data
rounded down to either a single precision or single precision can be loaded into the output register by using the TSX, TSL
plus 3-bit extended result. In the multiply mode, the Extended and TSM signals as input controls.
PIN CONFIGURATIONS
X
X
X
X
X
X
X
6
5
4
3
2
1
0
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
X
X
X
X
X
X
X
X
X
7
8
9
10
11
12
13
14
15
2
3
4
6059 58 575655 54 53 525150 4948 4746 45 44
5
6
P1, Y1 61
P0, Y0 62
X0 63
43 P17
42
41 P19
40 P20
39 P21
7
P18
P
0
,
,
,
,
,
,
8
P
P
P
P
P
1
2
3
4
5
9
X1 64
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TSL
X2 65
RND
SUB
ACC
CLKX
CLKY
38
X3 66
P22
X4 67
37 P23
X5 68
36
35
34
P24
P25
P26
P ,
P6
X6
X7
1
2
3
4
J68-1
7
,
GND
VCC
C64-2
X8
33 P27
P
P
8
9
,
,
,
,
,
,
,
,
TC
32
X9
P28
TSX
PREL
X10
X11
X12
X13
X14
5
6
7
8
9
31 P29
P
P
P
P
P
P
10
11
12
13
14
15
30
P30
P31
TSM
29
28 P32
27 P33
CLKP
P
P
34
P3323
1011 1213 14 1516 17 1819 20 2122 2324 25 26
P
16
17
18
19
20
21
22
23
P
P
P
P
P
P
P
P
31
30
29
28
27
26
25
24
2577 drw 03
P
P
P
P
P
P
P
PLCC
TOP VIEW
2577 drw 02
DIP
TOP VIEW
64636261605958575655 545352 515049
P16
P0, Y0
X0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47 P17
46 P18
45 P19
P20
P21
42 P22
41 P23
40 P24
39 P25
38 P26
X1
X2
X3
44
43
X4
X5
X6
X7
F64-1
X8
X9
X10
X11
X12
X13
37
P27
36 P28
35 P29
34 P30
33 P31
X14
17181920212223242526 272829 303132
2577 drw 04
FLATPACK
TOP VIEW
11.2
2
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11
10
09
08
07
06
05
04
03
02
01
NC
X15 RND ACC CLKY TC PREL CLKP P33
X13
X11
X9
X14 TSL SUB CLKX VCC TSX TSM P34
NC
P31
P32
P30
X12
X10
X8
P28
P26
P24
P22
P20
P29
P27
P25
P23
P21
P19
P17
X7
X5
X6
X4
X2
X0
G68-2
X3
X1
Y0,
P0
P18
P16
NC
Y1,
P1
Y3,
P3
Y5,
P5
Y7,
P7
Y8,
P8
Y10,
P10
Y12,
P12
Y14,
P14
NC
A
Y2,
P2
Y4,
P4
Y6,
P6
Y9,
P9
Y11,
P11
Y13,
P13
Y15,
P15
GND
Pin 1
Designator
B
C
D
E
F
G
H
J
K
L
PGA
2577 drw 05
TOP VIEW
PIN DESCRIPTIONS
Pin Name
I/O
Description
X0 - 15
I
Data Inputs
Y0 - 15/ P0 - 15
I/O
Multiplexed I/O port. Y0 - 15 are data inputs and can be used to preload LSP register on PREL = 1. P0 - 15
are LSP register outputs - enabled by TSL.
P16 - 31
P32 - 34
I/O
I/O
MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1.
XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when
PREL = 1.
CLKX
CLKY
CLKP
TSX
I
I
I
I
I
I
I
I
Input data X0 - 15 loaded in X input register on CLKX rising edge.
Input data Y0 - 15 loaded in Y input register on CLKY rising edge.
Output data loaded into output register on rising edge of CLKP.
TSX = 0 enables XTP outputs, TSX = 1 tristates P32 - 34 lines.
TSM = 0 enables MSP outputs, TSM = 1 tristates P16 - 31 lines.
TSL = 0 enables LSP outputs, TSL = 1 tristates P0 - 15 lines.
TSM
TSL
PREL
ACC
When PREL= 1 data is input on P0 - 15 lines. When PREL = 0, inputs on these lines are ignored.
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a
subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a
simple multipler with no accumulation
SUB
I
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted
from the result and stored back in the output register. When SUB = 0 the contents of the output register
are added to the result and stored back in the output register
TC
I
I
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y
inputs are assumed to be in unsigned magnitude form
RND
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and
XTP data
2577 tbl 01
11.2
3
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES ON TWO'S COMPLEMENT FORMATS
1. In two's complement notation, the location of the binary
point that signifies the separation of the fractional and
integer fileds is just after the sign, between the sign bit
(-2°) and the next significant bit for the multiplier inputs.
This same format is carried over to the output format,
except that the extended significance of the integer filed is
provided to extend the utility of the accumulator. In the
case of the output rotation, the output binary point is
PRELOAD TRUTH TABLE
PREL
TSX
TSM
TSL
XTP
Q
MSP
Q
LSP
Q
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
Q
Q
Hi Z
Q
0
1
0
Q
Hi Z
Hi Z
Q
0
1
1
Q
Hi Z
Q
1
0
0
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
PL
1
0
1
Q
Hi Z
Q
1
located between the2° and 2 bit positions. The location of
1
1
0
Hi Z
Hi Z
Hi Z
Hi Z
PL
the binary point is arbitrary, as long as there is consistency
with both the input and output formats. The number filed
can be considered entirely integer with the binary point just
to the right of the least significant bit for the input, product
and the accumulated sum.
1
1
1
Hi Z
Hi Z
PL
0
0
0
0
0
1
34
0
1
0
Hi Z
PL
2. When in the non-accumulating mode, the first four bits (P
31
to P ) will all indicate the sign of the product. Additionally,
the P term will also indicate the sign with one exception,
0
1
1
PL
30
1
0
0
Hi Z
Hi Z
PL
Hi Z
PL
when multiplying -1 x -1. With the additional bits that are
available in this multiplier, the –1 x –1 is a valid operation
that yields a +1 product.
1
0
1
PL
1
1
0
PL
Hi Z
3. In operations that require the accumulation of single prod-
ucts or sum of products, there is no change in format. To
allow for a valid summation beyond that available for a
single multiplication product, three additional significant
bits (guard bits) are provided. This is the same as if the
productwasaccumulatedoff-chipinaseparate35-bitwide
adder. Taking the sign at the most significant bit position
will guarantee that the largest number field will be used.
When the accumulated sum only occupies the right hand
portion of the accumulator, the sign will be extended into
the lesser significant bit positions.
1
1
1
1
PL
PL
PL
NOTES:
2577 tbl 02
Hi Z = Output buffers at high impedance (output disabled)
Q = Output buffers at low impedance. Contents of output register will be
transferred to output pins.
PL = Output buffers at high impedance or output disabled. Preload data
supplied externally at output pins will be loaded into the output
register at the rising edge of CLKP.
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Power Supply
Voltage
Commercial
Military
Unit
Symbol
Parameter(1)
Conditions
Max. Unit
VCC
-0.5 to +7.0
-0.5 to +7.0
V
CIN
Input Capacitance
VIN = 0V
10
12
pF
pF
COUT
Output Capacitance
VOUT = 0V
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
VCC +0.5V
–0.5 to
VCC +0.5V
V
NOTE:
2577 tbl 04
1. This parameter is measured at characterization and not 100%tested.
TA
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125 °C
TBIAS
TSTG
IOUT
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
50
50
mA
NOTE:
2577 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
11.2
4
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
Min. Typ.(1) Max.
Military
Min. Typ.(1) Max.
Unit
V
Symbol
Parameter
Input High Voltage
Test Conditions(5)
VIH
Guaranteed Logic HIGH Level 2.0
—
—
—
—
—
0.8
10
10
2.0
—
—
—
—
—
—
—
—
0.8
10
10
VIL
Input Low Voltage
Guaranteed Logic LOW Level
VCC = Max., VIN = 0V to VCC
—
—
—
V
|ILI|
|ILO|
Input Leakage Current
Output Leakage Current
µA
µA
VCC = Max., Outputs Disabled
VOUT = 0 to VCC
VOH
Output HIGH Voltage
VCC = Min., IOH = –2.0mA
2.4
—
—
—
—
45
—
0.4
-100
90
2.4
—
—
—
—
45
—
V
V
(4)
VOL
Output LOW Voltage
VCC = Min., IOL = 4mA
VCC = Max., V0 GND
0.4
IOS
Output Short Circuit Current
Operating Power Supply Current
-20
—
-20
—
-100
110
mA
mA
(2)
ICC
VCC = Max., Outputs Enabled
f= 10MHz(2)
CL = 50 pF
ICCQ1
ICCQ2
Quiescent Power Supply Current
Quiescent Power Supply Current
VIN ≥ VIH, VIN ≤ VIL
—
—
—
20
4
30
10
6
—
—
—
20
4
30
12
8
mA
mA
VIN ≥ VCC –0.2V, V IN ≤ 0.2V
ICC/f(2,3) Increase in Power Supply
Current MHz
VCC = Max., Outputs Disabled
—
—
mA/
MHz
NOTES:
2577 tbl 05
1. Typical implies VCC = 5V and TA = +25°C.
2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
ICC = 90+ 6(f –10)mA, where f = operating frequency in MHz. For the military range, ICC = 110 + 8(f –10). f = operating frequency in MHz, f = 1/tMA.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. IOL = 4mA for tMA > 55ns.
5. For conditions shown as Max. or Min., use appropriate value specified under electrical characteristics.
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V ± 10%, TA = 0° to +70°C)
7210L20 7210L25 7210L35 7210L45 7210L55 7210L65
Symbol
tMA
tD
Parameter
Multiply-Accumulate Time(2)
Output Delay(2)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.0 20 2.0 25 2.0 35 2.0 45 2.0 55 2.0 65
2.0 18 2.0 20 2.0 25 2.0 25 2.0 30 2.0 35
ns
ns
tENA
tDIS
tS
3-State Enable Time
3-State Disable Time(1)
Input Register Set-up Time
Input Register Hold Time
Clock Pulse Width
—
—
10
3
18
18
—
—
—
—
–
–
20
20
–
–
–
25
25
–
–
–
25
25
–
–
–
30
30
–
–
–
30
30
–
ns
ns
12
3
12
3
15
3
20
3
25
3
ns
tH
–
–
–
–
–
ns
tPW
tHCL
NOTES:
9
10
0
–
10
0
–
15
0
–
20
0
–
25
0
–
ns
Relative Hold Time
0
–
–
–
–
–
ns
2577 tbl 06
1. Transition is measured ±500mV from steady state voltage.
2. Minimum delays guaranteed but not tested
AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V ± 10%, TA = –55° to +125°C)
7210L25 7210L30 7210L40 7210L55 7210L65 7210L75
Symbol
tMA
tD
Parameter
Multiply-Accumulate Time(2)
Output Delay(2)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.0 25 2.0 30 2.0 40 2.0 55 2.0 65 2.0 75
2.0 20 2.0 20 2.0 25 2.0 30 2.0 35 2.0 35
ns
ns
tENA
tDIS
tS
3-State Enable Time
3-State Disable Time(1)
Input Register Set-up Time
Input Register Hold Time
Clock Pulse Width
—
—
12
3
20
20
—
—
—
—
–
–
20
20
–
–
–
25
25
–
–
–
30
25
–
–
–
30
30
–
–
–
35
30
–
ns
ns
12
3
15
3
20
3
25
3
25
3
ns
tH
–
–
–
–
–
ns
tPW
tHCL
NOTES:
10
0
10
0
–
15
0
–
20
0
–
25
0
–
25
0
–
ns
Relative Hold Time
–
–
–
–
–
ns
2577 tbl 07
1. Transition is measured ±500mV from steady state voltage.
2. Minimum delays guaranteed but not tested
11.2
5
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONTROL AND
INPUT
DATAIN
tS
tH
tPW
tMA
tHCL
INPUT
CLOCK
OUTPUT
CLOCK
tPW
PRELOAD
THREE-STATE
CONTROL
tDIS
tENA
HIGH IMPEDANCE
tDIS
tS
tH
tENA
DATAOUT
PRELOAD IN DATA
DATAOUT
OUTPUT
tD
Figure 1. Timing Diagram
11.2
6
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11.2
7
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11.2
8
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500Ω
VOUT
Enable Low
VIN
Pulse
Generator
Open
D.U.T.
All Other Tests
2577 lnk 09
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
50pF
C L
500Ω
T
R
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2577 drw 06
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
1.5V
ETC.
SYNCHRONOUS CONTROL
PRESET
3V
2577 drw 08
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
2577 drw 07
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2577 drw 09
0V
2577 drw 10
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
11.2
9
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
A
999
A
X
Device Type Power
Speed
Package
Process/
Temperature
Range
Blank
B
Commercial (0
°
C to +70
°C)
Military (–55 C to +125
°
°
C)
Compliant to MIL-STD-883, Class B
C
J
F
G
Topbraze DIP
Plastic Leaded Chip Carrier
Flatpack
Pin Grid Array
Com'l.
Mil.
25
30
20
25
35
45
55
65
40
Speed in Nanoseconds
55
65
75
L
Low Power
7210
16 x 16 Parallel Multiplier Accumulator
2577 drw 11
11.2
10
相关型号：
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