IDT72125L50SOG [IDT]
FIFO, 1KX16, 50ns, Synchronous, CMOS, PDSO28, SOIC-28;
| 型号： | IDT72125L50SOG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 1KX16, 50ns, Synchronous, CMOS, PDSO28, SOIC-28 先进先出芯片 光电二极管 |
| 文件： | 总10页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72105
IDT72115
IDT72125
CMOS PARALLEL-TO-SERIAL FIFO
256 x 16, 512 x 16, 1,024 x 16
Integrated Device Technology, Inc.
networks (LANs), video storage and disk/tape controller ap-
plications.
Expansion in width and depth can be achieved using
multiplechips. IDT’suniqueserialexpansionlogicmakesthis
possible using a minimum of pins.
Theuniqueserialoutputportisdrivenbyonedatapin(SO)
and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.
FEATURES:
• 25ns parallel port access time, 35ns cycle time
• 45MHz serial output shift rate
• Wide x16 organization offering easy expansion
• Low power consumption (50mA typical)
• Least/Most Significant Bit first read selected by asserting
the FL/DIR pin
• Four memory status flags: Empty, Full, Half-Full, and
Almost-Empty/Almost-Full
Monitoring the FIFO is eased by the availability of four
statusflags:Empty, Full, Half-FullandAlmost-Empty/Almost-
Full. TheFullandEmptyflagspreventanyFIFOdataoverflow
orunderflowconditions. TheHalf-FullFlagisavailableinboth
single and expansion mode configurations. The Almost-
Empty/Almost-Full Flag is available only in a single device
mode.
The IDT72105/72115/72125 are fabricated using IDT’s
leading edge, submicron CMOS technology. Military grade
productismanufacturedincompliancewiththelatestrevision
of Mil-STD-883, Class B.
• Dual-Port zero fall-through architecture
• Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
•
Industrial temperature range (–40°C to +85°C)
DESCRIPTION:
The IDT72105/72115/72125s are very high-speed, low-
power,dedicated, parallel-to-serial FIFOs. These FIFOs
possessa16-bitparallelinputportandaserialoutputportwith
256, 512 and 1,024 word depths, respectively.
The ability to buffer wide word widths (x16) make these
FIFOs ideal for laser printers, FAX machines, local area
FUNCTIONAL BLOCK DIAGRAM
D0–15
16
RESET
LOGIC
RAM
WRITE
POINTER
READ
POINTER
ARRAY
256 x 16
512 x 16
1,024 x 16
RSIX
RSOX
/DIR
EXPANSION
LOGIC
FLAG
LOGIC
SERIAL OUTPUT
LOGIC
2665 drw 01
SOCP
SO
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
INDUSTRIAL TEMPERATURE RANGE
DECEMBER 1999
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
©1999 Integrated Device Technology, Inc.
DSC-2665/-
1
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
D
D
D
0
1
2
D15
D14
D13
D12
D11
D10
3
4
5
D
3
6
D
D
D
D
4
7
5
8
6
7
D9
9
D8
10
11
12
13
14
SO
SOCP
RSO
/DIR
RSIX
GND
2665 drw 02
PLASTIC THIN DIP (P28-2, order code: TP)
SOIC (SO28-3, order code: SO)
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
D
0
–D15
Inputs
I
I
Data inputs for 16-bit wide data.
Reset
Write
When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM
array. FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE
after power-up. W must be high during the RS cycle. Also the First Load pin (FL) is programmed
only during Reset.
RS
I
A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up
and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the
RAM array sequentially and independently of any ongoing read operation.
W
SOCP
Serial Output
Clock
I
I
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
FL/DIR
First Load/
Direction
This is a dual purpose input used in the width and depth expansion configurations. The First
Load (FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first
device to be loaded with a byte of data. All other devices should be programmed HIGH. The
Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the
Least Significant or Most Significant bit first.
RSIX
SO
FF
Read Serial In
Expansion
I
In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain
expansion, RSIX is connected to RSOX (expansion out) of the previous device.
Serial Output
O
O
O
O
O
Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending
on the Direction pin programming. During Expansion the SO pins are tied together.
Full Flag
When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is
HIGH, the device is not full.
Empty Flag
Half-Full Flag
When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is
HIGH, the device is not empty.
EF
When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to
half-full.
HF
RSOX/AEF Read Serial
Out Expansion
Almost-Empty,
Almost-Full
This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEF
output pin. When AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When
AEF is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX
connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the
width, depth or daisy chain expansion.
Flag
V
CC
Power Supply
Ground
Single power supply of 5V.
GND
Single ground of 0V.
2665 tbl 01
2
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
STATUS FLAGS
Number of Words in FIFO
FF
H
H
H
H
H
L
AEF
L
HF
H
H
H
L
EF
L
IDT72105
0
IDT72115
0
IDT72125
0
1–31
1–63
1–127
L
H
H
H
H
H
32–128
129–224
225–255
256
64–256
257–448
449–511
512
128–512
513–896
897–1023
1024
H
H
L
L
L
L
2665 tbl 02
RECOMMENDED DC OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Unit
Symbol
Parameter
Supply Voltage
Supply Voltage
Input HIGH Voltage
Min. Typ. Max. Unit
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
V
VCC
4.5
0
5.0
0
5.5
0
V
V
V
GND
VIH
TSTG
Storage Temperature
DC Output Current
–55 to +125
–50 to +50
°C
2.0
—
—
IOUT
mA
2665 tbl 03
(1)
VIL
Input LOW Voltage
—
—
—
0.8
V
NOTE:
TA
Operating Temperature -40
+85
°C
2665 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
IDT72105
IDT72115
IDT72125
Industrial
Symbol
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic "1" Voltage IOUT = –2mA(3)
Output Logic "0" Voltage IOUT = 8mA(4)
Active Power Supply Current
Min.
–1
Typ.
Max.
1
Unit
µA
µA
V
(1)
ILI
—
(2)
ILO
–10
2.4
—
—
10
—
VOH
VOL
ICC1
ICC2
—
—
0.4
100
8
V
(5)
—
50
4
mA
mA
(5,6,7)
Standby Current
—
(W = RS = FL/DIR = VIH; SOCP = VIL)
(5,6,7)
ICC3
Power Down Current
—
1
6
mA
NOTES:
2665 tbl 05
1. Measurements with 0.4V ≤ VIN ≤ VCC.
2. SOCP = VIL, 0.4 ≤ VOUT ≤ VCC.
3. For SO, IOUT = –4mA.
4. For SO, IOUT = 16mA.
5. Tested with outputs open (IOUT = 0).
6. RS = FL/DIR = W = VCC - 0.2V; SOCP = 0.2V; all other inputs = VCC - 0.2.
7. Measurements are made after reset.
3
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5V±10%, TA = -40°C to +85°C)
INDUSTRIAL
72105L25
72115L25
72125L25
72105L50
72115L50
72125L50
Symbol
Parameter
Parallel Shift Frequency
Serial Shift Frequency
Figure
—
Min.
Max.
28.5
50
Min.
Max.
Unit
MHz
MHz
t
S
—
—
—
—
15
t
SOCP
—
40
PARALLEL INPUT TIMINGS
t
t
t
t
t
t
t
t
t
WC
Write Cycle Time
2
2
35
25
10
12
0
—
—
—
—
—
35
35
35
—
65
50
15
15
2
—
—
—
—
—
45
45
45
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
WPW
WR
Write Pulse Width
Write Recovery Time
Data Set-up Time
2
DS
2
DH
Data Hold Time
2
WEF
WFF
WF
Write High to EF HIGH
Write Low to FF LOW
Write Low to Transitioning HF, AEF
Write Pulse Width After FF HIGH
5, 6
4, 7
8
—
—
—
25
—
—
—
50
WPF
7
SERIAL OUTPUT TIMINGS
t
t
t
t
t
t
t
t
SOCP
SOCW
SOPD
SOHZ
SOLZ
Serial Clock Cycle Time
3
3
20
8
—
—
14
14
14
35
35
35
25
10
—
3
—
—
15
15
15
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock Width HIGH/LOW
SOCP Rising Edge to SO Valid Data
SOCP Rising Edge to SO at High-Z(1)
SOCP Rising Edge to SO at Low-Z(1)
SOCP Rising Edge to EF LOW
SOCP Rising Edge to FF HIGH
3
—
3
3
3
3
3
SOCEF
SOCFF
SOCF
5, 6
4, 7
8
—
—
—
—
—
—
SOCP Rising Edge to Transitioning
HF, AEF
t
REFSO
SOCP Delay After EF HIGH
6
35
—
65
—
ns
RESET TIMINGS
t
t
t
t
RSC
RS
Reset Cycle Time
Reset Pulse Width
Reset Set-up Time
Reset Recovery Time
1
1
1
1
35
25
25
10
—
—
—
—
65
50
50
15
—
—
—
—
ns
ns
ns
ns
RSS
RSR
EXPANSION MODE TIMINGS
t
t
t
t
t
FLS
FL Set-up Time to RS Rising Edge
FL Hold Time to RS Rising Edge
9
9
9
9
9
7
0
—
—
—
—
15
8
2
—
—
—
—
17
ns
ns
ns
ns
ns
FLH
DIRS
DIRH
SOXD1
DIR Set-up Time to SOCP Rising Edge
DIR Hold Time from SOCP Rising Edge
10
5
12
5
SOCP Rising Edge to RSOX Rising
Edge
—
—
t
t
t
SOXD2
SIXS
SOCP Rising Edge to RSOX Falling
Edge
9
9
9
—
5
15
—
—
—
8
17
—
—
ns
ns
RSIX Set-up Time to SOCP Rising
Edge
SIXPW
RSIX Pulse Width
10
15
ns
NOTE:
1. Values guaranteed by design.
2665 tbl 06
4
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
AC TEST CONDITIONS
5V
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns
1.5V
1.1KΩ
TO
OUTPUT
PIN
1.5V
See Figure A
30pF*
2665 tbl 07
680Ω
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
IN = 0V
OUT = 0V
Max. Unit
2665 drw 03
C
IN
Input Capacitance
V
10
12
pF
pF
or equivalent circuit
C
OUT
Output
V
Figure A. Output Load
Capacitance
*Includes jig and scope capacitances.
NOTE:
2665 tbl 08
1. Characterized values, not currently tested.
is incremented. Write operations can occur simultaneously or
asynchronously with read operations.
FUNCTIONAL DESCRIPTION
Parallel Data Input
The device must be reset before beginning operation so
that all flags are set to their initial state. In width or depth
expansion the First Load pin (FL) must be programmed to
indicate the first device.
The data is written into the FIFO in parallel through the D0–
15 input data lines. A write cycle is initiated on the falling edge
of the Write (W) signal provided the Full Flag (FF) is not
asserted. If the Wsignal changes from HIGH-to-LOW and the
Full Flag (FF) is already set, the write line is internally inhibited
internally from incrementing the write pointer and no write
operation occurs.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (EF)
isnotasserted.IftheEmptyFlagisassertedthenthenextdata
word is inhibited from moving to the output register and being
clocked out by SOCP.
The serial word is shifted out Least Significant Bit or Most
Significant Bit first, depending on the FL/DIR level during
operation. A LOW on DIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
Data set-up and hold times must be met with respect to the
rising edge of Write. On the rising edge of W, the write pointer
tRSC
t
RS
tRSS
tRSR
tRSC
FLAG
STABLE
t
RSC
FLAG
STABLE
tRSS
t
RSR
SOCP
/DIR
NOTE 2
tFLS
tFLH
2665 drw 04
NOTES:
1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at tRSC.
2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.
Figure 1. Reset
5
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
tWC
tWPW
tWR
t
DS
tDH
D0–15
2665 drw 05
Figure 2. Write Operation
1/t SOCP
0
1
n–1
SOCP
SO
t SOCW
t SOCW
(First Device in Width Expansion Mode)
t
SOHZ
tSOLZ
(Single Device Mode or Second
Device in Width Expansion Mode)
t
SOPD
SO
2665 drw 06
NOTE:
1. In Single Device Mode, SO will not tri-state except after reset.
Figure 3. Read Operation
IGNORED
WRITE
FIRST READ
ADDITIONAL READS FIRST WRITE
LAST WRITE
0
0
1
n–1
1
n–1
SOCP
tSOCFF
tWFF
2665 drw 07
Figure 4. Full Flag from Last Write to First Read
ADDITIONAL
WRITES
FIRST READ
LAST READ
NO READ
FIRST WRITE
0
1
n–1
0
1
n–1
NOTE 1
SOCP
tSOCFF
tSOCEF
tSOPD
VALID
VALID
VALID
SO
2665 drw 08
NOTE:
1. SOCP should not be clocked until EF goes HIGH.
Figure 5. Empty Flag from Last Read to First Write
6
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
DATA IN
tWEF
tSOCEF
tREFSO
0
1
n–1
NOTE 1
SOCP
tSOPD
tSOLZ
NOTE 2
SO
NOTES:
2665 drw 09
1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.
Figure 6. Empty Boundary Condition Timing
0
1
n–1
SOCP
t
SOCFF
tWFF
t
WPF
t
DS
tDH
DATA IN VALID
DATA IN
t
SOPD
NOTE 1
NOTE 1
DATA OUT VALID
SO
2665 drw 10
NOTE:
1. Single Device Mode will not tri-state but will retain the last valid data.
Figure 7. Full Boundary Condition Timing
HALF-FULL (1/2)
HALF-FULL
HALF-FULL + 1
tSOCF
tWF
SOCP
t
SOCF
tWF
7/8 FULL
7/8 FULL
ALMOST-FULL (7/8 FULL + 1)
1/8 FULL
ALMOST-EMPTY
(1/8 FULL – 1)
ALMOST-EMPTY
(1/8 FULL – 1)
2665 drw 11
Figure 8. Half-Full, Almost-Full and Almost-Empty Timings
7
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
15
0
SOCP
t
DIRS
tFLS
tFLH
t
DIRH
/DIR
tSOXD1
t
SOXD2
RSOX
t
SIXS
RSIXPW
t
RSIX
2665 drw 12
Figure 9. Serial Read Expansion
Width Expansion Mode
OPERATING CONFIGURATIONS
In the cascaded case, word widths of more than 16 bits can
be achieved by using more than one device. By tying the RSOX
and RSIX pins together, as shown in Figure 11, and program-
ming which is the Least Significant Device, a cascaded serial
word is achieved. The Least Significant Device is programmed
by a LOW on the FL/DIR pin during reset. All other devices
should be programmed HIGH on the FL/DIR pin at reset.
Single Device Mode
The device must be reset before beginning operation so
that all flags are set to location zero. In the standalone case,
the RSIX line is tied HIGH and indicates single device opera-
tion to the device. The RSOX/AEF pin defaults to AEF and
outputs the Almost-Empty and Almost-Full Flag.
PARALLEL DATA IN
D0–15
VCC
RSIX
RSOX
ALMOST-EMPTY/FULL FLAG
SERIAL OUTPUT CLOCK
SOCP
SO
SERIAL DATA OUT
2665 drw 13
Figure 10. Single Device Configuration
Inputs
Internal Status
Outputs
RS
FL
FF
1
HF
1
AEF EF
Mode
DIR
X
Read Pointer Write Pointer
,
Reset
0
X
X
Location Zero Location Zero
0
Read/Write
1
0,1
Increment(1)
Increment(1)
X
X
X
NOTE:
2665 tbl 09
1. Pointer will increment if appropriate flag is HIGH.
Table 1. Reset and First Load Truth Table–Single Device Configuration
The Serial Data Output (SO) of each device in the serial
The three flag outputs, Empty (EF), Half-Full (HF) and
word must be tied together. Since the SO pin is three stated, Full (FF), should be taken from the Most Significant Device (in
only the device which is currently shifting out is enabled and the example, FIFO #2). The Almost-Empty/Almost-Full flag is
driving the 1-bit bus. NOTE: After reset, the level on the not available. The RSOX pin is used for expansion.
FL/DIR pin decides if the Least Significant or Most Significant
Bit is read first out of each device.
8
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
SERIAL OUTPUT CLOCK
PARALLEL DATA IN
LOW AT RESET
HIGH AT RESET
D0–15
RSIX
D16–31
SOCP
FIFO #1
RSOX
/DIR
SOCP
FIFO #2
RSOX
/DIR
EMPTY FLAG
HALF-FULL FLAG
FULL FLAG
SO
RSIX
SO
SERIAL DATA OUT
2665 drw 14
Figure 11. Width Expansion for 32-bit Parallel Data In
Depth Expansion (Daisy Chain) Mode
The IDT72105/72115/72125 can easily be adapted to
applications requiring greater than 1,024 words. Figure 12
3. External logic is needed to generate composite Empty,
Half-Full and Full Flags. This requires the ORing of all EF,
HF and FF Flags.
demonstratesDepthExpansionusingthreeIDT72105/72115/ 4. The Almost-Empty and Almost-Full Flag is not available
72125s and an IDT74FCT138 Address Decoder. Any depth
can be attained by adding additional devices. The Address
due to using the RSOX pin for expansion.
Decoder is necessary to determine which FIFO is being Compound Expansion (Daisy Chain) Mode
written. A word of data must be written sequentially into each These FIFOs can be expanded in both depth and width as
FIFO so that the data will be read in the correct sequence. Figure 13 indicates:
These devices operate in the Depth Expansion Mode when
the following conditions are met:
1. The RSOX-to-RSIX expansion signals are wrapped
around sequentially.
1. The first device must be programmed by holding FL LOW
atReset.Allotherdevicesmustbeprogrammedbyholding
FL HIGH at reset.
2. The write (W) signal is expanded in width.
3. Flag signals are only taken from the Most Significant
Devices.
2. TheReadSerialOutExpansionpin(RSOX)ofeachdevice
must be tied to the Read Serial In Expansion pin (RSIX) of
the next device (see Figure 12).
4. The Least Significant Device in the array must be pro-
grammed with a LOW on FL/DIR during reset.
LOW AT RESET
PARALLEL DATA IN
D0–15
/DIR
RSIX
FIFO #1
EMPTY
FLAG
SOCP
RSOX
SO
00
01
10
ADDRESS
DECODER
74FCT138
HIGH AT RESET
D0–15
/DIR
RSIX
HALF-FULL
FLAG
FIFO #2
SERIAL OUTPUT CLOCK
SOCP
RSOX
SO
HIGH AT RESET
/DIR
D0–15
RSIX
FIFO #3
RSOX
FULL
FLAG
SOCP
SO
SERIAL DATA OUT
2665 drw 15
Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125
9
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
Inputs
Internal Status
Outputs
RS
FL
EF
HF FF
Mode
DIR
X
Read Pointer
Write Pointer
Location Zero
Location Zero
X
,
Reset-First Device
Reset All Other Devices
0
0
1
0
1
Location Zero
Location Zero
X
0
0
1
1
X
Read/Write
X
0,1
X
X
NOTE:
2665 tbl 10
1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half- Full Flag Output, FF = Full Flag Output.
Table 2. Reset and First Load Truth Table–Width/Depth Compound Expansion Mode
ADDRESS
DECODER
74FCT138
PARALLEL DATA IN
00 01 10
SERIAL OUTPUT CLOCK
LOW ON RESET
HIGH ON RESET
SOCP
/DIR
SOCP
/DIR
EMPTY
FLAG
D
D
D
0–15
D
D
D
16–31
FIFO #1
RSOX
FIFO #2
RSOX
RSIX
SO
RSIX
SO
SOCP
/DIR
SOCP
/DIR
0–15
16–31
HALF-FULL
FLAG
FIFO #3
RSOX
FIFO #4
RSOX
RSIX
SO
RSIX
SO
SOCP
/DIR
SOCP
/DIR
0–15
16–31
FIFO #5
RSOX
FIFO #6
RSOX
FULL
FLAG
RSIX
SO
RSIX
SO
SERIAL DATA OUT
2665 drw 16
Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
X
DeviceType
Package
Power
Speed
Process/
Temperature
Range
BLANK
Industrial (-40°C to +85°C)
TP
SO
Plastic Thin DIP (300mil, P28-2)
Small Outline IC (Gull Wing, SOIC, SO28-3)
25
50
(50 MHz serial shift rate)
(40MHz serial shift rate)
Parallel Access Time
(t ) in Nanoseconds
A
L
Low Power
72105
72115
72125
256 x 16-Bit Parallel-to-Serial FIFO
512 x 16-Bit Parallel-to-Serial FIFO
1,024 x 16-Bit Parallel-to-Serial FIFO
2665 drw 17
10
相关型号：
©2020 ICPDF网 联系我们和版权申明