IDT72142S50J [IDT]
FIFO, 4KX9, 50ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | IDT72142S50J |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 4KX9, 50ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总11页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72132
IDT72142
CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9 and 4,096 x 9
Integrated Device Technology, Inc.
FEATURES:
• 35ns parallel-port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 8, 9, 16-18, and
32-36 bit using Flexshift™ serial input without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-Port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low-power CMOS
technology
DESCRIPTION:
TheIDT72132/72142arehigh-speed, low-powerserial-to-
parallel FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). These devices can be configured with
the IDTs parallel-to-serial FIFOs (IDT72131/72141) for bidi-
rectional serial data buffering.
The FIFO has a serial input port and a 9-bit parallel output
port. Wider and deeper serial-to-parallel data buffers can be
built using multiple IDT72132/72142 chips. IDTs unique
Flexshift serial expansion logic (SIX, NW) makes width
expansion possible with no additional components. These
FIFOswillexpandtoavarietyofwordwidthsincluding8,9,16,
and 32 bits. These devices can also be directly connected for
depth expansion.
Five flags are provided to monitor the FIFO. The Full and
Empty flags prevent any FIFO data overflow or underflow
conditions.TheAlmost-Full(7/8),Half-Full,andAlmost-Empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72132/72142 is fabricated using IDTs high-speed
submicron CMOS technology.
• Available in the 28-pin plastic DIP
•
Industrial temperature range (–40oC to +85oC)
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
SICP
D7
D8
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
D7
SIX
SI
SERIAL INPUT
CIRCUITRY
2
GND
3
D8
FLAG
LOGIC
4
5
Q0
Q1
6
SI
RAM ARRAY
2,048 x 9
4,096 x 9
NEXT WRITE
POINTER
READ
POINTER
7
SICP
SIX
Q2
8
Q3
9
Q4
10
11
12
13
14
GND
GND
Q8
RESET
LOGIC
Q5
Q6
EXPANSION
LOGIC
Q7
0
8
Q -Q
2752 drw 01
2752 drw 02
PLASTIC DIP (P28-1, order code: P)
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 1999
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
©1999 Integrated Device Technology, Inc.
DSC-2752/-
1
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
SI
Serial Input
I
Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input
(SI) pins are tied together and SIX plus D7, D8 determine which device stores the data.
RS
Reset
I
When RS is set LOW, internal READ and WRITE pointers are set to the first location of the
RAMarray. HFandFFgoHIGH, andAEF, andEFgoLOW. Aresetisrequiredbeforeaninitial
WRITE after power-up. R must be HIGH during an RS cycle.
NW
Next Write
I
I
To program the Serial In word width , connect NW with one of the Data Set pins (D7, D8).
SICP
Serial Input Clock
Serial data is read into the serial input register on the rising edge of SICP. In both Depth and
Serial Word Width Expansion modes, all of the SICP pins are tied together.
R
Read
I
I
WhenREADisLOW,datacanbereadfromtheRAMarraysequentially,independentofSICP.
In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF-LOW), the
internal READ operation is blocked and Q0-Q8 are in a high impedance condition.
FL/RT
First Load/
Retransmit
This is a dual-purpose input. In the single device configuration (XI grounded), activating
retransmit (FL/RT-LOW) will set the internal READ pointer to the first location. There is no
effect on the WRITE pointer. R must be HIGH and SICP must be LOW before setting FL/RT
LOW. Retransmit is not possible in depth expansion. In the depth expansion configuration,
FL/RT grounded indicates the first activated device.
XI
Expansion In
I
I
In the single device configuration, XI is grounded. In depth expansion or daisy chain
expansion, XI is connected to XO (expansion out) of the previous device.
SIX
Serial Input
Expansion
In the Expansion mode, the SIX pin of the least significant device is tied HIGH. The SIX pin
of all other devices is connected to the D7 or D8 pin of the previous device. For single device
operation, SIX is tied HIGH.
OE
Output Enable
I
When OEis set LOW, the parallel output buffers receive data from the RAM array. When OE
is set HIGH, parallel three state buffers inhibit data flow.
Q0–Q8
FF
Output Data
Full Flag
O
O
Data outputs for 9-bit wide data.
When FF goes LOW, the device is full and data must not be clocked by SICP. When FF is
HIGH, the device is not full. See the diagram on page 7 for more details.
EF
Empty Flag
O
O
O
When EF goes LOW, the device is empty and further READ operations are inhibited. When
EF is HIGH, the device is not empty.
AEF
XO/HF
Almost-Empty/
Almost-FullFlag
WhenAEFis LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEFis HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
Expansion Out/
Half-Full Flag
This is a dual-purpose output. In the single device configuration (XI grounded), the device is
more than half full when HF is LOW. In the depth expansion configuration (XO connected to
XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array
is filled.
D7, D8
Data Set
O
The appropriate Data Set pin (D7, D8 ) is connected to NWto program the Serial In data word
width. For example: D7 - NW programs a 8-bit word width, D8 - NW programs a 9-bit word
width, etc.
VCC
Power Supply
Ground
Single Power Supply of 5V.
GND
Three grounds at 0V.
2752 tbl 01
STATUS FLAGS
Number of Words in FIFO
IDT72132
0
IDT72142
0
FF
H
H
H
H
H
L
AEF
L
HF
H
H
H
L
EF
L
1-255
1-511
L
H
H
H
H
256-1,024
1,025-1,792
1,793-2,047
2,048
512-2,048
2,049-3,584
3,585-4,095
4,096
H
H
L
L
L
L
H
2752 tbl 02
2
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage with
–0.5 to +7.0
V
VCC
Commercial Supply
Voltage
4.5
5.0
5.5
V
Respect to GND
GND
VIH
Supply Voltage
0
0
0
V
V
TSTG
IOUT
Storage Temperature
DC Output Current
–55 to +125
–50 to +50
°C
Input High Voltage
Commercial
2.0
—
—
mA
NOTE:
2752 tbl 03
(1)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VIL
Input Low Voltage
—
—
—
0.8
V
TA
Operating Temperature -40
Industrial
+85
°C
NOTE:
2752 tbl 04
1. 1.5V undershoots are allowed for 10ns once per cycle.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
Max.
10
Unit
pF
CIN
Input Capacitance
VIN = 0V
COUT
Output Capacitance VOUT = 0V
12
pF
NOTE:
1. Characterized values, not currently tested.
2752 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
IDT72132
IDT72142
Industrial
Symbol
Parameter
Min.
Typ.
Max.
Unit
IIL(1)
Input Leakage Current
(Any Input)
–1
—
1
µA
IOL(2)
VOH
Output Leakage Current
–10
2.4
—
—
10
—
µA
Output Logic "1" Voltage,
IOUT = –2mA
V
VOL
Output Logic "0" Voltage,
IOUT = 8mA
—
—
0.4
V
ICC1(3)
ICC2(3,4)
Active Power Supply Current
—
—
90
8
140
12
mA
mA
Standby Current
(R = RS = FL/RT = VIH; SICP = VIL)
ICC3(3,4)
Power Down Current
—
—
2
mA
NOTES:
2752 tbl 06
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≤ VIL, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RS = FL/RT = R = VCC -0.2V; SICP ≤ 0.2V; all other inputs = VCC - 0.2V or GND + 0.2V, which toggle at 20 MHz.
3
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
Industrial
IDT72132L35 IDT72132L50
IDT72142L35 IDT72142L50
Symbol
tS
Parameter
Parallel Shift Frequency
Serial-InShift Frequency
Min.
—
Max.
22.2
50
Min.
—
Max.
Unit
MHz
MHz
15
40
tSICP
—
—
PARALLEL OUTPUT TIMINGS
tA
Access Time
—
10
35
45
5
35
—
—
—
—
20
—
15
—
20
—
15
50
65
10
—
5
50
—
—
—
—
30
—
15
—
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRR
Read Recovery Time
tRPW
tRC
Read Pulse Width
Read Cycle Time
tRLZ
tRHZ
tDV
Read Pulse LOW to Data Bus at Low-Z(1)
Read Pulse HIGH to Data Bus at High-Z(1)
Data Valid from Read Pulse HIGH
Output Enable to High-Z (Disable)(1)
Output Enable to Low-Z (Enable)(1)
Output Enable to Data Valid (Q0-8)
—
5
tOEHZ
tOELZ
tAOE
—
5
—
5
—
—
SERIAL INPUT TIMINGS
tSIS
Serial Data in Set-Up Time to SICP Rising Edge
12
0
—
—
—
—
15
0
—
—
—
—
ns
ns
ns
ns
tSIH
Serial Data in Hold Time to SICP Rising Edge
SIX Set-Up Time to SICP Rising Edge
Serial-In Clock Width HIGH/LOW
tSIX
5
5
tSICW
8
10
FLAG TIMINGS
tSICEF
tSICFF
tSICF
tRFFSI
tREF
SICP Rising Edge (Last Bit - First Word) to EF HIGH
—
—
—
15
—
—
—
35
45
30
45
—
30
30
45
—
—
—
—
15
—
—
—
50
65
40
65
—
45
45
65
—
ns
ns
ns
ns
ns
ns
ns
ns
SICP Rising Edge (Bit 1 - Last Word) to FF LOW
SICP Rising Edge to HF, AEF
Recovery Time SICP After FF Goes HIGH
Read LOW to EF LOW
tRFF
Read HIGH to FF HIGH
tRF
Read HIGH to Transitioning HF and AEF
Read Pulse Width After EF HIGH
tRPE
RESET TIMINGS
tRSC
tRS
Reset Cycle Time
45
35
35
10
—
—
20
5
—
—
—
—
45
45
—
17
65
50
50
15
—
—
35
5
—
—
—
—
65
65
—
20
ns
ns
ns
ns
ns
ns
ns
ns
Reset Pulse Width
tRSS
tRSR
tRSF1
tRSF2
tRSDL
tPOI
Reset Set-up Time
Reset Recovery Time
Reset to EF and AEF LOW
Reset to HF and FF HIGH
Reset to D LOW
SICP Rising Edge to D
RETRANSMIT TIMINGS
tRTC
tRT
Retransmit Cycle Time
45
35
35
10
—
—
—
—
65
50
50
15
—
—
—
—
ns
ns
ns
ns
Retransmit Pulse Width
Retransmit Set-up Time
Retransmit Recovery Time
tRTS
tRTR
DEPTH EXPANSION MODE TIMINGS
tXOL
tXOH
tXI
Read/Write to XO LOW
Read/Write to XO HIGH
XI Pulse Width
—
—
35
10
16
40
40
—
—
—
—
—
50
10
15
50
50
—
—
—
ns
ns
ns
tXIR
XI Recovery Time
XI Set-up Time
ns
tXIS
ns
NOTE:
2752 tbl 07
1. Guaranteed by design minimum times, not tested
4
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
AC TEST CONDITIONS
5V
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns
1.5V
1.1KΩ
1.5V
D.U.T.
680Ω
See Figure A
2752 tbl 08
30pF*
2752 drw 03
or equivalent circuit
Figure A. Output Load
*Includies jig and scope capacitances
FUNCTIONAL DESCRIPTION
Serial Data Input
Parallel Data Output
A read cycle is initiated on the falling edge of Read (R)
The serial data is input on the SI pin. The data is clocked
in on the rising edge of SICP providing the Full Flag (FF) is not provided the Empty Flag is not set. The output data is
asserted. IftheFullFlagisassertedthenthenextparalleldata accessed on a first-in/first-out basis, independent of the
word is inhibited from moving into the RAM array. NOTE: ongoing write operations. The data is available tA after the
SICP should not be clocked once the last bit of the last word falling edge of R and the output bus Q goes into high imped-
has been shifted in, as indicated by NW HIGH and FF LOW. ance after R goes HIGH.
If it is, then the input data will be lost.
Alternately, the user can access the FIFO by keeping R
The serial word is shifted in Least Significant Bit first. Thus, LOW and enabling data on the bus by asserting Output
when the FIFO is read, the Least Significant Bit will come out Enable (OE). When Ris LOW, the OE signal enables data on
on Q0 and the second bit is on Q1 and so on. The serial word the output bus. When R is LOW and OE is HIGH, the output
width must be programmed by connecting the appropriate bus is three-stated. When R is HIGH, the output bus is
Data Set line (D7, D8) to the NW input. The data set lines are disabled irrespective of OE.
taps off a digital delay line. Selecting one of these taps
programs the width of the serial word to be written in.
t
t
RSC
RSS
t
RS
0
n-1
(1)
t
RSR
SICP
t
RSS
t
t
RSF1
RSF2
t
PDI
t
RSDL
7
8
D ,D
2752 drw 04
NOTE:
1. Input bits are numbered 0 to n-1. D7 and D8 correspond to n=8 and n=9 respectively
Figure 1. Reset
5
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
t
SICW
1
tSICW
(1)
0
2
n – 1
SICP
1/t SICP
SIX
t
SIX
t
SIS
tSIH
SI
2752 drw 05
NOTE:
1. Input bits are numbered 0 to n-1.
Figure 2. Write Operation
tRC
t
RR
t
RPW
t
A
tRHZ
t
RLZ
tDV
Q
0–8
VALID DATA
2752 drw 06
Figure 3. Read Operation
t
RC
tRR
TERMINATEREADCYCLE
tA
SECOND READ BY CONTROLLIN
AOE
t
t
RLZ
t
DV
t
OEHZ
t
OELZ
Q
0–8
DATA 1
DATA 1
2752 drw 07
Figure 4. Output Enable Timings
LAST WRITE
NO WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
0
1
n – 1
0
1
n – 1
SICP
(1)
tSICFF
t
RFF
2752 drw 08
NOTE:
1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
Figure 5. Full Flag from Last Write to First Read
6
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
0
1
n – 1
0
1
n – 1
SICP
tSICEF
t
REF
A
t
DATAOUT
VALID
VALID
2752 drw 09
Figure 6. Empty Flag from Last Read to First Write
FIRST SERIAL-IN WORD
SECOND SERIAL-IN WORD
0
1
n – 1
0
1
n – 1
0
SICP
t
SICEF
t
RPE
tA
DATAOUT
2752 drw 10
Figure 7. Empty Boundry Condition Timing
t
RFF
tSICFF
t
RFFSI
0
1
n – 1
SICP
SI
(1)
tSIS
tA
DATAOUT
2752 drw 11
NOTE:
1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
Figure 8. Full Boundry Condition Timing
7
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
0
1
n – 2
n – 1
SICP
HALF-FULL
HALF-FULL
tSICF
HALF-FULL + 1
t
t
RF
RF
tSICF
7/8 FULL
7/8 FULL
ALMOST-FULL (7/8 + 1)
1/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
ALMOST-EMPTY
(1/8 FULL-1)
2752 drw 12
Figure 9. Half-Full, Almost-Full and Almost-Empty Timings
t
RTC
t
RT
0
1
t
RTS
t
RTR
SICP
tRTS
FLAG VALID
2752 drw 13
NOTE:
1. EF, AEF, HF and FF may change status during Retransmit, but flags will be valid at tRTC.
Figure 10. Retransmit
WRITE TO LAST PHYSICAL LOCATION
n – 1
0
1
SICP
READ FROM LAST
PHYSICAL LOCATION
t
XOH
tXOH
t
XOL
tXOL
2752 drw 14
Figure 11. Expansion-Out
8
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
t
XI
tXIR
t
XIS
0
1
n – 1
SICP
Read from
physical location
t
XIS
Write to first
physical location
2752 drw 15
Figure 12. Expansion-In
Data Set lines (D7, D8) go LOW and a new serial word is
started. The Data Set lines then go HIGH on the equivalent
SICP clock pulse. This continues until the D line connected to
NW goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SICP.
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SIX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SICP clock, both of the
SERIAL DATA IN
SI
SICP
SIX
Q0-8
PARALLEL DATA OUTPUT
GND
SERIAL INPUT CLOCK
VCC
D7 D8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
SICP
D
7
8
D
2752 drw 16
Figure 13. Nine-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs
Internal Status
Outputs
Mode
Reset
RS
0
FL/RT
XI
0
Read Pointer
Write Pointer
Location Zero
Unchanged
AEF, EF
FF
1
HF
X
0
1
Location Zero
Location Zero
Increment(1)
0
X
X
1
Retransmit
Read/Write
NOTE:
1
0
X
X
1
0
Increment(1)
X
X
2752 tbl 09
1. Pointer will increment if appropriate flag is HIGH.
9
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
Width Expansion Configuration
On the first LOW-to-HIGH clock edge of SICP, both the
In the cascaded case, word widths of more than 9 bits can Data Set lines go LOW. Just as in the standalone case, on
be achieved by using more than one device. By tying the SIX each corresponding clock cycle, the equivalent Data Set line
line of the least significant device HIGH and the SIX of the goes HIGH in order of least to most significant.
subsequent devices to the appropriate Data Set lines of the
previous devices, a cascaded serial word is achieved.
SERIAL DATA IN
8
PARALLEL
SI
SI
DATA OUT
8
Q
0-7
Q
0-7
8
SICP
SIX
FIFO #1
SICP
SIX
FIFO #2
SERIAL-IN CLOCK
V
CC
D7
D7
0
1
7
8
9
10
14
15
0
SOCP
D
7
OF FIFO #1
AND SIX OF
FIFO #2
D7 OF FIFO #2
AND
TO
FIFO #1 AND
FIFO #2
2752 drw 17
Figure 14. Serial-In to Parallel-Out Data of 16 Bits
Depth Expansion (Daisy Chain) Mode
The IDT72132/72142 can be easily adapted to applica- 3. The Expansion Out (XO) pin and Expansion In (XI) pin
tionswheretherequirementsareforgreaterthan2,048/4,096 of each device must be tied together.
words. Figure 15 demonstrates Depth Expansion using three 4. External logic is needed to generate a composite Full
2. All other devices must have FL in the high state.
IDT72132/72142. Any depth can be attained by adding
additional IDT72132/72142 operates in the Depth Expansion
configuration when the following conditions are met:
1. The first device must be designated by grounding the
First Load (FL) control input.
Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (i.e., all must be
set to generate the correct composite (FF) or (EF).
5. The Retransmit (RT) function and Half-Full Flag (HF)
are not available in the Depth Expansion mode.
Q0-7
Q0-7
VCC
SIX
FIFO #1
IDT72142
R
7
D
SI
SI
SICP
SICP
Q
0-7
VCC
FIFO #2
IDT72142
R
SIX
7
D
SICP
SI
2752 drw 18
Figure 15. An 8K x 8 Serial-In Parallel-Out FIFO
10
IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO
2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
TABLE 2: RESET AND FIRST LOAD TRUTH TABLE —
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
FL/RT
0
Internal Status
Outputs
Mode
RS
0
XI
Read Pointer
Write Pointer
EF
0
FF
1
Reset-First
Device
(1)
Location Zero
Location Zero
Reset all
Other Devices
0
1
1
(1)
(1)
Location Zero
X
Location Zero
X
0
1
Read/Write
X
X
X
NOTES:
2752 tbl 10
1. XI is connected to XO of the previous device.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output, XI = Expansion Input.
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL
DATA IN
VCC
7
D
SI
SI
SI
SIX
D7
SIX
D7
SIX
SICP
SICP
SICP
Q0-7
Q0-7
Q0-7
VCC
D7
7
D
SIX
D
7
SIX SI
SICP
SIX
SI
SI
SERIAL
INPUT
CLOCK
SICP
SICP
READ
Q0-7
Q0-7
Q0-7
P0-7
P8-15
PARALLEL DATA OUT
Figure 16. An 8K x 24 Serial-In, Parallel-Out FIFO Using Six IDT72142s
P16-23
2752 drw 19
ORDERING INFORMATION
IDT
XXX
XXXXX
X
X
X
Package
Process/
Temperature
Range
Device Type Power
Speed
Blank
P
Industrial (-40°C to +85°C)
Plastic DIP (P28-1)
35
50
(50MHz serial shift rate)
(40MHz serial shift rate)
Parallel Access Time (t A)
L
Low Power
72132
72142
2,048 x 9-Bit Serial-Parallel FIFO
4,096 x 9-Bit Serial-Parallel FIFO
2752 drw 20
11
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